Hi all,
I just wanted to ask about the current status of the Supermicro X11-series of boards.
I read on a German magazine that it should be supported by joint efforts of 9elements and Mullvad. Link (auto-translated):
https://translate.google.com/translate?hl=&sl=de&tl=en&u=https%3A%2F%2Fwww.…
Apparently there was a presentation planned at the OSFC 2019, but I can't find anything on it and the boards-list still shows them as status "Unknown", which seems odd.
Does somebody have any infos on the current development with these boards?
Kind regards!
Maybe it is not a 100% suitable quesion. I assume big boys in coreboot know this.
[cid:1fe4e7e2-ae0a-4631-8340-d284b41a2f9d]
When I check the interrupt of network device in Windows 10, it says the IRQ is 0xFFFFFFDC(-36).
I am confused about this minus. What does it mean? Is it MSI?
Thanks.
Zheng
Hello Coreboot,
I am looking at upgrading a Lenovo T60 that has a 4 year old Libreboot
installed. Looking to try git master today, I find myself tracking down
some details of how the old version was built. While the included
.config is invaluable, I'm getting a few ideas for improvements.
-CBFS total size, visible in bootblock. Some platforms do not have the
entire flash chip address space decoded after power on reset. While
this could be inferred from knowledge of make and model, a reliable and
generic test would use a marker in the bootblock (and possibly something
at the start of the flash part can be probed to confirm the mapping), at
least for platforms where the reset vector it at top of (flash) memory.
I haven't thought out the details but probably something can be made for
low address reset vector platforms. Perhaps a flag in CBFS header to
indicate which as a clue to cbfstool. Being size aware could also be
used when swapping a flash chip to a different size.
-the .config is overwritten when added to coreboot.rom via CBFS at the
end of the build (if you choose that option)... should this be a
separate file for each of fallback and normal? Since there can be two
different versions and/or configurations, would fallback/config and
normal/config make more sense? Also the "revision" file might benefit
from similar treatment. Need to look into cmos* files also.
-similarly, platforms with a top-swap like Intel, could have 2 different
bootblock versions, so perhaps a subset of .config relevant to
bootblock, and a version marker, could go in the same swap-block as each
bootblock?
-embed the top-swap feature presence, and block size. I haven't checked
the code, but the cbfstool -j topswap-size and --ibb features are
related, if they don't implement this already. CBFS files should
optionally not span these block boundaries.
-embed flash chip relative offset, in bootblock (of each top-swap area),
to be able to probe if top-swap is active at any given moment.
-flash erase block size could be indicated in CBFS header. This can
have 2 uses, a) for alignment and padding when adding files, and b)
when flashing for a different part, to detect when cbfs should be
rebuilt with new padding and alignment. These may not be of use yet,
but I can envision an enhanced "flashrom -i <layoutfile>" that uses a
libcbfs to flash individual files, which would benefit knowing the erase
size the supplied CBFS was build for.
Perhaps each should be discussed in a separate thread, I'll leave that
to others' discretion.
Regards,
Jeremy
Hi, admin of gerrit,
I tried to add my working mail address zheng.bao(a)amd.com<mailto:zheng.bao@amd.com> to my gerrit account. But it says it is used by another account.
I am pretty sure that is because I tried to use this mail address to create an account, but can not login by authorization.
I have forgot the account name and other information.
Is there any way to find out that account and delete it? Thanks.
Zheng
Good morning, everyone,
I hadn't updated my coreboot version for a long time on my Asrock
E350M1 card because of lack of time and because this one was on a very
stable version. While trying to test the current 4.12 version, I
encountered problems in Debian 10.
Indeed, there is a bad graphical detection, the resolution of my hdmi
output went from 1360x768 to 720x400 pixels.
Xorg indicates that the drm device cannot be opened :
(EE) open /dev/dri/card0: No such file or directory
I once had a Oops kernel message:
https://pastebin.com/uZLZyYrq
My coreboot graphical configuration is as follows:
CONFIG_VGA_BIOS_ID="1002,9802"
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
CONFIG_VGA_BIOS=y
CONFIG_VGA_BIOS_FILE="vgabios.bin"
I manage to restore normal working in coreboot 4.12-git by removing the commits:
a5c2ac6256d0dae112b24c422d1270919acb6321 "x86/acpi: Add VFCT table"
6f978cfd1ab6a57e5729e19bed3df7702c4f09cb "x86/acpi: Use initialized
VBIOS in VFCT table"
Thank you. Best regards,
Loic
Hi Everyone,
I am currently working on a custom Denverton board similar to the Intel
Harcuvar board. CAR is working and the ROM stage is executing.
There should be console output on UART0, but it does not appear to be
initializing. There is a logic analyzer connected directly to the SOC UART
pins and the internal pull up can be seen working during hard strap
sampling, but after strap sampling TX goes low and stays low.
I have tried configuring it as both HSUART and legacy UART with early
console init both disabled and enabled and nothing has worked. Is there
anything that could be preventing the UART from initializing?
Thanks
Balaji
Hi,
I am trying to use the coreboot code on Intel Coffeelake-S RVP8 CRB board, but system can not boot completely and stop at post code 0x95.
First, system can boot to post code 0x94, and has a reboot, then stop at post code 0x95. Is there any idea about it?
I have used FSP from git or from Intel, and has the same fail. Does anybody know what’s the meaning of post code 0x95?
Thanks.
BR
Fred
Hi all,
Can someone give me some hints or point me to some instructions please?
Machine: Lenovo X1 Carbon 1st Gen (2012, no Boot Guard)
Flashing tool: CH341A USB programmer + Debian Linux
I am trying to replace the OEM firmware with Coreboot 4.12 and then install
OpenBSD into the machine and set it up as an internet facing firewall. I
ran me_cleaner against the dumped SPI image already.
1. Can anyone please tell let me know how can I achieve the captioned
objectives? I looked into ifdtool & uefitool but found nothing related to
my goal. I also tried the "lock ME/TXE" option during make menuconfig but
Intel chipsec is still reporting the captioned bits not set on my
Coreboot-flashed X1 Carbon
2. Is it correct to say that once the PR0-5 bits are set and Coreboot
flashed into the machine, the values of the PR registers will be configured
accordingly after machine boot up (when OS is having control)?
Thank you very much for looking into my questions!
Hi all,
Machine: Lenovo X1 Carbon 1st Gen (2012, no Boot Guard)
Flashing tool: CH341A USB programmer + Debian Linux
I am trying to replace the OEM firmware with Coreboot 4.12 and then install OpenBSD into the machine and set it up as an internet facing firewall. I ran me_cleaner against the dumped SPI image already.
1. Can anyone please tell let me know how I can achieve the captioned objectives? I looked into ifdtool & uefitool but found nothing related to my goal. I also tried the "lock ME/TXE" option during make menuconfig but Intel chipsec is still reporting the captioned bits not set on my Coreboot-flashed X1 Carbon.
2. Is it correct to say that once the PR0-5 bits are set and Coreboot flashed into the machine, the values of the PR registers will be configured accordingly after machine boot up (when OS is having control)?
Thank you for looking into my questions!
Hi Peter,
> Keith,
>
> Keith Hui wrote:
> > I had to upgrade the kernel from 4.4.14 to 5.4.42 for the i2c-scmi driver
> > to catch on. Then I was getting a shitload of invalid parameter errors
> > which eventually boils down to _SBW being expected to return a package of
> > one integer, instead of just an integer. Oops. I fixed that, but somehow
> > it's still not showing my devices. Gotta try harder.
>
> Just a note that it's interesting, fun and exciting to follow your progress!
>
> Keep up the good work. You'll get there.
Thanks for your encouragement!
***
Hi all,
After another 2 days I now have a working SCMI implementation on P3B-F
and can get readings from lm-sensors using i2c-scmi, with all relevant
vendor code connected to SCMI. I spent another few hours refactoring
so that it can be more easily extended to other southbridges. At this
point my use case is solved and I can submit and updated patch.
Now that I think more about it...
SCMI is sufficient for getting hwmon working on Linux, but for Windows
I don't know if eg. Speedfan can use it, or if it's even necessary.
The next step in the evolution of ACPI-based hardware monitoring on
ASUS mainboards would be ATK0110. It's an all-ACPI wrapper around
whatever hardware monitor chip is on the actual board. I could figure
out what methods I need to implement, and if I can make SCMI work, I
can make ATK0110 work too, but is it worth the effort?
Pros:
- Forget i2c-scmi and all the i2c crap, just load asus_atk0110 and go
- I can debug my work by overriding DSDT in Linux instead of flashing
- Possibility of wider adoption (use asus-atk0110 for all corebooted
[asus] boards)
Cons:
- My use case has been solved already
- May have to do scaling math that I don't fully understand. As it is,
some values (eg. 12V rail reading) don't make sense
- More hours, more grey hair falling off (:-P
- Who's using this board anyway?
Regards
Keith
