coreboot

coreboot@coreboot.org

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38917 discussions

Another day, another SMM loader vulnerability

by Arthur Heymans

Hi After last week's SMM loader problem on all but the BSP, I noticed another problem in the SMM setup. The permanent smihandler is currently built as a relocatable module such that coreboot can place it wherever it thinks it's a good idea. (TSEG is not known at buildtime). These relocatable modules have an alignment requirement. It looks however that the code to deal with the alignment requirement is also wrong and aligns the handler upwards instead of downwards which makes it encroach either an SSE2 FX_SAVE area or an SMM register save state. It's hard to know whether this is easily exploitable. I would think that a carefully crafted SMM save state on the right AP arbitrary code executing might be possible. On the other hand I noticed last week that launching SMM on APs is broken too so this is likely a lesser problem. Anyway the fix is in https://review.coreboot.org/c/coreboot/+/63475 (It has a comment indicating what code was causing this problem) Please review and update your coreboot code! Kind regards Arthur

1 day, 16 hours

Please test and review AGESA code

by Arthur Heymans

Hi We spend more time debating whether to keep AGESA in the master branch than actually reviewing code to maintains it. Here are some patches series I would like to be tested & reviewed: - Agesa was never properly linked and relied on default linker behavior to append unmatched data. Here is the fix: https://review.coreboot.org/q/topic:AGESA_DATA - Use MRC cache for non volatile data https://review.coreboot.org/q/topic:AGESA_MRC_CACHE - Use CLFLUSH to make sure code hits DRAM and incidently avoid inconsistent MTRRs (bonus is compressed postcar stage): https://review.coreboot.org/q/topic:compress_postcar Kind regards Arthur

5 days

Open Source Firmware Hackathon 2022

by Felix Singer

Hi everyone, after two crazy years, we decided it's time to do a open source firmware hackathon. It will take place from 10th June - 12th June in Darmstadt, Germany. For more details and tickets, have a look on this site [1]. The hackathon will cover open source firmware projects, like coreboot, oreboot, flashrom, LinuxBoot and any topics related to them. We have two lecture rooms (2x 80 people) for discussions and presentations. Currently, only 17 tickets are left. Everyone is welcome, no matter if beginner or professional. 24h breakfast, snacks and soft drinks are provided for free. Would love to see you there! // Felix [1] https://osfw.foundation/events/osff-summer-hackathon-2022/

6 days, 13 hours

[RFC] #pragma once

by Arthur Heymans

Hi To make sure headers don't create conflicts, guards are added to all of them. But the guard needs to be correct: e.g. https://review.coreboot.org/c/coreboot/+/64360/2 Most compilers implement '#pragma once ' as an alternative. Should we use this instead across the tree, as it is less error prone and less code? Sidenote: clang warns about wrong header guards. https://review.coreboot.org/c/coreboot/+/62173/23 hooks up clang to our CI for some platforms ;-). Kind regards Arthur

1 week

Re: Please test and review AGESA code

by Martin Roth

May 17, 2022, 11:40 by coreboot(a)coreboot.org: > Just my opinion, and I'm intentionally replying off list. > Oops. Or not. :-/

1 week

New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 5 new defect(s) introduced to coreboot found with Coverity Scan. 3 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 5 of 5 defect(s) ** CID 1488867: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/cpu/x86/mtrr/earlymtrr.c: 45 in var_mtrr_set() ________________________________________________________________________________________________________ *** CID 1488867: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /src/cpu/x86/mtrr/earlymtrr.c: 45 in var_mtrr_set() 39 min base bit set and maximum size bit set. */ 40 if (addr_lsb > size_msb) 41 mtrr_size = 1 << size_msb; 42 else 43 mtrr_size = 1 << addr_lsb; 44 >>> CID 1488867: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "(uint64_t)addr >> 32" is 0 regardless of the values of its operands. This occurs as the operand of assignment. 45 base.hi = (uint64_t)addr >> 32; 46 base.lo = addr | type; 47 mask.hi = upper_mask; 48 mask.lo = ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID; 49 ctx->mtrr[ctx->used_var_mtrrs].base = base; 50 ctx->mtrr[ctx->used_var_mtrrs].mask = mask; ** CID 1488866: (TAINTED_SCALAR) /util/amdfwtool/amdfwread.c: 121 in read_soft_fuse() /util/amdfwtool/amdfwread.c: 121 in read_soft_fuse() ________________________________________________________________________________________________________ *** CID 1488866: (TAINTED_SCALAR) /util/amdfwtool/amdfwread.c: 121 in read_soft_fuse() 115 &current_entries, &num_current_entries) != 0) 116 return 1; 117 118 while (1) { 119 uint32_t l2_dir_offset = 0; 120 >>> CID 1488866: (TAINTED_SCALAR) >>> Using tainted variable "num_current_entries" as a loop boundary. 121 for (size_t i = 0; i < num_current_entries; i++) { 122 uint32_t type = current_entries[i].type; 123 if (type == AMD_PSP_FUSE_CHAIN) { 124 uint64_t mode = current_entries[i].address_mode; 125 uint64_t addr = current_entries[i].addr; 126 uint64_t fuse = mode << 62 | addr; /util/amdfwtool/amdfwread.c: 121 in read_soft_fuse() 115 &current_entries, &num_current_entries) != 0) 116 return 1; 117 118 while (1) { 119 uint32_t l2_dir_offset = 0; 120 >>> CID 1488866: (TAINTED_SCALAR) >>> Using tainted variable "num_current_entries" as a loop boundary. 121 for (size_t i = 0; i < num_current_entries; i++) { 122 uint32_t type = current_entries[i].type; 123 if (type == AMD_PSP_FUSE_CHAIN) { 124 uint64_t mode = current_entries[i].address_mode; 125 uint64_t addr = current_entries[i].addr; 126 uint64_t fuse = mode << 62 | addr; ** CID 1488865: Integer handling issues (BAD_SHIFT) /src/cpu/x86/mtrr/earlymtrr.c: 45 in var_mtrr_set() ________________________________________________________________________________________________________ *** CID 1488865: Integer handling issues (BAD_SHIFT) /src/cpu/x86/mtrr/earlymtrr.c: 45 in var_mtrr_set() 39 min base bit set and maximum size bit set. */ 40 if (addr_lsb > size_msb) 41 mtrr_size = 1 << size_msb; 42 else 43 mtrr_size = 1 << addr_lsb; 44 >>> CID 1488865: Integer handling issues (BAD_SHIFT) >>> In expression "(uint64_t)addr >> 32", right shifting "addr" by more than 31 bits always yields zero. The shift amount is 32. 45 base.hi = (uint64_t)addr >> 32; 46 base.lo = addr | type; 47 mask.hi = upper_mask; 48 mask.lo = ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID; 49 ctx->mtrr[ctx->used_var_mtrrs].base = base; 50 ctx->mtrr[ctx->used_var_mtrrs].mask = mask; ** CID 1488864: (TAINTED_SCALAR) /util/amdfwtool/amdfwread.c: 91 in read_psp_directory() /util/amdfwtool/amdfwread.c: 92 in read_psp_directory() ________________________________________________________________________________________________________ *** CID 1488864: (TAINTED_SCALAR) /util/amdfwtool/amdfwread.c: 91 in read_psp_directory() 85 expected_cookie, header->cookie); 86 return 1; 87 } 88 89 /* Read the entries */ 90 *num_entries = header->num_entries; >>> CID 1488864: (TAINTED_SCALAR) >>> Passing tainted expression "16UL * header->num_entries" to "malloc", which uses it as an allocation size. [Note: The source code implementation of the function has been overridden by a builtin model.] 91 *entries = malloc(sizeof(psp_directory_entry) * header->num_entries); 92 if (fread(*entries, sizeof(psp_directory_entry), header->num_entries, fw) 93 != header->num_entries) { 94 ERR("Failed to read %d PSP entries\n", header->num_entries); 95 return 1; 96 } /util/amdfwtool/amdfwread.c: 92 in read_psp_directory() 86 return 1; 87 } 88 89 /* Read the entries */ 90 *num_entries = header->num_entries; 91 *entries = malloc(sizeof(psp_directory_entry) * header->num_entries); >>> CID 1488864: (TAINTED_SCALAR) >>> Passing tainted expression "header->num_entries" to "fread", which uses it as an offset. 92 if (fread(*entries, sizeof(psp_directory_entry), header->num_entries, fw) 93 != header->num_entries) { 94 ERR("Failed to read %d PSP entries\n", header->num_entries); 95 return 1; 96 } 97 ** CID 1488863: (RESOURCE_LEAK) /util/amdfwtool/amdfwread.c: 129 in read_soft_fuse() /util/amdfwtool/amdfwread.c: 152 in read_soft_fuse() /util/amdfwtool/amdfwread.c: 116 in read_soft_fuse() /util/amdfwtool/amdfwread.c: 129 in read_soft_fuse() ________________________________________________________________________________________________________ *** CID 1488863: (RESOURCE_LEAK) /util/amdfwtool/amdfwread.c: 129 in read_soft_fuse() 123 if (type == AMD_PSP_FUSE_CHAIN) { 124 uint64_t mode = current_entries[i].address_mode; 125 uint64_t addr = current_entries[i].addr; 126 uint64_t fuse = mode << 62 | addr; 127 128 printf("Soft-fuse:0x%lx\n", fuse); >>> CID 1488863: (RESOURCE_LEAK) >>> Variable "current_entries" going out of scope leaks the storage it points to. 129 return 0; 130 } else if (type == AMD_FW_L2_PTR) { 131 /* There's a second level PSP directory to read */ 132 if (l2_dir_offset != 0) 133 return 1; 134 /util/amdfwtool/amdfwread.c: 152 in read_soft_fuse() 146 /* Read the L2 PSP directory */ 147 if (read_psp_directory(fw, l2_dir_offset, PSPL2_COOKIE, &header, 148 &current_entries, &num_current_entries) != 0) 149 break; 150 } 151 >>> CID 1488863: (RESOURCE_LEAK) >>> Variable "current_entries" going out of scope leaks the storage it points to. 152 return 1; 153 } 154 155 enum { 156 AMDFW_OPT_HELP = 'h', 157 /util/amdfwtool/amdfwread.c: 116 in read_soft_fuse() 110 else 111 psp_offset = fw_header->new_psp_directory; 112 113 psp_directory_header header; 114 if (read_psp_directory(fw, psp_offset, PSP_COOKIE, &header, 115 &current_entries, &num_current_entries) != 0) >>> CID 1488863: (RESOURCE_LEAK) >>> Variable "current_entries" going out of scope leaks the storage it points to. 116 return 1; 117 118 while (1) { 119 uint32_t l2_dir_offset = 0; 120 121 for (size_t i = 0; i < num_current_entries; i++) { /util/amdfwtool/amdfwread.c: 129 in read_soft_fuse() 123 if (type == AMD_PSP_FUSE_CHAIN) { 124 uint64_t mode = current_entries[i].address_mode; 125 uint64_t addr = current_entries[i].addr; 126 uint64_t fuse = mode << 62 | addr; 127 128 printf("Soft-fuse:0x%lx\n", fuse); >>> CID 1488863: (RESOURCE_LEAK) >>> Variable "current_entries" going out of scope leaks the storage it points to. 129 return 0; 130 } else if (type == AMD_FW_L2_PTR) { 131 /* There's a second level PSP directory to read */ 132 if (l2_dir_offset != 0) 133 return 1; 134 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 week

coreboot 4.17 release planned for May 30th

by Martin Roth

The next quarterly release, 4.17 is targeted for May 30, 2022. Additionally, at that time, we plan to update the release packages and version numbers any of the coreboot branches which have been modified since they were released. Going forward, this should happen anytime there's a new release. Please test any boards that you have available. Current stats since the 4.16 release, 3 months ago (As of early Monday, May 16): Added 10 mainboards: ------------------- * Clevo L140MU / L141MU / L142MU * Dell Inc. Dell Precision T1650 * Google -> Craask * Google -> Gelarshie * Google -> Mithrax * Google -> Osiris * HP Z220 CMT Workstation * Star Labs Star Labs LabTop Mk IV (i3-10110U and i7-10710U) * Star Labs Star Labs Lite Mk III (N5000) * Star Labs Star Labs Lite Mk IV (N5030) Removed 2 mainboards: ------------------- * Google -> Deltan * Google -> Deltaur repo statistics ------------------- - Total Commits: 998 - Average Commits per day: 12.58 - Total lines added: 34473 - Average lines added per commit: 34.54 - Number of patches adding more than 100 lines: 40 - Average lines added per small commit: 22.35 - Total lines removed: 57663 - Average lines removed per commit: 57.78 - Total difference between added and removed: -23190 - Total authors: 131 - New authors: 17 Martin

1 week, 1 day

New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 2 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 2 of 2 defect(s) ** CID 1488815: Resource leaks (RESOURCE_LEAK) /src/drivers/usb/hub/acpi.c: 48 in usb_hub_add_ports() ________________________________________________________________________________________________________ *** CID 1488815: Resource leaks (RESOURCE_LEAK) /src/drivers/usb/hub/acpi.c: 48 in usb_hub_add_ports() 42 while ((port = dev_bus_each_child(dev->link_list, port)) != NULL) { 43 if (child_count++ >= config->port_count) { 44 printk(BIOS_WARNING, "%s cannot be added. Port Count limit reached.\n", 45 dev_name(port)); 46 continue; 47 } >>> CID 1488815: Resource leaks (RESOURCE_LEAK) >>> Failing to save or free storage allocated by "usb_hub_acpi_name(port)" leaks it. 48 acpigen_write_device(usb_hub_acpi_name(port)); 49 acpigen_write_name_byte("_ADR", port->path.usb.port_id + 1); 50 acpigen_write_device_end(); 51 } 52 } 53 ** CID 1488814: Uninitialized variables (UNINIT) ________________________________________________________________________________________________________ *** CID 1488814: Uninitialized variables (UNINIT) /src/soc/intel/alderlake/acpi.c: 307 in soc_lpi_get_constraints() 301 snprintf(path, sizeof(path), 302 CONFIG_ACPI_CPU_STRING, i); 303 break; 304 } 305 } 306 >>> CID 1488814: Uninitialized variables (UNINIT) >>> Using uninitialized value "*path" when calling "acpigen_emit_namestring". 307 acpigen_emit_namestring(path); 308 break; 309 310 default: 311 /* Unhandled */ 312 printk(BIOS_WARNING, ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 week, 4 days

Running coreboot on M1 Mac or Arm64 platforms

by Branden Waldner

> Dear coreboot community, > I just started coreboot and getting the hang of it. I am considering getting a M1 MacBook for my > development work. > May I will will coreboot work well on M1 MacBook? I am doing the coreboot work for x86 > platforms. > I understand that coreboot is using i386 cross GC Compiler, does it works on M1? There is > another option that I could run a Linux OS virtual box on M1 but it will still run on arm64 arc. > Thanks for the help. > Best Regards, > Cory I've built crossgcc-i386 on armv6 (raspberry pi B) and it produced a working rom for my asus/p2b. I don't know about how well it would work with any other targets though. Branden

1 week, 5 days

Will coreboot work on my machine? DELL XPS m1330

by Mateusz Kolbusz

1. a) Vendor: Dell b) Motherboard product: 0N6705 vendor: Dell Inc. c) Processor: Intel(R) Core(TM)2 Duo CPU T5800 @ 2.00GHz d) Bridge: Mobile PM965/GM965/GL960 Memory Controller Hub e) GPU: Mobile GM965/GL960 Integrated Graphics Controller (primary) 2. lspci -tvnn -[0000:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] +-02.0 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (primary) [8086:2a02] +-02.1 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller (secondary) [8086:2a03] +-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] +-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] +-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] +-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] +-1c.0-[0b]-- +-1c.1-[0c]----00.0 Qualcomm Atheros AR928X Wireless Network Adapter (PCI-Express) [168c:002a] +-1c.3-[0d-0e]-- +-1c.5-[09]----00.0 Broadcom Inc. and subsidiaries NetLink BCM5906M Fast Ethernet PCI Express [14e4:1713] +-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] +-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] +-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] +-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] +-1e.0-[03]--+-01.0 Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] | +-01.1 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] | +-01.2 Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter [1180:0592] | \-01.3 Ricoh Co Ltd xD-Picture Card Controller [1180:0852] +-1f.0 Intel Corporation 82801HM (ICH8M) LPC Interface Controller [8086:2815] +-1f.1 Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) IDE Controller [8086:2850] +-1f.2 Intel Corporation 82801HM/HEM (ICH8M/ICH8M-E) SATA Controller [AHCI mode] [8086:2829] \-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] 3. Superiotool -dV : [mateusz@mateusz superiotool]$ sudo superiotool -dV superiotool r4.16-884-gd4cdf5d581 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Aspeed Super I/O at 0x2e... Failed. Returned data: scratch registers all read as 0xff Probing for Aspeed Super I/O at 0x4e... Failed. Returned data: scratch registers all read as 0xff Probing for Exar Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Exar Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x20e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=it8987e) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x3201, rev=0x0 Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8987e) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x6e... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0xffff Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0xffff, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0x32, rev=0x01 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for VIA Super I/O (init=vt82c686) at 0x3f0... PCI device 1106:0686 not found. Probing for AMD EC Super I/O at 0xaa... Probing for Server Engines Super I/O at 0x2e... Failed. Returned data: id=0xffff, rev=0xff Probing for Infineon Super I/O at 0x2e... Failed. Returned data: id=0x32, rev=0x01 Probing for Infineon Super I/O at 0x4e... Failed. Returned data: id=0xff, rev=0xff No Super I/O found 4. flashrom -p internal -V flashrom v1.2 on Linux 5.17.5-arch1-1 (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.7.0, GCC 11.2.0, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Portable" Laptop detected via DMI. DMI string system-manufacturer: "Dell Inc." DMI string system-product-name: "XPS M1330 " DMI string system-version: "Not Specified" DMI string baseboard-manufacturer: "Dell Inc." DMI string baseboard-product-name: "0N6705" DMI string baseboard-version: " " Found chipset "Intel ICH8M" with PCI ID 8086:2815. Enabling flash write... Root Complex Register Block address = 0xfed18000 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000fed18000 /dev/mem mmap failed: Operation not permitted FAILED! FATAL ERROR! Error: Programmer initialization failed. It's has supported chipsed but not motherboard will it work anyway?

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