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[coreboot - Bug #579] (New) MAC address programmed by coreboot to onboard RTL8111F does not persist
by Keith Hui 23 Apr '25

23 Apr '25

Issue #579 has been reported by Keith Hui. ---------------------------------------- Bug #579: MAC address programmed by coreboot to onboard RTL8111F does not persist https://ticket.coreboot.org/issues/579 * Author: Keith Hui * Status: New * Priority: Normal * Category: chipset configuration * Target version: none * Start date: 2025-03-01 * Related links: https://review.coreboot.org/c/coreboot/+/86172 * Affected hardware: Asus P8Z77-V LE PLUS w/ RTL8111F * Affected OS: Linux kernel 6.12.7 ---------------------------------------- I am producing a coreboot port on Asus P8Z77-V LE PLUS on which this issue is observed. It has a RTL8111F ethernet controller without EEPROM for vital product data. I enabled the rtl8168 driver in coreboot so I can configure the LEDs and MAC address. Lights work great, but the MAC address always revert to `00:00:00:00:00:05` by the Linux r8169 kernel module. I would then have to reassign its proper MAC address using `ip link change eno0 address <mac>`. The device appears to be taking the address I programmed, but r8169 reverts it both on init and teardown, insisting that `00:00:00:00:00:05` is its permanent MAC address. Survival of coreboot programmed MAC address before r8169 driver is confirmed by a debug read back I inserted in the coreboot rtl81xx driver, as well as by temporarily blacklisting r8169. Vendor firmware is unaffected. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Memory map and type 13 (Fwd: Re: e820: Undefined type not treated as AddressRangeReserved)
by Paul Menzel 23 Apr '25

23 Apr '25

Dear coreboot folks, Some payloads, like GRUB [1] and formerly FILO [2], convert coreboot’s memory map(?) to E820 table, and copy the type 13. Currently, the Linux kernel does not follow the ACPI specification to treat the undefined types as AddressRangeReserved, so `cbmem` does not work, which can be worked around with `iomem=relaxed`. I brought this up to the Linux x86 maintainers, and Ingo Molnar kindly responded [attached, 3], and asked: > Just curious: why do they mark it type 13? What semantics do they > expect? It's not just some random value I suspect. Could somebody of the experts here shed some light on this? Thank you and kind regards, Paul PS: Ingo also prepared some patches to make Linux follow the ACPI specification [4]. [1]: https://ticket.coreboot.org/issues/590 [2]: https://review.coreboot.org/c/filo/+/51120 [3]: https://lore.kernel.org/all/aADkQoJE62OdWMhu@gmail.com/ [4]: https://lore.kernel.org/all/20250421185210.3372306-1-mingo@kernel.org/

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[coreboot - Support #581] (New) success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template
by Walter Sonius 23 Apr '25

23 Apr '25

Issue #581 has been reported by Walter Sonius. ---------------------------------------- Support #581: success new variant "compaq_pro_6300_sff" for hp/snb_ivb_desktops compatible with "compaq_8300_elite_sff" template https://ticket.coreboot.org/issues/581 * Author: Walter Sonius * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2025-03-15 ---------------------------------------- Successful flash and coreboot SeaBIOS functioning of a HP "compaq_pro_6300_sff" with a unchanged "compaq_8300_elite_sff" template using coreboot (24.12-758-g1e7ba810c6bb) and SeaBIOS (version rel-1.16.3-0-ga6ed6b70). These two HP Compaq devices are extremely similar, they use the same OEM proprietary BIOS upgrade files. Hardware wise the only 3 noticeable differences are that the "compaq_8300_elite_sff" comes with a Q77 chipset, SuperIO NPCD378 and J32 labeled 16x length "white" PCI-E slot versus a Q75 chipset, SuperIO NPCD379HAKFX with the J32 labeled slot populated with a limited physical 1x length "black" PCI-E slot on the "compaq_pro_6300_sff". Flashing from OEM proprietary BIOS 3.08revA enabling the FDO jumper on the motherboard as described for the compaq_8300_elite_sff works by booting with "iomem=relaxed" kernel parameter and specifying the specific 16MB chip 25Q128A: flashrom -p internal -w cbtest.rom -c "MT25QL128" Tested and Working: Poweron/Poweroff/Reboot CPU i3-3220 / e3-1225v2 RAM 1x 2x 4x populated slots total of 4GB/8GB/16GB/24GB (both 1.35v and 1.5v modules mixed with ECC) Serial port (including coreboot) PS2 keyboard (including SeaBIOS) PS2 mouse SATA 3 ports (blue/white/white) USB 2.0 4x front & 2x back ports USB 3.0 4x back ports Ethernet 1Gbit/100Mbit Display port works in SeaBIOS and OS VGA port only works in OS! PCI using realtek RTL8169 1Gb PCIE 3.0 16x using 2.0 8x 10Gb intel X540-AT2 / using 1.0 16x Nvidia Geforce 6200 LE (also works in SeaBIOS) PCIE 2.0 1x using 2.0 1x 2.5Gb realtek RTL8125 PCIE 2.0 1x using 1.0 1x 1Gb intel 82574L (SeaBIOS loads option rom) Audio built-in speaker (plays music in OS compared to legacy bleep pc-speaker) Audio front panel 3.5 mm headphone jack (auto disables built-in Speakers and selects Headphones) Audio front panel 3.5 mm headphone&mic jack (only microphone works with 4 pin 3.5mm combi mic/headphone) Audio back panel 3.5mm green jack (manually select Line Out and it works) Sensors CPU and 2 motherboard sensors SuperIO Booting USB / SATA(HDD/DVD) OS: Fedora-mate Linux kernel 6.11.4 / 6.13.6, KDE neon Linux kernel 6.8.0-52 Flashrom: needs additional parameters compared to OEM BIOS both for read/write depending on flashrom version? flashrom -p internal:boardmismatch=force,ich_spi_mode=hwseq -w test.rom -c "Opague flash chip" Tested not Working: RAM ECC functioning (see coreboot log) SATA port black Wakeonlan, it just auto wakes from itself so cannot verify... iGPU multigpu with PCIE nvidia geforce 6200 le, only PCIE nvidia geforce works and iGPU gets disabled. What to do next to get this "compaq_pro_6300_sff" variant officially supported? *Supply more logs/info? *Fill a bug for the ECC not working or first get this variant supported as is? *Fill a bug that VGA doesn't work in SeaBIOS? *Fill a bug/ticket on the flashrom support list for the difference in parameters needed pre/post flash? https://support.hp.com/us-en/drivers/hp-compaq-pro-6300-small-form-factor-p… https://support.hp.com/in-en/drivers/hp-compaq-elite-8300-small-form-factor… Walter Sonius ---Files-------------------------------- cb-log-hp-compaq_pro_6300_sff.txt (51.8 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #583] (New) Allow reconfiguring PCIe slots on Asus P8Z77-V
by Keith Hui 21 Apr '25

21 Apr '25

Issue #583 has been reported by Keith Hui. ---------------------------------------- Feature #583: Allow reconfiguring PCIe slots on Asus P8Z77-V https://ticket.coreboot.org/issues/583 * Author: Keith Hui * Status: New * Priority: Normal * Assignee: Keith Hui * Category: board support * Target version: none * Start date: 2024-11-30 * Related links: https://review.coreboot.org/c/coreboot/+/85413 * Affected hardware: mb/asus/p8z77-v ---------------------------------------- Vendor firmware allows configuring the PCIe slots in three different ways, by reallocating 4 of the PCIe lanes between PCIEX16_3, PCIEX1_1, PCIEX1_2, and the onboard ASM1061 serial ATA controller providing 2 additional SATA ports. The options are (devices not shown are disabled): * X4: PCIEX16_3 as x4 * X1: PCIEX16_3 as x1, PCIEX1_1, PCIEX1_2 * Auto: PCIEX16_3 as x1, PCIEX1_1, ASM1061 The technical details have been worked out and implemented as patch CB:85413. However, two issues remain: 1. Despite our best efforts, PCIEX1_2 still doesn't work. 2. Configuring PCIEX16_3 for 4x requires changing a PCH soft strap from firmware, and coreboot lacks infrastructure for doing so. It has been established that the descriptor itself, which contains the soft straps, needs to be reflashed to make this change. This issue tracks our progress implementing this feature. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Toolchain tarballs missing
by Tim Crawford 21 Apr '25

21 Apr '25

It is currently not possible to build the coreboot toolchain due to NASM. The project website (https://nasm.us), which is used to download the source tarball, has been offline for days. While being hosted on GitHub for years now, the project does not use it for creating and distributing releases. coreboot does have mirrors of tarballs (https://www.coreboot.org/releases/crossgcc-sources/), but the version of NASM used is not present. - How are the tarballs uploaded to the coreboot mirror in the first place? - Can someone upload the missing tarball(s) to the mirror? -- Tim Crawford System76 Kernel Engineer tcrawford(a)system76.com

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2025_04_23 coreboot Review Session
by mina＠coreboot.org 21 Apr '25

21 Apr '25

Hello coreboot, Pleased to announce that our upcoming group review session is scheduled for Wednesday, April 23. https://meet.google.com/kpu-yozw-gtt Please check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html Here is the link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Kindly add any specific patches you'd like the group to review to the top of the sheet. As an hour is not sufficient to address all patches on the list, reviewing patches in advance is greatly appreciated. Thank you. Best regards, Mina.

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potential targets,
by zap 19 Apr '25

19 Apr '25

would it be possible to pay for a service to port x1 carbon gen 6 to coreboot? or thinkpad x280 or both? I am aware deguard can be used for this purpose, because of an intel me vulnerability. Is there a price someone would be willing to do this for? Would want boot guard disabled, plus intel me disabled + coreboot. Name the price if you anyone has interest

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2025-04-16 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org 17 Apr '25

17 Apr '25

# 2025-04-16 - coreboot Leadership Meeting ## Attendees Felix Singer, Werner Zeh, Julius Werner, Maximilian Brune, Jay Talbott, Alicja Michalska, Matt DeVellier, Mina Asante, Martin Roth, Felix Held, Jon Murphy, Marshall Dawson, Jeremy Compostella, Paul Menzel. ## Open Action Items * 2024-11-27 * [Open] Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * [Open] Add clarification to docs, “do not use gerrit change-id or CB: format in reference to already-merged patches.” * 2024-10-16 * [Open] Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * [Open] Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * [Open] Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian(?) * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * [Open] Daniel: Look at how we want to localize (non-console) strings for coreboot. Long term project. ## Minutes ### [Martin] Here is a blog post of things we are putting in place to have better engagement with companies: (https://docs.google.com/document/d/1lFUm4A-8F6J0acVbFkE_N_OY6PQcEup0lLPXAe3…) * This collaboration gives room for companies or entities to enjoy the following benefits: * Private development repos * Public branches in the coreboot repo * ongoing or one-off meetings with companies * official company reps for the leadership meetings * blog posts from companies * FelixS: Why would someone need a private repo? * [Alicja] The current coreboot leadership meeting schedule is not favorable for participants in the Asian time zones, and there are companies here that are interested in coreboot. Is it possible to schedule the meeting in a way that makes it possible for everyone to attend? * [Martin] If there's interest in scheduling another meeting, I’m personally fine with it. However, I can’t guarantee that the leadership team will be able to attend. * [Werner] People are always welcome to update the agenda with their issues even if they cant make it to the meeting or reach out directly to any member of the leadership team at any time, and we will be happy to help. * [Felix H] We should put this on the mailing list to see if there’s a demand for a second leadership meeting. ### [Martin] This is a task from a while back to create a questionnaire poll about the concerns surrounding the use of AI tools in open source development [Possible AI poll questions](https://docs.google.com/document/d/1s__V82xvvojpSuI9fEVD3YwND5_H… * Could I get some review? # Next Leadership Meeting * April 30, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice Decisions shown here are not necessarily final and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course, items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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coreboot Leadership Meeting: Call for Interest from the Asian Region
by coreboot org 17 Apr '25

17 Apr '25

Hello all, We’d like to gauge interest in establishing a second coreboot leadership meeting scheduled at a time more accessible for contributors across Asia. As our community has grown globally, we recognize that our current meeting time may present challenges for many of our contributors in Asian time zones. While we've tried to be inclusive by encouraging people to submit agenda items via the mailing list or directly to the agenda regardless of attendance ability, we understand this is not the same as active participation in discussions. This topic was raised during the most recent leadership meeting, so we'd like to determine if there's sufficient interest to warrant a second regularly scheduled meeting. While all three members of the coreboot leadership team probably will not be able to attend this additional meeting, we see value in creating a dedicated forum to: - Hear perspectives from our Asian contributors - Discuss region-specific challenges and opportunities - Ensure diverse viewpoints are incorporated into project decisions - Build stronger connections with contributors across all regions If you're based in Asia or would benefit from an alternative meeting time, please respond to this post indicating: - Your interest in attending - Preferred time window - Early, overlapping more with the Americas - Late, overlapping more with Europe and Africa Feel free to respond on the mailing list or directly to the coreboot.org(a)gmail.com email if you don't feel comfortable posting to the mailing list. We'll assess the responses to determine if there's enough interest to move forward with this initiative. Thanks! Martin

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Qotom Q20331G9-S10 (Intel Denverton C3758R) — Two Issues Remaining (VGA + Console Drop)
by Enzo Potenza 16 Apr '25

16 Apr '25

Dear all, I’ve been working on porting coreboot to the Qotom Q20331G9-S10, which uses the Intel Atom C3758R (Denverton). So far: System boots All onboard devices are detected properly Payload (EDK II) loads fine Issues: 1. VGA Not Working Pre-OS The board uses an AST2400 BMC for VGA output. I’ve added the VGA ROM (pulled from the official site) into the coreboot image, but no output is visible during pre-OS phase. (without the ROM, no VGA at all) 2. Console Stops After Payload The serial console works fine during the bootblock and into romstage/post. However, once coreboot hands off to the payload, the console garbles and stops showing valid output. Here’s the last clean output before it breaks: FSP End of Firmware ... Install PPI: BD44F629-EAE7-4198-87F1-39FAB0FD717E NotifyPhaseApi() - End [Status: 0x00000000] ▒`▒f▒▒▒f▒▒▒▒`▒f▒▒▒f▒▒▒▒`▒f▒▒▒f▒▒ If anyone has any ideas, I’d love to hear your inputs. Happy to share build configs or logs if that helps. Thanks! enzo

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