#95: Run coreboot in VirtualBox
by coreboot
#95: Run coreboot in VirtualBox
---------------------------------+------------------------------------------
Reporter: uwe | Owner: somebody
Type: defect | Status: new
Priority: minor | Milestone:
Component: misc | Version:
Keywords: | Dependencies:
Patchstatus: there is no patch |
---------------------------------+------------------------------------------
It would be nice if we could test coreboot images in VirtualBox, see
http://virtualbox.org/.
VirtualBox does not (yet) provide a simple mechanism to use a different
BIOS in their emulated machines (something like "-L" in qemu). Instead the
BIOS image (a custom bochs BIOS + LGPL'g VGABIOS) is converted to C code
(an array of bytes, or the like) and merged into the VirtualBox
executable.
The relevant files are
{{{
src/VBox/Devices/PC/DevPcBios.cpp
bldprogs/bin2c.c
}}}
if someone want to hack VirtualBox to easily support using coreboot images
instead of their usual BIOS.
--
Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/95>
coreboot <http://www.coreboot.org/>
4 years, 3 months
EHCI debug port finder
by Carl-Daniel Hailfinger
I wanted to know which physical port of my multiple USB controllers have
the debug capability. There was no way to find that easily, so I created
a tool which will do most of the work for the user.
Example output:
The following PCI devices support a USB debug port (says lspci):
0000:00:1d.7
The following PCI devices support a USB debug port (says the kernel):
0000:00:1d.7
PCI device 0000:00:1d.7, USB bus 3, USB physical port 1
Currently connected high-speed devices:
/: Bus 03.Port 1: Dev 1, Class=root_hub, Driver=ehci_hcd/6p, 480M
|__ Port 2: Dev 20, If 0, Class=stor., Driver=usb-storage, 480M
The output can be improved, but it's a good start.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
4 years, 9 months
Dual SPI Flash adapter attempt 2.0
by Oliver Schinagl
Hi list(s),
Here's my second attempt at routing the previously mailed png of my schema.
It was a lot trickier to route then my previous version, but I think it
worked out!
As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
should be 10k or ideally 100k, as Peter mentioned earlier.
Hopefully there's no obvious mistakes and can start working on
alternative layouts (so it is insert-able in different angles).
DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
That said, DRC check passes when I set the copper width/distance to
7mil's instead of the current 8 mils.
I'm planning on having these PCB's manufactured by Seeed studio and
their minimal width is much smaller.
Minimum trace width: 6mil
Minimum trace/vias/pads space : 6mil
Minimum silkscreen width : 4mil
Minimum silkscreen text size : 32mil
I've used a grid size of 10mil and distances of 8 mils, as I didn't want
to rely on the minimum of seed. The silkscreen I positioned using a grid
size of 5 mil's however. Not sure what they mean with a 'minimum
silkscreen text size' however.
Anyhow, feedback greatly appreciated, so I can start working on
alternative layouts :)
5 years
#186: 3com 3c905tx / gpxe boot problem
by coreboot
#186: 3com 3c905tx / gpxe boot problem
-----------------------------------+----------------------------------
Reporter: jeroenkrabbendam@… | Owner: stepan@…
Type: defect | Status: new
Priority: minor | Milestone:
Component: coreboot | Keywords: gpxe
Dependencies: | Patch Status: there is no patch
-----------------------------------+----------------------------------
Although (or: just because) novice in the field, I encountered some
problems with netbooting with coreboot.
Mobo's tried: Asus P2B, VTech with bios id ITE8671-2A69KV3IC-00. All
mobo's boot '''harddisk''' fine with Asus P2B / Gigabyte GA-6BX{CE}
respectively.
NIC ROM is started, and loads the kernel by tftp. This is vvvveeeerrrryyy
slow! Although loading, the kernel is never able to start itself. Same
kernel on HDU is no problem at all (GRUB2)
Note: the gpxe-image is on the nic, coreboot payload is seabios.
--
Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/186>
coreboot <http://www.coreboot.org/>
5 years, 2 months
unsupported mb questions (amd fam10h)
by Roman Elshin
I try to get coreboot working with asrock 880g pro3 board.
First problem: spd eprom say that memory ddr1600 capable, but it is not
so, is there are right way to limit memory frequency at ddr1333?
Other problem, may be related as machine with broken memory are very
unpredictable: boot process stop with "It is not SB800 or SB810"
message. I try to enable sb850 by this patch, but looks like it is not
enough, most of time coreboot does not detect hdd. Sometimes in very
rare case it is possible to boot from sata. Are sb850 supported by
coreboot?
-----------------------------------------------------------------------
diff -urN a/src/southbridge/amd/sb800/early_setup.c
b/src/southbridge/amd/sb800/early_setup.c
--- a/src/southbridge/amd/sb800/early_setup.c 2012-07-14
19:00:40.000000000 +0400
+++ b/src/southbridge/amd/sb800/early_setup.c 2012-07-14
21:49:54.000000000 +0400
@@ -94,7 +94,10 @@
rev = REV_SB800_A11;
} else if (rev_id == 0x41) {
rev = REV_SB800_A12;
- } else {
+ } else if (rev_id == 0x42) {
+ rev = REV_SB800_A13;
+ }
+ else {
die("It is not SB800 or SB810\r\n");
}
diff -urN a/src/southbridge/amd/sb800/sb800.h
b/src/southbridge/amd/sb800/sb800.h
--- a/src/southbridge/amd/sb800/sb800.h 2012-07-14 19:00:40.000000000
+0400
+++ b/src/southbridge/amd/sb800/sb800.h 2012-07-14 21:49:10.000000000
+0400
@@ -48,7 +48,7 @@
#define REV_SB800_A11 0x11
#define REV_SB800_A12 0x12
-
+#define REV_SB800_A13 0x13
#ifdef __PRE_RAM__
void sb800_lpc_port80(void);
-------------------------------------------------------------------------
5 years, 8 months
Re: [coreboot] ASUS m5a88-v AGESA port (bulldozer)
by darkdefende＠gmail.com
Idwer Vollering writes:
> Done.
Thanks for attaching the log for me.
Some recent commits to coreboot master seems to have solved my problem
with the pci scan hang. Now I don't have to hack around it any more.
However it still freezes after it's done (?) loading seabios.
I have uploaded my changes to https://github.com/DarkDefender/coreboot
if anyone want's to look at them.
I've tried to enable more debugging options in the "OptionsIds.h" for
AGESA but it doesn't seem to do anything.
The asserts are triggered druing boot are still the same as before.
I've tried to look at it but I didn't really understand what I should
change to solve them.
5 years, 8 months
ASRock E350M1: `PCI: Static device PCI: 00:04.0 not found, disabling it.` despite vendor BIOS showing it
by Paul Menzel
Dear coreboot folks,
the ASRock E350M1 [1] still has some issues and with the changes
committed since May 2012 new ones have been introduced too and I am
going to report them to the list one by one starting from the first
issues reported in the coreboot log.
The following is reported with the vendor BIOS [2].
-[0000:00]-+-00.0 1022:1510
+-01.0 1002:9802
+-01.1 1002:1314
+-04.0-[01]--
+-11.0 1002:4391
+-12.0 1002:4397
+-12.2 1002:4396
+-13.0 1002:4397
+-13.2 1002:4396
+-14.0 1002:4385
+-14.1 1002:439c
+-14.2 1002:4383
+-14.3 1002:439d
+-14.4-[02]--
+-14.5 1002:4399
+-15.0-[03]--
+-15.1-[04]----00.0 10ec:8168
+-16.0 1002:4397
+-16.2 1002:4396
+-18.0 1022:1700
+-18.1 1022:1701
+-18.2 1022:1702
+-18.3 1022:1703
+-18.4 1022:1704
+-18.5 1022:1718
+-18.6 1022:1716
\-18.7 1022:1719
Running the board with coreboot (based on fdfd89f2 with [4] applied and
debug messages) [3] PCI device 0:04.0 is not detected.
$ lspci -tnvv
-[0000:00]-+-00.0 1022:1510
+-01.0 1002:9802
+-01.1 1002:1314
+-11.0 1002:4390
+-12.0 1002:4397
+-12.2 1002:4396
+-13.0 1002:4397
+-13.2 1002:4396
+-14.0 1002:4385
+-14.2 1002:4383
+-14.3 1002:439d
+-14.4-[01]--
+-14.5 1002:4399
+-18.0 1022:1700
+-18.1 1022:1701
+-18.2 1022:1702
+-18.3 1022:1703
+-18.4 1022:1704
+-18.5 1022:1718
+-18.6 1022:1716
\-18.7 1022:1719
This problem has been present since the beginning (at least confirmed
with an image built from commit bdca153.
$ git show bdca153
commit bdca15337bc9337f399b43290dc74cb598c5ec4d
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon May 21 14:01:52 2012 +0200
libpayload: Remove orphaned delay from USB mass storage
The coreboot log (attached) contains the following.
[…]
Mainboard E350M1 Enable.
scan_static_bus for Root Device
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi =
0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi =
0x00000002
setup_uma_memory: uma size 0x18000000, memory start 0xc8000000
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
CPU_CLUSTER: 0 scanning...
AP siblings=1
CPU: APIC: 00 enabled
CPU: APIC: 01 enabled
DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [1022/1510] ops
PCI: 00:00.0 [1022/1510] enabled
PCI: 00:01.0 [1002/9802] enabled
PCI: 00:01.1 [1002/1314] enabled
PCI: Static device PCI: 00:04.0 not found, disabling it.
sb800_enable SB800 - Smbus.c - alink_ab_indx - Start.
SB800 - Smbus.c - alink_ab_indx - End.
PCI: 00:11.0 [1002/4390] enabled
sb800_enable PCI: 00:12.0 [1002/4397] ops
PCI: 00:12.0 [1002/4397] enabled
sb800_enable PCI: 00:12.2 [1002/4396] ops
PCI: 00:12.2 [1002/4396] enabled
sb800_enable PCI: 00:13.0 [1002/4397] ops
PCI: 00:13.0 [1002/4397] enabled
sb800_enable PCI: 00:13.2 [1002/4396] ops
PCI: 00:13.2 [1002/4396] enabled
[…]
Any idea what might be wrong. The vendor BIOS says it is the following
device.
00:04.0 PCI bridge: Advanced Micro Devices [AMD] Family 14h Processor Root Port (prog-if 00 [Normal decode])
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
I/O behind bridge: 00001000-00001fff
Memory behind bridge: d0100000-d02fffff
Prefetchable memory behind bridge: 00000000d0300000-00000000d04fffff
Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
Capabilities: [50] Power Management version 3
Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+)
Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
ExtTag+ RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 128 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #247, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <64ns, L1 <1us
ClockPM- Surprise- LLActRep+ BwNot+
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed unknown, Width x16, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise-
Slot #4, PowerLimit 75.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
Changed: MRL- PresDet- LinkState-
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
DevCap2: Completion Timeout: Range ABCD, TimeoutDis+ ARIFwd-
DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis- ARIFwd-
LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [b0] Subsystem: Advanced Micro Devices [AMD] Device 1234
Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 Len=010 <?>
Kernel driver in use: pcieport
00: 22 10 12 15 07 00 10 00 00 00 04 06 10 00 01 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00
20: 10 d0 20 d0 31 d0 41 d0 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 0b 01 10 00
Any ideas are appreciated.
Thanks,
Paul
[1] http://www.coreboot.org/ASRock_E350M1
[2] http://www.coreboot.org/File:ASRock_E350M1_info_dump.tar.bz2
[3] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=fdfd89f21326f...
[4] http://review.coreboot.org/#/c/2536/
6 years
X201 status
by Vladimir 'φ-coder/phcoder' Serbinenko
Current status.
Raminit: works with delays/printfs currently in place, 1-ranked memory
populating one slot. Didn't test in any other config yet (either
removing debug and delays or trying other type of memory). Looks like
resulting settings are slower than original BIOS due to me skipping some
of advanced training.
EHCI and AHCI work in GRUB shell.
VGA option ROM works
keyboard works.
LAN card doesn't show up in lspci
ACPI tables are visible in GRUB but mysteriously disappear when Linux is
booted (working theory is that some other device got mapped over).
Linux boots into debian netinst (images taken from USB stick).
6 years
New patch to review for coreboot: e932afb ARM: fix the ldscripts so that exit/enter stage work correctly.
by Ronald G. Minnich
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2560
-gerrit
commit e932afbe3f175afe77f304aa5e93fb6dfe52d78e
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Thu Feb 28 15:21:41 2013 -0600
ARM: fix the ldscripts so that exit/enter stage work correctly.
Remove the spurious creation of a start symbol, and use the
stage entry symbol directly.
Change-Id: Ia62d5c056ac8b20c8ffdb78bff3d306065b6c45f
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/arch/armv7/coreboot_ram.ld | 2 +-
src/arch/armv7/romstage.ld | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index 2edf8e3..c2ead7a 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -22,7 +22,7 @@
/* We use ELF as output format. So that we can debug the code in some form. */
INCLUDE ldoptions
-ENTRY(_start)
+ENTRY(stage_entry)
SECTIONS
{
diff --git a/src/arch/armv7/romstage.ld b/src/arch/armv7/romstage.ld
index 6728fb1..568ac1a 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/armv7/romstage.ld
@@ -28,7 +28,7 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
-ENTRY(_start)
+ENTRY(stage_entry)
SECTIONS
{
6 years
