2:50 p.m.
Hi list(s),
Here's my second attempt at routing the previously mailed png of my schema.
It was a lot trickier to route then my previous version, but I think it
worked out!
As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
should be 10k or ideally 100k, as Peter mentioned earlier.
Hopefully there's no obvious mistakes and can start working on
alternative layouts (so it is insert-able in different angles).
DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
That said, DRC check passes when I set the copper width/distance to
7mil's instead of the current 8 mils.
I'm planning on having these PCB's manufactured by Seeed studio and
their minimal width is much smaller.
Minimum trace width: 6mil
Minimum trace/vias/pads space : 6mil
Minimum silkscreen width : 4mil
Minimum silkscreen text size : 32mil
I've used a grid size of 10mil and distances of 8 mils, as I didn't want
to rely on the minimum of seed. The silkscreen I positioned using a grid
size of 5 mil's however. Not sure what they mean with a 'minimum
silkscreen text size' however.
Anyhow, feedback greatly appreciated, so I can start working on
alternative layouts :)
8:23 p.m.
Hi!
I've worked on a rotated version and planning to do two other
orientations as well, so early feedback is good, so I don't have to redo
them again :)
Silk screening isn't 100% right, since I still need to rename them
eventually somehow (edit .pcb file directly is probably the easiest way?)
On 04/20/12 14:50, Oliver Schinagl wrote:
Hi list(s),
Here's my second attempt at routing the previously mailed png of my schema.
It was a lot trickier to route then my previous version, but I think it
worked out!
As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
should be 10k or ideally 100k, as Peter mentioned earlier.
Hopefully there's no obvious mistakes and can start working on
alternative layouts (so it is insert-able in different angles).
DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
That said, DRC check passes when I set the copper width/distance to
7mil's instead of the current 8 mils.
I'm planning on having these PCB's manufactured by Seeed studio and
their minimal width is much smaller.
Minimum trace width: 6mil
Minimum trace/vias/pads space : 6mil
Minimum silkscreen width : 4mil
Minimum silkscreen text size : 32mil
I've used a grid size of 10mil and distances of 8 mils, as I didn't want
to rely on the minimum of seed. The silkscreen I positioned using a grid
size of 5 mil's however. Not sure what they mean with a 'minimum
silkscreen text size' however.
Anyhow, feedback greatly appreciated, so I can start working on
alternative layouts :)
12:06 a.m.
Really quick update,
routed a sideway version. Wow, that was a huge pain. Lots of via's.
Don't wanna have to redo this one :)
Oliver
On 04/23/12 20:23, Oliver Schinagl wrote:
Hi!
I've worked on a rotated version and planning to do two other
orientations as well, so early feedback is good, so I don't have to redo
them again :)
Silk screening isn't 100% right, since I still need to rename them
eventually somehow (edit .pcb file directly is probably the easiest way?)
On 04/20/12 14:50, Oliver Schinagl wrote:
> Hi list(s),
>
> Here's my second attempt at routing the previously mailed png of my
> schema.
>
> It was a lot trickier to route then my previous version, but I think it
> worked out!
>
> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
> should be 10k or ideally 100k, as Peter mentioned earlier.
>
> Hopefully there's no obvious mistakes and can start working on
> alternative layouts (so it is insert-able in different angles).
>
> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
> That said, DRC check passes when I set the copper width/distance to
> 7mil's instead of the current 8 mils.
>
> I'm planning on having these PCB's manufactured by Seeed studio and
> their minimal width is much smaller.
>
> Minimum trace width: 6mil
> Minimum trace/vias/pads space : 6mil
> Minimum silkscreen width : 4mil
> Minimum silkscreen text size : 32mil
>
> I've used a grid size of 10mil and distances of 8 mils, as I didn't want
> to rely on the minimum of seed. The silkscreen I positioned using a grid
> size of 5 mil's however. Not sure what they mean with a 'minimum
> silkscreen text size' however.
>
> Anyhow, feedback greatly appreciated, so I can start working on
> alternative layouts :)
>
>
6:56 p.m.
Hey all,
Well here it is, the last version which was even harder then the 3rd
one. or so it seemed anyhow.
I will work on copying these four to the bottom and renaming the labels
before sending them off. I'll post the final pcb on this list again,but
routing wise, Nothing will change, unless of course someone found a
grand mistake.
So really, all input is greatly appreciated :D would be shameful to send
this off to get printed, just to find bugs and have another batch made.
Oliver
On 23-04-12 20:23, Oliver Schinagl wrote:
Hi!
I've worked on a rotated version and planning to do two other
orientations as well, so early feedback is good, so I don't have to
redo them again :)
Silk screening isn't 100% right, since I still need to rename them
eventually somehow (edit .pcb file directly is probably the easiest way?)
On 04/20/12 14:50, Oliver Schinagl wrote:
> Hi list(s),
>
> Here's my second attempt at routing the previously mailed png of my
> schema.
>
> It was a lot trickier to route then my previous version, but I think it
> worked out!
>
> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
> should be 10k or ideally 100k, as Peter mentioned earlier.
>
> Hopefully there's no obvious mistakes and can start working on
> alternative layouts (so it is insert-able in different angles).
>
> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
> That said, DRC check passes when I set the copper width/distance to
> 7mil's instead of the current 8 mils.
>
> I'm planning on having these PCB's manufactured by Seeed studio and
> their minimal width is much smaller.
>
> Minimum trace width: 6mil
> Minimum trace/vias/pads space : 6mil
> Minimum silkscreen width : 4mil
> Minimum silkscreen text size : 32mil
>
> I've used a grid size of 10mil and distances of 8 mils, as I didn't want
> to rely on the minimum of seed. The silkscreen I positioned using a grid
> size of 5 mil's however. Not sure what they mean with a 'minimum
> silkscreen text size' however.
>
> Anyhow, feedback greatly appreciated, so I can start working on
> alternative layouts :)
>
>
12:41 a.m.
Had a few hours this evening, and .. it's done.
I've had to re-arrange some labels and 1 part to make sure the
silk-screen would not interferer with the solderpads. Not sure how I
could have missed that, it was really really small bit that was
overlapping though.
Somehow I managed to mirror one of my labels on a component. So the part
was on the top side, while the label looked like it was on the bottom
side. Long story short, i just deleted the part, and copied it from the
neighboring part. Due to all the renaming though, I get all strange
connects when using the automated rats nest, but I guess that's the
price to pay.
So the big question is; shall I send this to seeed for fabrication or
does it need some big change?
In any case, thanks so far for all your time and help ;)
Oliver
On 04/26/12 18:56, Oliver Schinagl wrote:
Hey all,
Well here it is, the last version which was even harder then the 3rd
one. or so it seemed anyhow.
I will work on copying these four to the bottom and renaming the labels
before sending them off. I'll post the final pcb on this list again,but
routing wise, Nothing will change, unless of course someone found a
grand mistake.
So really, all input is greatly appreciated :D would be shameful to send
this off to get printed, just to find bugs and have another batch made.
Oliver
On 23-04-12 20:23, Oliver Schinagl wrote:
> Hi!
>
> I've worked on a rotated version and planning to do two other
> orientations as well, so early feedback is good, so I don't have to
> redo them again :)
>
> Silk screening isn't 100% right, since I still need to rename them
> eventually somehow (edit .pcb file directly is probably the easiest way?)
>
> On 04/20/12 14:50, Oliver Schinagl wrote:
>> Hi list(s),
>>
>> Here's my second attempt at routing the previously mailed png of my
>> schema.
>>
>> It was a lot trickier to route then my previous version, but I think it
>> worked out!
>>
>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>
>> Hopefully there's no obvious mistakes and can start working on
>> alternative layouts (so it is insert-able in different angles).
>>
>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>> That said, DRC check passes when I set the copper width/distance to
>> 7mil's instead of the current 8 mils.
>>
>> I'm planning on having these PCB's manufactured by Seeed studio and
>> their minimal width is much smaller.
>>
>> Minimum trace width: 6mil
>> Minimum trace/vias/pads space : 6mil
>> Minimum silkscreen width : 4mil
>> Minimum silkscreen text size : 32mil
>>
>> I've used a grid size of 10mil and distances of 8 mils, as I didn't want
>> to rely on the minimum of seed. The silkscreen I positioned using a grid
>> size of 5 mil's however. Not sure what they mean with a 'minimum
>> silkscreen text size' however.
>>
>> Anyhow, feedback greatly appreciated, so I can start working on
>> alternative layouts :)
>>
>>
>
>
1:20 a.m.
Oliver Schinagl wrote:
Somehow I managed to mirror one of my labels on a component. So the
part was on the top side, while the label looked like it was on the
bottom side. Long story short, i just deleted the part, and copied it
from the neighboring part. Due to all the renaming though, I get all
strange connects when using the automated rats nest, but I guess
that's the price to pay.
I prefer to drive my layout with gschem. That is, all parts in the
layout are also mentiond in the schematic - no manual insertion of
footprints in pcb. For a multiple instances like in your layout can
be achieved with a hierarchical schematic.
So the big question is; shall I send this to seeed for fabrication
The outline lines should look more simple. The gerbers expicitely
call for a milled edge at the middle of each line. So ther should
be a single line where you expect the fab to cut the board.
The fabs I know, would object against such a multiple part layout
and charge extra for their increased handling effort. They prefer
layouts in one piece.
Copper lines look a bit on the skinny side. If they are more beefy
the manufactured board can be tweaked more easily. Depending on
the currents, ground and supply may benefit from increased line
thickness. If S1 and S2 are SMD supposed to be jumpers, then it
may be hard to close them with a solder iron. The pads should be
much wider than the gab to make the solder bridge more likely.
---<)kaimartin(>---
--
Kai-Martin Knaak, Email: kmk(a)familieknaak.de
http://pool.sks-keyservers.net:11371/pks/lookup?search=0x6C0B9F53
Still unhappy with moderation of geda-user.
Why? Because it is completely intransparent.
2:08 a.m.
Oliver Schinagl wrote:
So the big question is; shall I send this to seeed for fabrication
or does it need some big change?
The RN has slivers of soldermask between pads. Avoid this; it's too
thin to work at all in production and the component size is so small
that you want to avoid any chance of soldermask getting in the way
of soldering. Board production processes are not exact, they are
messy mechanically and chemically, and you should never push your
producer's limits. If their limit is 6 never use less than 8.
The SMD ICs and RN all have the package outline on silk absolutely
tight around the soldermask apertures. Avoid this, again because the
silk is way too close to the pads, and you never want silk anywhere
outside the solder mask.
The U3 "orientation marker" (the arc) is rotated 45 degrees.
The RN outline isn't closed.
Keep in mind that there will be chip mounted on U2 so your JP1 legend
will never be visible. I would center JP1 and put a 1 and a 2 on each
side, and put a 1 and a 2 near the corresponding flash chips.
I don't particularly like that the U1 pins use 2x a 4-pin header
footprint. I would create a copy of the U2 footprint and adapt it to
make room for the SO8 inside of it, to make it completely clear what
goes mounted which way where.
Make sure to check that the sockets and pin headers you will use
actually fit in the holes that are in the footprints. Remember that
the hole in the footprint file is what will get drilled. After
drilling the holes will be plated, so the usable hole diameter is:
$drillsize - 2 * $platingthickness
Drills also never create nominal diameter holes, but always slightly
smaller. It is quite annoying to have boards full of holes that are
too small to fit the part.
The 45 degree PCB corners look fancy but really just add annoying
complexity and problems for the board house. Unneccessary complexity,
strip it off and have simple 90 degree corners.
The v in v0.1 and S in S1 on the bottom of the upper third board from
left is too close to pin U2-5 and pad S1-2 respectively.
The right edge of 'r' in some silk text goes in between pads where I
would make sure to keep clear.
There is way way too much silk for my taste. I don't like silk too
much when space is tight except if something *really* needs to be
explained. "JP1" is useless to all users. The *only* thing that needs
to be explained on the PCBs is what jumper setting activates what
flash chip. Explaining this with this little space is difficult!
Adding the inverter logic gate makes the problem simpler to explain
and means that JP1 has one less pin = more space for text, maybe
"Orig" or such, which would be clear to the user because they put
their original flash chip in the socket.
The silk of RN1 on the back of the third board from the left (as seen
from the front or after pressing Shift-Tab) goes outside the soldermask
aperture onto the keepout between the annular ring and the soldermask.
I would make the SMD pads extend longer "outwards" in order to make
hand soldering easier.
I would completely drop U1 through hole pins and make the PCB
strictly for a surface mounte U1. The board could become smaller
and/or have a little more text explaining the jumper.
All that said I believe you could manufacture this board and that the
PCBs would work. (But they would be a bit tough to populate.)
//Peter
11:32 a.m.
New subject: [geda-user] Re: Dual SPI Flash adapter attempt 2.0
Wow, nice big review :D feedback!
On 04/27/12 02:08, Peter Stuge wrote:
Oliver Schinagl wrote:
> So the big question is; shall I send this to seeed for fabrication
> or does it need some big change?
The RN has slivers of soldermask between pads. Avoid this; it's too
thin to work at all in production and the component size is so small
that you want to avoid any chance of soldermask getting in the way
of soldering. Board production processes are not exact, they are
messy mechanically and chemically, and you should never push your
producer's limits. If their limit is 6 never use less than 8.
That's just
how the part comes. I haven't made or modified it. Is there
some way to increase soldermask spacing or better yet, so set up some
minimal with?
Their limit is 6, i've designed the board entirely using 8; however the
U3 part, the FET switch just comes in this size, or smaller and would
thus be impossible to use.
The SMD ICs and RN all have the package outline on silk absolutely
tight around the soldermask apertures. Avoid this, again because the
silk is way too close to the pads, and you never want silk anywhere
outside the solder mask.
Again, this is how the RN and SMD IC's come with
PCB/gEDA. I could
design new parts or remove the silk-screen from those parts and use
custom parts, but if these parts are so 'flawed' they should be
removed/modified from geda?
I do agree however that that ink will be close to the pads.
The U3 "orientation marker" (the arc) is rotated 45 degrees.
You mean the u between pin 1 and pin 8? The half circle? I haven't
spotted this or am not quite sure what you mean.
The RN outline isn't closed.
That's how the part comes
:( As above I suppose.
Keep in mind that there will be chip mounted on U2 so your JP1 legend
will never be visible. I would center JP1 and put a 1 and a 2 on each
side, and put a 1 and a 2 near the corresponding flash chips.
Yes, I have thought
of that too, but since U2 is a socket! this can be
read when the chip is removed. I know it's far from ideal, but there's
only very very limited space.
I don't particularly like that the U1 pins use 2x a 4-pin header
footprint. I would create a copy of the U2 footprint and adapt it to
make room for the SO8 inside of it, to make it completely clear what
goes mounted which way where.
I initially had this as an idea too, but I thought
the two headers where
more matching in what will eventually be installed. 2 header rows.
Spacing for the SO8 shouldn't be a problem, as the headers will be
facing the bottom and the SO8 sits on top.
Make sure to check that the sockets and pin headers you will use
actually fit in the holes that are in the footprints. Remember that
the hole in the footprint file is what will get drilled. After
drilling the holes will be plated, so the usable hole diameter is:
$drillsize - 2 * $platingthickness
Drills also never create nominal diameter holes, but always slightly
smaller. It is quite annoying to have boards full of holes that are
too small to fit the part.
Heh, I just assumed, whoever made those parts accounted
for this. I am
going to print it all on paper and see if things fit properly there. I
will measure socket/header pin widths and make sure that drillsize -2 *
platingthickness (if I can find this from seeed's spec) is big enough. I
belive I can change the drill size quite easily in PCB?
The 45 degree PCB corners look fancy but really just add annoying
complexity and problems for the board house. Unneccessary complexity,
strip it off and have simple 90 degree corners.
Ok, will do. I am guessing that
i'll have to cut those boards myself.
Since even if they let me subpanel them, I have to cut it myself anyhow.
Scorch with exacto knife and metal ruler and break :S
The v in v0.1 and S in S1 on the bottom of the upper third board from
left is too close to pin U2-5 and pad S1-2 respectively.
Fixed. But I did a very
very close up with the soldermask enabled and
didn't see it. Stil, there was room so I moved it.
The right edge of 'r' in some silk text goes in between pads where I
would make sure to keep clear.
But there was no room for my full name! I'll
make it smaller if that
could cause issues.
There is way way too much silk for my taste. I don't like silk too
much when space is tight except if something *really* needs to be
explained. "JP1" is useless to all users. The *only* thing that needs
to be explained on the PCBs is what jumper setting activates what
flash chip. Explaining this with this little space is difficult!
Adding the inverter logic gate makes the problem simpler to explain
and means that JP1 has one less pin = more space for text, maybe
"Orig" or such, which would be clear to the user because they put
their original flash chip in the socket.
I actually tried to see if there was room
for the additional inverter
logic gate, but I couldn't make it work. I guess it will require some
minimal manual?
The silk of RN1 on the back of the third board from the left (as seen
from the front or after pressing Shift-Tab) goes outside the soldermask
aperture onto the keepout between the annular ring and the soldermask.
Fixed! Crap,
I did miss that one. I had 1 more with he same mistake.
Peer review is good!
I would make the SMD pads extend longer "outwards" in order to make
hand soldering easier.
I'd have to use a custom part for this? I had a SO8-W at
some point, but
the insides where shorter and it didn't properly fit. So how would I do
this manually (First time PCB user, or EDA user in general :) without
using a custom part ideally?
I would completely drop U1 through hole pins and make the PCB
strictly for a surface mounte U1. The board could become smaller
and/or have a little more text explaining the jumper.
Yes! But! People who are
lucky enough to use this board to plug into
their existing socket, can remain using their existing chip, which has
several advantages?
All that said I believe you could manufacture this board and that the
PCBs would work. (But they would be a bit tough to populate.)
I'll fix
everything you mentioned (THANK YOU!) and will mail a fixed PCB
later today/tomorrow to include all mentioned fixes by everyone.
As for the though to populate, for those who are handy enough to solder,
can get the solder version. If the board is a success and is wanted to
be given away at events, They'll have to be made prepopulated I suppose!
//Peter
Oliver
2:21 a.m.
Oliver Schinagl wrote:
So the big question is; shall I send this to seeed for fabrication
or does it need some big change?
One last thing (I think) is to check if the 20 mil = 0.5 mm Y-axis
clearance between the individual boards will actually work.
Even the 60 mil = 1.52 mm X-axis clearance is rather small if they
are doing a disk cut.
If they only V score the outline and then break them apart
mechanically then the 20 mil is fine. The boards I have do have flush
edges however, so they were disc cut, and the disc is likely wider
than 0.5 mm => you need to increase Y clearance or perhaps simply
throw out the U1 pins and make it SO only.
//Peter
4:14 p.m.
Hey all,
Find here all included fixes and modifications. I've increased spacing
and removed the 'outline' layer. I moved parts to the edge. Since Seeed
does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
is ...
If I don't see any feedback on things that need fixing here, I'll set
out an order for the prototypes :)
Oliver
Have a good weekend all!
On 04/26/12 18:56, Oliver Schinagl wrote:
Hey all,
Well here it is, the last version which was even harder then the 3rd
one. or so it seemed anyhow.
I will work on copying these four to the bottom and renaming the labels
before sending them off. I'll post the final pcb on this list again,but
routing wise, Nothing will change, unless of course someone found a
grand mistake.
So really, all input is greatly appreciated :D would be shameful to send
this off to get printed, just to find bugs and have another batch made.
Oliver
On 23-04-12 20:23, Oliver Schinagl wrote:
> Hi!
>
> I've worked on a rotated version and planning to do two other
> orientations as well, so early feedback is good, so I don't have to
> redo them again :)
>
> Silk screening isn't 100% right, since I still need to rename them
> eventually somehow (edit .pcb file directly is probably the easiest way?)
>
> On 04/20/12 14:50, Oliver Schinagl wrote:
>> Hi list(s),
>>
>> Here's my second attempt at routing the previously mailed png of my
>> schema.
>>
>> It was a lot trickier to route then my previous version, but I think it
>> worked out!
>>
>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>
>> Hopefully there's no obvious mistakes and can start working on
>> alternative layouts (so it is insert-able in different angles).
>>
>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>> That said, DRC check passes when I set the copper width/distance to
>> 7mil's instead of the current 8 mils.
>>
>> I'm planning on having these PCB's manufactured by Seeed studio and
>> their minimal width is much smaller.
>>
>> Minimum trace width: 6mil
>> Minimum trace/vias/pads space : 6mil
>> Minimum silkscreen width : 4mil
>> Minimum silkscreen text size : 32mil
>>
>> I've used a grid size of 10mil and distances of 8 mils, as I didn't want
>> to rely on the minimum of seed. The silkscreen I positioned using a grid
>> size of 5 mil's however. Not sure what they mean with a 'minimum
>> silkscreen text size' however.
>>
>> Anyhow, feedback greatly appreciated, so I can start working on
>> alternative layouts :)
>>
>>
>
>
3:39 p.m.
Just an FYI,
This is the final version that I will send over to seeed after placing
an order. The only thing that will change is the order number (now it's
an arbitrary number). If I have to do major changes to the board, I will
of course send an updated version to the list.
Oliver
On 04/28/12 16:14, Oliver Schinagl wrote:
Hey all,
Find here all included fixes and modifications. I've increased spacing
and removed the 'outline' layer. I moved parts to the edge. Since Seeed
does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
is ...
If I don't see any feedback on things that need fixing here, I'll set
out an order for the prototypes :)
Oliver
Have a good weekend all!
On 04/26/12 18:56, Oliver Schinagl wrote:
> Hey all,
>
> Well here it is, the last version which was even harder then the 3rd
> one. or so it seemed anyhow.
>
> I will work on copying these four to the bottom and renaming the labels
> before sending them off. I'll post the final pcb on this list again,but
> routing wise, Nothing will change, unless of course someone found a
> grand mistake.
>
> So really, all input is greatly appreciated :D would be shameful to send
> this off to get printed, just to find bugs and have another batch made.
>
> Oliver
>
> On 23-04-12 20:23, Oliver Schinagl wrote:
>> Hi!
>>
>> I've worked on a rotated version and planning to do two other
>> orientations as well, so early feedback is good, so I don't have to
>> redo them again :)
>>
>> Silk screening isn't 100% right, since I still need to rename them
>> eventually somehow (edit .pcb file directly is probably the easiest
>> way?)
>>
>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>> Hi list(s),
>>>
>>> Here's my second attempt at routing the previously mailed png of my
>>> schema.
>>>
>>> It was a lot trickier to route then my previous version, but I think it
>>> worked out!
>>>
>>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>
>>> Hopefully there's no obvious mistakes and can start working on
>>> alternative layouts (so it is insert-able in different angles).
>>>
>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>>> That said, DRC check passes when I set the copper width/distance to
>>> 7mil's instead of the current 8 mils.
>>>
>>> I'm planning on having these PCB's manufactured by Seeed studio and
>>> their minimal width is much smaller.
>>>
>>> Minimum trace width: 6mil
>>> Minimum trace/vias/pads space : 6mil
>>> Minimum silkscreen width : 4mil
>>> Minimum silkscreen text size : 32mil
>>>
>>> I've used a grid size of 10mil and distances of 8 mils, as I didn't
>>> want
>>> to rely on the minimum of seed. The silkscreen I positioned using a
>>> grid
>>> size of 5 mil's however. Not sure what they mean with a 'minimum
>>> silkscreen text size' however.
>>>
>>> Anyhow, feedback greatly appreciated, so I can start working on
>>> alternative layouts :)
>>>
>>>
>>
>>
>
>
>
6:23 p.m.
Hi coreboot!
I finally sent off my order to seeed and have received the boards back.
It turns out, that over the last year (and a half) seeed actually
improved their processes and have even narrower minimals, which is great
for this board.
Anyway, I took some pics and the uploaded the schematics to [1]. I
rather host the schematics etc somewhere on coreboot's servers, as I
feel this is as use full to coreboot as anything else.
The only thing I'm not so happy about is the footprint of the FET
switch. The legs don't seem to match up perfectly (the outer ones only
strangely) and the pads should have been bigger to make soldering
easier. But since it is optional (if you bridge s1 and s2 the chip
doesn't have to be mounted, nor does RN1 I think, but it's been a while :p)
I haven't split all of the boards yet, but I should have tons! 12 * 8. I
am attending FOSDEM2014 so if any of the coreboot folk are having a
booth or even just attending, I'd be happy to bring the boards along so
they can be gifted. Anybody able to cut them though? I used a stanley
knife scorching the board but that took quite some time :) Using a
dremel requires extremely steady hands, as the cutting wheel probably
does fit, but it's extremely tight.
Anyway, looking forward to show it all off @FOSDEM2014 ;)
oliver
[1] http://oliver.schinagl.nl/gallery/v/geek_stuff/dspif/
Quoted the below to help remind people what this post is really about ;)
On 05/13/12 15:39, Oliver Schinagl wrote:
Just an FYI,
This is the final version that I will send over to seeed after placing
an order. The only thing that will change is the order number (now it's
an arbitrary number). If I have to do major changes to the board, I will
of course send an updated version to the list.
Oliver
On 04/28/12 16:14, Oliver Schinagl wrote:
> Hey all,
>
> Find here all included fixes and modifications. I've increased spacing
> and removed the 'outline' layer. I moved parts to the edge. Since Seeed
> does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
> is ...
>
> If I don't see any feedback on things that need fixing here, I'll set
> out an order for the prototypes :)
>
> Oliver
>
> Have a good weekend all!
>
> On 04/26/12 18:56, Oliver Schinagl wrote:
>> Hey all,
>>
>> Well here it is, the last version which was even harder then the 3rd
>> one. or so it seemed anyhow.
>>
>> I will work on copying these four to the bottom and renaming the labels
>> before sending them off. I'll post the final pcb on this list again,but
>> routing wise, Nothing will change, unless of course someone found a
>> grand mistake.
>>
>> So really, all input is greatly appreciated :D would be shameful to send
>> this off to get printed, just to find bugs and have another batch made.
>>
>> Oliver
>>
>> On 23-04-12 20:23, Oliver Schinagl wrote:
>>> Hi!
>>>
>>> I've worked on a rotated version and planning to do two other
>>> orientations as well, so early feedback is good, so I don't have to
>>> redo them again :)
>>>
>>> Silk screening isn't 100% right, since I still need to rename them
>>> eventually somehow (edit .pcb file directly is probably the easiest
>>> way?)
>>>
>>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>>> Hi list(s),
>>>>
>>>> Here's my second attempt at routing the previously mailed png of my
>>>> schema.
>>>>
>>>> It was a lot trickier to route then my previous version, but I think it
>>>> worked out!
>>>>
>>>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>>
>>>> Hopefully there's no obvious mistakes and can start working on
>>>> alternative layouts (so it is insert-able in different angles).
>>>>
>>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>>>> That said, DRC check passes when I set the copper width/distance to
>>>> 7mil's instead of the current 8 mils.
>>>>
>>>> I'm planning on having these PCB's manufactured by Seeed studio
and
>>>> their minimal width is much smaller.
>>>>
>>>> Minimum trace width: 6mil
>>>> Minimum trace/vias/pads space : 6mil
>>>> Minimum silkscreen width : 4mil
>>>> Minimum silkscreen text size : 32mil
>>>>
>>>> I've used a grid size of 10mil and distances of 8 mils, as I
didn't
>>>> want
>>>> to rely on the minimum of seed. The silkscreen I positioned using a
>>>> grid
>>>> size of 5 mil's however. Not sure what they mean with a 'minimum
>>>> silkscreen text size' however.
>>>>
>>>> Anyhow, feedback greatly appreciated, so I can start working on
>>>> alternative layouts :)
>>>>
>>>>
>>>
>>>
>>
>>
>>
>
>
>
>
6:45 p.m.
Hi coreboot!
I finally sent off my order to seeed and have received the boards back.
It turns out, that over the last year (and a half) seeed actually
improved their processes and have even narrower minimals, which is great
for this board.
Anyway, I took some pics and the uploaded the schematics to [1]. I
rather host the schematics etc somewhere on coreboot's servers, as I
feel this is as use full to coreboot as anything else.
The only thing I'm not so happy about is the footprint of the FET
switch. The legs don't seem to match up perfectly (the outer ones only
strangely) and the pads should have been bigger to make soldering
easier. But since it is optional (if you bridge s1 and s2 the chip
doesn't have to be mounted, nor does RN1 I think, but it's been a while :p)
I haven't split all of the boards yet, but I should have tons! 12 * 8. I
am attending FOSDEM2014 so if any of the coreboot folk are having a
booth or even just attending, I'd be happy to bring the boards along so
they can be gifted. Anybody able to cut them though? I used a stanley
knife scorching the board but that took quite some time :) Using a
dremel requires extremely steady hands, as the cutting wheel probably
does fit, but it's extremely tight.
Anyway, looking forward to show it all off @FOSDEM2014 ;)
oliver
[1] http://oliver.schinagl.nl/gallery/v/geek_stuff/dspif/
Quoted the below to help remind people what this post is really about ;)
On 05/13/12 15:39, Oliver Schinagl wrote:
Just an FYI,
This is the final version that I will send over to seeed after placing
an order. The only thing that will change is the order number (now it's
an arbitrary number). If I have to do major changes to the board, I will
of course send an updated version to the list.
Oliver
On 04/28/12 16:14, Oliver Schinagl wrote:
> Hey all,
>
> Find here all included fixes and modifications. I've increased spacing
> and removed the 'outline' layer. I moved parts to the edge. Since Seeed
> does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
> is ...
>
> If I don't see any feedback on things that need fixing here, I'll set
> out an order for the prototypes :)
>
> Oliver
>
> Have a good weekend all!
>
> On 04/26/12 18:56, Oliver Schinagl wrote:
>> Hey all,
>>
>> Well here it is, the last version which was even harder then the 3rd
>> one. or so it seemed anyhow.
>>
>> I will work on copying these four to the bottom and renaming the labels
>> before sending them off. I'll post the final pcb on this list again,but
>> routing wise, Nothing will change, unless of course someone found a
>> grand mistake.
>>
>> So really, all input is greatly appreciated :D would be shameful to send
>> this off to get printed, just to find bugs and have another batch made.
>>
>> Oliver
>>
>> On 23-04-12 20:23, Oliver Schinagl wrote:
>>> Hi!
>>>
>>> I've worked on a rotated version and planning to do two other
>>> orientations as well, so early feedback is good, so I don't have to
>>> redo them again :)
>>>
>>> Silk screening isn't 100% right, since I still need to rename them
>>> eventually somehow (edit .pcb file directly is probably the easiest
>>> way?)
>>>
>>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>>> Hi list(s),
>>>>
>>>> Here's my second attempt at routing the previously mailed png of my
>>>> schema.
>>>>
>>>> It was a lot trickier to route then my previous version, but I think it
>>>> worked out!
>>>>
>>>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted. RN1
>>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>>
>>>> Hopefully there's no obvious mistakes and can start working on
>>>> alternative layouts (so it is insert-able in different angles).
>>>>
>>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to shallow.
>>>> That said, DRC check passes when I set the copper width/distance to
>>>> 7mil's instead of the current 8 mils.
>>>>
>>>> I'm planning on having these PCB's manufactured by Seeed studio
and
>>>> their minimal width is much smaller.
>>>>
>>>> Minimum trace width: 6mil
>>>> Minimum trace/vias/pads space : 6mil
>>>> Minimum silkscreen width : 4mil
>>>> Minimum silkscreen text size : 32mil
>>>>
>>>> I've used a grid size of 10mil and distances of 8 mils, as I
didn't
>>>> want
>>>> to rely on the minimum of seed. The silkscreen I positioned using a
>>>> grid
>>>> size of 5 mil's however. Not sure what they mean with a 'minimum
>>>> silkscreen text size' however.
>>>>
>>>> Anyhow, feedback greatly appreciated, so I can start working on
>>>> alternative layouts :)
>>>>
>>>>
>>>
>>>
>>
>>
>>
>
>
>
>
12:01 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
Nobody interested at all?
I've since found that I can cut them more then adequatly with an
metal-saw and is much faster then using a break-away-knife. SO i should
have 80 adapters at FOSDEM.
You reccon it's better to give them away? or sell them for 50c - 1e?
This to prevent people from just randomly grabbing them cause its free
stuff and not actually even remotely intend to actually use them.
Oliver
On 01/19/14 18:45, Olliver Schinagl wrote:
Hi coreboot!
I finally sent off my order to seeed and have received the boards back.
It turns out, that over the last year (and a half) seeed actually
improved their processes and have even narrower minimals, which is great
for this board.
Anyway, I took some pics and the uploaded the schematics to [1]. I
rather host the schematics etc somewhere on coreboot's servers, as I
feel this is as use full to coreboot as anything else.
The only thing I'm not so happy about is the footprint of the FET
switch. The legs don't seem to match up perfectly (the outer ones only
strangely) and the pads should have been bigger to make soldering
easier. But since it is optional (if you bridge s1 and s2 the chip
doesn't have to be mounted, nor does RN1 I think, but it's been a while :p)
I haven't split all of the boards yet, but I should have tons! 12 * 8. I
am attending FOSDEM2014 so if any of the coreboot folk are having a
booth or even just attending, I'd be happy to bring the boards along so
they can be gifted. Anybody able to cut them though? I used a stanley
knife scorching the board but that took quite some time :) Using a
dremel requires extremely steady hands, as the cutting wheel probably
does fit, but it's extremely tight.
Anyway, looking forward to show it all off @FOSDEM2014 ;)
oliver
[1] http://oliver.schinagl.nl/gallery/v/geek_stuff/dspif/
Quoted the below to help remind people what this post is really about ;)
On 05/13/12 15:39, Oliver Schinagl wrote:
> Just an FYI,
>
> This is the final version that I will send over to seeed after placing
> an order. The only thing that will change is the order number (now it's
> an arbitrary number). If I have to do major changes to the board, I will
> of course send an updated version to the list.
>
> Oliver
>
> On 04/28/12 16:14, Oliver Schinagl wrote:
>> Hey all,
>>
>> Find here all included fixes and modifications. I've increased spacing
>> and removed the 'outline' layer. I moved parts to the edge. Since Seeed
>> does 5x5 boards, I'll assume that those 5x5 is after cutting? Assumption
>> is ...
>>
>> If I don't see any feedback on things that need fixing here, I'll set
>> out an order for the prototypes :)
>>
>> Oliver
>>
>> Have a good weekend all!
>>
>> On 04/26/12 18:56, Oliver Schinagl wrote:
>>> Hey all,
>>>
>>> Well here it is, the last version which was even harder then the 3rd
>>> one. or so it seemed anyhow.
>>>
>>> I will work on copying these four to the bottom and renaming the labels
>>> before sending them off. I'll post the final pcb on this list again,but
>>> routing wise, Nothing will change, unless of course someone found a
>>> grand mistake.
>>>
>>> So really, all input is greatly appreciated :D would be shameful to send
>>> this off to get printed, just to find bugs and have another batch made.
>>>
>>> Oliver
>>>
>>> On 23-04-12 20:23, Oliver Schinagl wrote:
>>>> Hi!
>>>>
>>>> I've worked on a rotated version and planning to do two other
>>>> orientations as well, so early feedback is good, so I don't have to
>>>> redo them again :)
>>>>
>>>> Silk screening isn't 100% right, since I still need to rename them
>>>> eventually somehow (edit .pcb file directly is probably the easiest
>>>> way?)
>>>>
>>>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>>>> Hi list(s),
>>>>>
>>>>> Here's my second attempt at routing the previously mailed png of
my
>>>>> schema.
>>>>>
>>>>> It was a lot trickier to route then my previous version, but I think
it
>>>>> worked out!
>>>>>
>>>>> As mentioned, S1 and S2 need to be shorted if U3 is to be omitted.
RN1
>>>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>>>
>>>>> Hopefully there's no obvious mistakes and can start working on
>>>>> alternative layouts (so it is insert-able in different angles).
>>>>>
>>>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to
shallow.
>>>>> That said, DRC check passes when I set the copper width/distance to
>>>>> 7mil's instead of the current 8 mils.
>>>>>
>>>>> I'm planning on having these PCB's manufactured by Seeed
studio and
>>>>> their minimal width is much smaller.
>>>>>
>>>>> Minimum trace width: 6mil
>>>>> Minimum trace/vias/pads space : 6mil
>>>>> Minimum silkscreen width : 4mil
>>>>> Minimum silkscreen text size : 32mil
>>>>>
>>>>> I've used a grid size of 10mil and distances of 8 mils, as I
didn't
>>>>> want
>>>>> to rely on the minimum of seed. The silkscreen I positioned using a
>>>>> grid
>>>>> size of 5 mil's however. Not sure what they mean with a
'minimum
>>>>> silkscreen text size' however.
>>>>>
>>>>> Anyhow, feedback greatly appreciated, so I can start working on
>>>>> alternative layouts :)
>>>>>
>>>>>
>>>>
>>>>
>>>
>>>
>>>
>>
>>
>>
>>
9:16 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
For all those that did not attend FOSDEM,
coreboot should have these in their hands now, happily sharing them in
future events!
P.S. Do not use a dremel to cut them :p If i didn't run out of time, I
would have cut them, so sorry on that end ...
oliver
On 25-01-14 12:01, Oliver Schinagl wrote:
Nobody interested at all?
I've since found that I can cut them more then adequatly with an
metal-saw and is much faster then using a break-away-knife. SO i
should have 80 adapters at FOSDEM.
You reccon it's better to give them away? or sell them for 50c - 1e?
This to prevent people from just randomly grabbing them cause its free
stuff and not actually even remotely intend to actually use them.
Oliver
On 01/19/14 18:45, Olliver Schinagl wrote:
> Hi coreboot!
>
> I finally sent off my order to seeed and have received the boards back.
> It turns out, that over the last year (and a half) seeed actually
> improved their processes and have even narrower minimals, which is great
> for this board.
>
> Anyway, I took some pics and the uploaded the schematics to [1]. I
> rather host the schematics etc somewhere on coreboot's servers, as I
> feel this is as use full to coreboot as anything else.
>
> The only thing I'm not so happy about is the footprint of the FET
> switch. The legs don't seem to match up perfectly (the outer ones only
> strangely) and the pads should have been bigger to make soldering
> easier. But since it is optional (if you bridge s1 and s2 the chip
> doesn't have to be mounted, nor does RN1 I think, but it's been a
> while :p)
>
> I haven't split all of the boards yet, but I should have tons! 12 * 8. I
> am attending FOSDEM2014 so if any of the coreboot folk are having a
> booth or even just attending, I'd be happy to bring the boards along so
> they can be gifted. Anybody able to cut them though? I used a stanley
> knife scorching the board but that took quite some time :) Using a
> dremel requires extremely steady hands, as the cutting wheel probably
> does fit, but it's extremely tight.
>
> Anyway, looking forward to show it all off @FOSDEM2014 ;)
>
> oliver
>
> [1] http://oliver.schinagl.nl/gallery/v/geek_stuff/dspif/
>
> Quoted the below to help remind people what this post is really about ;)
>
> On 05/13/12 15:39, Oliver Schinagl wrote:
>> Just an FYI,
>>
>> This is the final version that I will send over to seeed after placing
>> an order. The only thing that will change is the order number (now it's
>> an arbitrary number). If I have to do major changes to the board, I
>> will
>> of course send an updated version to the list.
>>
>> Oliver
>>
>> On 04/28/12 16:14, Oliver Schinagl wrote:
>>> Hey all,
>>>
>>> Find here all included fixes and modifications. I've increased spacing
>>> and removed the 'outline' layer. I moved parts to the edge. Since
>>> Seeed
>>> does 5x5 boards, I'll assume that those 5x5 is after cutting?
>>> Assumption
>>> is ...
>>>
>>> If I don't see any feedback on things that need fixing here, I'll
set
>>> out an order for the prototypes :)
>>>
>>> Oliver
>>>
>>> Have a good weekend all!
>>>
>>> On 04/26/12 18:56, Oliver Schinagl wrote:
>>>> Hey all,
>>>>
>>>> Well here it is, the last version which was even harder then the 3rd
>>>> one. or so it seemed anyhow.
>>>>
>>>> I will work on copying these four to the bottom and renaming the
>>>> labels
>>>> before sending them off. I'll post the final pcb on this list
>>>> again,but
>>>> routing wise, Nothing will change, unless of course someone found a
>>>> grand mistake.
>>>>
>>>> So really, all input is greatly appreciated :D would be shameful
>>>> to send
>>>> this off to get printed, just to find bugs and have another batch
>>>> made.
>>>>
>>>> Oliver
>>>>
>>>> On 23-04-12 20:23, Oliver Schinagl wrote:
>>>>> Hi!
>>>>>
>>>>> I've worked on a rotated version and planning to do two other
>>>>> orientations as well, so early feedback is good, so I don't have
to
>>>>> redo them again :)
>>>>>
>>>>> Silk screening isn't 100% right, since I still need to rename
them
>>>>> eventually somehow (edit .pcb file directly is probably the easiest
>>>>> way?)
>>>>>
>>>>> On 04/20/12 14:50, Oliver Schinagl wrote:
>>>>>> Hi list(s),
>>>>>>
>>>>>> Here's my second attempt at routing the previously mailed png
of my
>>>>>> schema.
>>>>>>
>>>>>> It was a lot trickier to route then my previous version, but I
>>>>>> think it
>>>>>> worked out!
>>>>>>
>>>>>> As mentioned, S1 and S2 need to be shorted if U3 is to be
>>>>>> omitted. RN1
>>>>>> should be 10k or ideally 100k, as Peter mentioned earlier.
>>>>>>
>>>>>> Hopefully there's no obvious mistakes and can start working
on
>>>>>> alternative layouts (so it is insert-able in different angles).
>>>>>>
>>>>>> DRC Check fails on S1, S2 and U3. It thinks the distance is to
>>>>>> shallow.
>>>>>> That said, DRC check passes when I set the copper width/distance
to
>>>>>> 7mil's instead of the current 8 mils.
>>>>>>
>>>>>> I'm planning on having these PCB's manufactured by Seeed
studio and
>>>>>> their minimal width is much smaller.
>>>>>>
>>>>>> Minimum trace width: 6mil
>>>>>> Minimum trace/vias/pads space : 6mil
>>>>>> Minimum silkscreen width : 4mil
>>>>>> Minimum silkscreen text size : 32mil
>>>>>>
>>>>>> I've used a grid size of 10mil and distances of 8 mils, as I
didn't
>>>>>> want
>>>>>> to rely on the minimum of seed. The silkscreen I positioned using
a
>>>>>> grid
>>>>>> size of 5 mil's however. Not sure what they mean with a
'minimum
>>>>>> silkscreen text size' however.
>>>>>>
>>>>>> Anyhow, feedback greatly appreciated, so I can start working on
>>>>>> alternative layouts :)
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>>>
>>>
>>>
>>>
>>>
>
>
9:16 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
On 25.1.2014 12:01, Oliver Schinagl wrote:
Nobody interested at all?
Well not true :) I thought immediately oh nice I always wanted to design that. I
was not in the FOSDEM this year, but if usual suspect have them, I will ask them
if they could ship it to me!
Anyway thanks for a great tool.
Thanks
Rudolf
8:32 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
With FOSDEM having slowly settled a bit, I was wondering if it is time
to setup a home for the files somewhere on coreboot. I'll write a wiki
page if i can find my account ;) but what's the best place to host the
design files? With it all being OSHW and coreboot.org marked on it; it
should live there imo :)
Olliver
On 02/03/14 21:16, Rudolf Marek wrote:
On 25.1.2014 12:01, Olliver Schinagl wrote:
> Nobody interested at all?
Well not true :) I thought immediately oh nice I always wanted to design that. I
was not in the FOSDEM this year, but if usual suspect have them, I will ask them
if they could ship it to me!
Anyway thanks for a great tool.
Thanks
Rudolf
8:48 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
Am Freitag, den 07.03.2014, 20:32 +0100 schrieb Olliver Schinagl:
With FOSDEM having slowly settled a bit, I was wondering if it is
time
to setup a home for the files somewhere on coreboot. I'll write a wiki
page if i can find my account ;) but what's the best place to host the
design files? With it all being OSHW and coreboot.org marked on it; it
should live there imo :)
A repository, so people can contribute! :-)
If you agree to that, I can set up a git repository. Through gitweb you
can link the files from wiki text.
Regards,
Patrick
9:13 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
Am 03.02.2014 21:16 schrieb Rudolf Marek:
On 25.1.2014 12:01, Oliver Schinagl wrote:
> Nobody interested at all?
Well not true :) I thought immediately oh nice I always wanted to
design that. I was not in the FOSDEM this year, but if usual suspect
have them, I will ask them if they could ship it to me!
I am the suspect in this case ;-)
Anyway thanks for a great tool.
Yes indeed.
Regards,
Carl-Daniel
--
http://www.hailfinger.org/
12:35 p.m.
New subject: Plans to give the DSPIF away at FOSDEM WAS: Re: Dual SPI Flash adapter attempt 2.0
With FOSDEM having slowly settled a bit, I was wondering if it is time
to setup a home for the files somewhere on coreboot. I'll write a wiki
page if i can find my account ;) but what's the best place to host the
design files? With it all being OSHW and coreboot.org marked on it; it
should live there imo :)
Olliver
On 02/03/14 21:16, Rudolf Marek wrote:
On 25.1.2014 12:01, Olliver Schinagl wrote:
> Nobody interested at all?
Well not true :) I thought immediately oh nice I always wanted to design that. I
was not in the FOSDEM this year, but if usual suspect have them, I will ask them
if they could ship it to me!
Anyway thanks for a great tool.
Thanks
Rudolf
1935
days inactive
2623
days old
19 comments
8 participants
participants (8)
-
Carl-Daniel Hailfinger -
Kai-Martin Knaak -
Oliver Schinagl -
Oliver Schinagl -
Olliver Schinagl
-
Patrick Georgi -
Peter Stuge -
Rudolf Marek