coreboot July 2021

coreboot@coreboot.org

21 participants
24 discussions

ThinkPad T420 and FireWire chip on Linux

by Alesandar Metodiev

Hello, Recently I have decided to give a try to coreboot for first time and flashed my ThinkPad T420, but a few weeks ago I have swapped the USB controller on the back, next to the battery, with a FireWire/USB controller (40GAB5809-G200) from another T420. Nothing special, since some models have been shipped like this. The controller is no longer accessible on my laptop. It seems like it may have been detected as an "SD Host Controller" or not detected at all. I will probably have to remove the chip and compare the output of lspci and lshw. If nothing has changed, I will probably have to return the stock BIOS and compare the results again. I have also tried to load some of the firewire kernel modules manually with modprobe. The operating systems I have tested so far are Arch Linux and Xubuntu. I am willing to provide more useful information, boot into a fresh Windows install, flash the chip again or whatever else. Correct me if I am wrong, but if I go back to the stock BIOS, the next time I flash, I will have to disassemble the laptop again and otherwise I must be fine with flashing internally, right? Thanks

2 months, 3 weeks

TigerLake RVP TCSS init failure

by Michal Zygowski

Dear coreboot community, I have encountered problem with silicon init on Tiger Lake RVP platform. I managed to resolve previous issues with memory initialization and now hitting an error with TCSS init. The FSP asserts on IOM ready check, which is 0. The configuration has selected CONFIG_USE_INTEL_FSP_MP_INIT (without MP PPI service). When the CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is selected, then the FSP-S returns smoothly (at least from one of the phases I guess) and resets after clearing MCEs in coreboot's CPU init: CPU: vendor Intel device 806c0 CPU: family 06, model 8c, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is available and visible CPU #0 initialized Initializing CPU #2 Initializing CPU #6 Initializing CPU #7 CPU: vendor Intel device 806c0 CPU: family 06, model 8c, stepping 00 CPU: vendor Intel device 806c0 CPU: family 06, model 8c, stepping 00 Clearing out pending MCEs Cl (tutaj następuje reset) Any ideas what may cause these issues? When I clean this up, I will upstream the DDR4 variant of TGL UP3 RVP. -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com

8 months, 1 week

Currently broken devicetrees (was Re: X200 dock has been broken since November 2019)

by Nico Huber

Hi all, that we had another case of a missing-device-below-chip in a devicetree made me write a patch for `sconfig` [1]. Now that it's checking for the issue, that uncovered a few (31) more cases [2] that need to be fixed before upstream can benefit from the patch. Please help to fix the devicetrees. Note, `sconfig` currently doesn't print the file name of override trees, e.g. when it says SCONFIG mainboard/.../devicetree.cb line 10: end: syntax error that might as well refer to line 10 in an override tree. Nico [1] https://review.coreboot.org/c/coreboot/+/51119 [2] https://qa.coreboot.org/job/coreboot-gerrit/164572/ Failing boards: board.AMD_BILBY board.AMD_CEREME board.AMD_MANDOLIN board.GETAC_P470 board.GOOGLE_BRYA0 board.GOOGLE_FALCO board.GOOGLE_PEPPY board.GOOGLE_WOLF board.KONTRON_BSL6 board.LENOVO_R500 board.LENOVO_T430S board.LENOVO_T431S board.LENOVO_T520 board.LENOVO_T530 board.LENOVO_W530 board.LENOVO_X1 board.LENOVO_X220 board.LENOVO_X220I board.LENOVO_X220_MRC_BIN board.LENOVO_X220_OPTION_TABLE_DEBUG_TPM_EXTENDED_CBFS board.LENOVO_X230 board.LENOVO_X230S board.LENOVO_X230T board.LENOVO_X301 board.LENOVO_X60 board.RODA_RK886EX board.SIEMENS_BOXER26

10 months

A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).

by dponamorev＠gmail.com

Hi! We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem. For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%). Intel confirmed that it might be so and that's okay ... Part of devicetree.cb: device cpu_cluster 0 on device lapic 4 on end end If we do not specify lapic id correctly in devicetree.cb, freeBSD OS does not BOOT (Unix like). FreeBSD BOOT log (set lapic #4 in devicetree.cb but need lapic #0): Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 APIC: Found table at 0x7f769420 APIC: Using the MADT enumerator. MADT: Found CPU APIC ID 0 ACPI ID 0: enabled SMP: Added CPU 0 (AP) MADT: Found CPU APIC ID 4 ACPI ID 1: enabled SMP: Added CPU 4 (AP) MADT: Found CPU APIC ID 12 ACPI ID 2: enabled SMP: Added CPU 12 (AP) MADT: Found CPU APIC ID 16 ACPI ID 3: enabled SMP: Added CPU 16 (AP) MADT: Found CPU APIC ID 24 ACPI ID 4: enabled SMP: Added CPU 24 (AP) Copyright (c) 1992-2019 The FreeBSD Project. Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994 The Regents of the University of California. All rights reserved. FreeBSD is a registered trademark of The FreeBSD Foundation. FreeBSD 11.3-RELEASE #0 r349754: Fri Jul 5 04:45:24 UTC 2019 root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64 FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0) Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 Table 'HPET' at 0x7f7694a0 ACPI: No SRAT table found PPIM 0: PA=0xa0000, VA=0xffffffff82410000, size=0x10000, mode=0 VT(vga): resolution 640x480 Preloaded elf kernel "/boot/kernel/kernel" at 0xffffffff8226d000. Calibrating TSC clock ... TSC clock: 2100071708 Hz CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz (2100.07-MHz K8-class CPU) Origin="GenuineIntel" Id=0x506f1 Family=0x6 Model=0x5f Stepping=1 Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE> Features2=0x4ff8ebbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,RDRAND> AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM> AMD Features2=0x101<LAHF,Prefetch> Structured Extended Features=0x2294e283<FSGSBASE,TSCADJ,SMEP,ERMS,NFPUSG,MPX,PQE,RDSEED,SMAP,CLFLUSHOPT,PROCTRACE,SHA> Structured Extended Features3=0xac000400<MD_CLEAR,IBPB,STIBP,ARCH_CAP,SSBD> XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES> IA32_ARCH_CAPS=0x69<RDCL_NO,SKIP_L1DFL_VME> VT-x: Basic Features=0xda0400<SMM,INS/OUTS,TRUE> Pin-Based Controls=0xff<ExtINT,NMI,VNMI,PreTmr,PostIntr> Primary Processor Controls=0xfff9fffe<INTWIN,TSCOff,HLT,INVLPG,MWAIT,RDPMC,RDTSC,CR3-LD,CR3-ST,CR8-LD,CR8-ST,TPR,NMIWIN,MOV-DR,IO,IOmap,MTF,MSRmap,MONITOR,PAUSE> Secondary Processor Controls=0x1d6fff<APIC,EPT,DT,RDTSCP,x2APIC,VPID,WBINVD,UG,APIC-reg,VID,PAUSE-loop,RDRAND,VMFUNC,VMCS,XSAVES> Exit Controls=0xda0400<PAT-LD,EFER-SV,PTMR-SV> Entry Controls=0xda0400 EPT Features=0x6334141<XO,PW4,UC,WB,2M,1G,INVEPT,AD,single,all> VPID Features=0xf01<INVVPID,individual,single,all,single-globals> TSC: P-state invariant, performance statistics DTLB: 4k pages, fully associative, 32 entries Data TLB: 4 KBytes pages, 4-way set associative, 512 entries Instruction TLB: 4 KByte pages, fully associative, 48 entries DTLB: 2M/4M Byte pages, 4-way associative, 32 entries L2 cache: 2048 kbytes, 16-way associative, 64 bytes/line real memory = 8589934592 (8192 MB) Physical memory chunk(s): 0x0000000000010000 - 0x000000000009bfff, 573440 bytes (140 pages) 0x0000000000100000 - 0x00000000001fffff, 1048576 bytes (256 pages) 0x0000000002400000 - 0x000000007f74ffff, 2100625408 bytes (512848 pages) 0x0000000100000000 - 0x000000027012efff, 6175256576 bytes (1507631 pages) avail memory = 8220336128 (7839 MB) Table 'FACP' at 0x7f768070 Table 'SSDT' at 0x7f768170 Table 'MCFG' at 0x7f7693e0 Table 'APIC' at 0x7f769420 Table 'HPET' at 0x7f7694a0 ACPI: No DMAR table found Event timer "LAPIC" quality 600 ACPI APIC Table: <COREv4 COREBOOT> WARNING: L1 data cache covers less APIC IDs than a core 0 < 1 Package ID shift: 5 L2 cache ID shift: 2 L1 cache ID shift: 1 Core ID shift: 1 panic: AP #4 (PHY# 0) failed! cpuid = 0 KDB: stack backtrace: #0 0xffffffff80b4c4b7 at kdb_backtrace+0x67 #1 0xffffffff80b054ce at vpanic+0x17e #2 0xffffffff80b05343 at panic+0x43 #3 0xffffffff80f752a4 at native_start_all_aps+0x344 #4 0xffffffff80f74c4f at cpu_mp_start+0x2ef #5 0xffffffff80b5cb76 at mp_start+0xa6 #6 0xffffffff80aa0b48 at mi_startup+0x118 #7 0xffffffff8031202c at btext+0x2c Uptime: 1s Other Linux OS boot but show an incorrect number of cores (5 instead of 4) and offline processor cores appear (see log). Ubuntu 18.04 LTS (GNU/Linux 4.15.0-20-generic x86_64) # lscpu Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian CPU(s): 5 On-line CPU(s) list: 0,2-4 Off-line CPU(s) list: 1 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 95 Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz Stepping: 1 CPU MHz: 2097.502 CPU max MHz: 2100.0000 CPU min MHz: 800.0000 BogoMIPS: 4200.00 Virtualization: VT-x L1d cache: 24K L1i cache: 32K L2 cache: 2048K NUMA node0 CPU(s): 0,2-4 What can be done in this situation? How to make a universal version of devicetree.cb?

10 months, 1 week

denverton_ns: failed to write RW_MRC_CACHE

by Sumo

Hi, I'm stuck in a problem where coreboot fails to write the MRC cache in the SPI Flash. Below is the log output: FMAP: area RW_MRC_CACHE found @ 810000 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 MRC: no data in 'RW_MRC_CACHE' MRC: cache data 'RW_MRC_CACHE' needs update. SPI Transaction Error at Flash Offset 810000 HSFSTS = 0x01046003 REGF metadata allocation failed: 1949 data blocks 4096 total blocks MRC: failed to update 'RW_MRC_CACHE'. Any clues? Thanks, Sumo

10 months, 2 weeks

Re: Question On External Display

by Rao G

Hi Nico, Thanks for your email & response. The problem originally I had was that on PortC, DP/HDMI did not work for the external display in the OS, In BIOS it looked good, so I configured PortC as an eDP interface then the external display started working in the OS. Now at runtime when there is no external display, the VBIOS is causing delay, so I want to disable PortC for eDP at runtime when there is no external display connected. So am trying to find which MMIO register gets set when there is external Display connected to DisplayPort Thanks Rao On Fri, Jul 30, 2021 at 3:29 PM Rao G <grao.v80(a)gmail.com> wrote: > Hi Nico, > > Thanks for your response, though I enabled Bits 29,28,27 in 0x61110h, the > values in 0x61114h returned 0, > I have configured the port as eDP in VBIOS not as HDMI/DP, will that > make a difference? > For eDP which MMIO register need to be checked? > > Thanks > Rao > > On Fri, Jul 30, 2021 at 2:47 PM Nico Huber <nico.h(a)gmx.de> wrote: > >> Hello Rao, >> >> On 30.07.21 13:53, Rao G wrote: >> > trying to see the MMIO or VBIOS data when a external display device is >> > plugged/unplugged with DP/HDMI interface, which MMIO register is set or >> > cleared >> >> I think you are looking at the right register (last one below). >> >> > >> > Any inputs are appreciated, some of the registers tried on Port B/Port C >> > are given below. when Display is connected and when Display is not >> > connected, both these instances >> > return the same data. Looking for register/bit that sets/clears when >> > external display is connected/disconnected >> > >> > printk(BIOS_DEBUG, "Intel Gfx BAR GTTMMADR\n"); >> > printk(BIOS_DEBUG, " DP_B %X\n", read32(bar+0x180000+0x64100)); >> > printk(BIOS_DEBUG, " DP_C %X\n", read32(bar+0x180000+0x64200)); >> > printk(BIOS_DEBUG, " HDMIC %X\n", read32(bar+0x180000+0x61160)); >> > printk(BIOS_DEBUG, " HDMIB %X\n", read32(bar+0x180000+0x61140)); >> > printk(BIOS_DEBUG, " Hotplug control %X\n", >> read32(bar+0x180000+0x61164)); >> > printk(BIOS_DEBUG, " pipeA control %X\n", read32(bar+0x180000+0x61204)); >> > printk(BIOS_DEBUG, " pipeB control %X\n", read32(bar+0x180000+0x61304)); >> > printk(BIOS_DEBUG, " porthot plug stat %X\n", >> read32(bar+0x180000+0x61114)); >> >> According to the datasheet, the bits in this register should change but >> only if enabled in PORT_HOTPLUG_EN (0x61110). >> >> Nico >> >> NB. There is also libgfxinit support under review [1]. In case you are >> trying to do some native graphics init ;) >> >> [1] https://review.coreboot.org/q/topic:%2522baytrail-libgfxinit%2522 >> >

10 months, 3 weeks

FsptUpd.h: No such file or directory - compilation terminated - Error 1

by James Feeney

$ cat defconfig ... CONFIG_ADD_FSP_BINARIES=y ... There is *no* "fspt.bin" file in this chromebook recovery bios file used as source. $ make ... src/soc/intel/apollolake/fspcar.c:3:10: fatal error: FsptUpd.h: No such file or directory #include <FsptUpd.h> ^~~~~~~~~~~ compilation terminated. make: *** [Makefile:379: build/bootblock/soc/intel/apollolake/fspcar.o] Error 1 What Makefile is that? There is no such line 379. $ find -name FsptUpd.h ... ./3rdparty/fsp/ApolloLakeFspBinPkg/Include/FsptUpd.h ... $ less src/soc/intel/alderlake/Kconfig ... config FSP_HEADER_PATH string "Location of FSP headers" default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" $ less src/drivers/intel/fsp2_0/Kconfig ... config FSP_T_FILE string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES depends on FSP_CAR default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-T binary for this platform. $ make nconfig ... > Generic Drivers ... (src/vendorcode/intel/fsp/fsp2_0/glk) Location of FSP headers How did that get there? Not me... $ ll src/vendorcode/intel/fsp/fsp2_0/glk total 116 drwxr-x--- 2 james james 4096 Oct 29 2020 . drwxr-x--- 9 james james 4096 Jun 14 19:04 .. -rw-r----- 1 james james 45977 Oct 29 2020 FspmUpd.h -rw-r----- 1 james james 57332 Oct 29 2020 FspsUpd.h -rw-r----- 1 james james 1967 Oct 29 2020 FspUpd.h Why is src/soc/intel/apollolake/fspcar.c being built here? It seems that no fspt.bin file is needed. James

11 months

Does coreboot support ASRock H110M-DVS R3.0?

by Alexander Zhang

Hello, Does anyone know if coreboot supports the ASRock H110M-DVS R3.0 mainboard? The documentation doesn't mention the revision number but the links are all for the R2.0 board and I can only find R3.0 boards for sale. Thanks, Alex

11 months

[coreboot - Bug #314] (New) Please disable 'administrator approval' on ticket.coreboot.org

by coreboot＠fe80.eu

Issue #314 has been reported by akjuxr3 akjuxr3. ---------------------------------------- Bug #314: Please disable 'administrator approval' on ticket.coreboot.org https://ticket.coreboot.org/issues/314 * Author: akjuxr3 akjuxr3 * Status: New * Priority: Normal * Assignee: * Category: infrastructure * Target version: ---------------------------------------- Please disable this 'administrator approval' on ticket.coreboot.org. It feels like discrimination. Before i have written the first word on ticket.coreboot.org i have to be approved by someone by hand without this person knowing anything from me. I had to wait several days for this approval. Its completely unclear what is been tracked. Have the IP-address used for registration been tracked? Have the used email-address been tracked? E-mail-address-discrimination is illegal in many countries and this is completely breaking the freedom of choice! Username? Choosing (user)names is up to the user and making decision based on what names are 'allowed' to enter a platform is the most racist thing possible. Conclusion: This 'administrator approval' is sort of discrimination i have not seen for years on free projects! There is no data available at the registration process that could or should be used to decide who is allowed to report a bug in the coreboot project. Please disable this discrimination that is stopping people for days or even forever to report a coreboot issue. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

11 months, 1 week

New Defects reported by Coverity Scan for coreboot

by scan-admin＠coverity.com

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 20 new defect(s) introduced to coreboot found with Coverity Scan. 13 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 20 of 20 defect(s) ** CID 1461240: Control flow issues (DEADCODE) /3rdparty/chromeec/core/cortex-m/watchdog.c: 37 in watchdog_trace() ________________________________________________________________________________________________________ *** CID 1461240: Control flow issues (DEADCODE) /3rdparty/chromeec/core/cortex-m/watchdog.c: 37 in watchdog_trace() 31 32 /* 33 * This is our last breath, the last opportunity to sort out all 34 * matters. Flush and invalidate D-cache if cache enabled. 35 */ 36 if (IS_ENABLED(CONFIG_ARMV7M_CACHE)) >>> CID 1461240: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "cpu_clean_invalidate_dcache();". 37 cpu_clean_invalidate_dcache(); 38 39 panic_printf("### WATCHDOG PC=%08x / LR=%08x / pSP=%08x ", 40 stack[6], stack[5], psp); 41 if ((excep_lr & 0xf) == 1) 42 panic_puts("(exc) ###\n"); ** CID 1461239: (PARSE_ERROR) /3rdparty/chromeec/common/shared_mem.c: 19 in () /3rdparty/chromeec/common/shared_mem.c: 19 in () /3rdparty/chromeec/common/shared_mem.c: 19 in () ________________________________________________________________________________________________________ *** CID 1461239: (PARSE_ERROR) /3rdparty/chromeec/common/shared_mem.c: 19 in () 13 #include "util.h" 14 15 static int buf_in_use; 16 static int max_used; 17 18 /* 1 MB buffer for fake shared memory implementation */ >>> CID 1461239: (PARSE_ERROR) >>> expression must be an integral constant expression 19 STATIC_IF(CONFIG_FAKE_SHMEM) char fake_shmem_buf[BIT(20)]; 20 21 int shared_mem_size(void) 22 { 23 if (IS_ENABLED(CONFIG_FAKE_SHMEM)) 24 return sizeof(fake_shmem_buf); /3rdparty/chromeec/common/shared_mem.c: 19 in () 13 #include "util.h" 14 15 static int buf_in_use; 16 static int max_used; 17 18 /* 1 MB buffer for fake shared memory implementation */ >>> CID 1461239: (PARSE_ERROR) >>> function call is not allowed in a constant expression 19 STATIC_IF(CONFIG_FAKE_SHMEM) char fake_shmem_buf[BIT(20)]; 20 21 int shared_mem_size(void) 22 { 23 if (IS_ENABLED(CONFIG_FAKE_SHMEM)) 24 return sizeof(fake_shmem_buf); /3rdparty/chromeec/common/shared_mem.c: 19 in () 13 #include "util.h" 14 15 static int buf_in_use; 16 static int max_used; 17 18 /* 1 MB buffer for fake shared memory implementation */ >>> CID 1461239: (PARSE_ERROR) >>> expression must have integral type 19 STATIC_IF(CONFIG_FAKE_SHMEM) char fake_shmem_buf[BIT(20)]; 20 21 int shared_mem_size(void) 22 { 23 if (IS_ENABLED(CONFIG_FAKE_SHMEM)) 24 return sizeof(fake_shmem_buf); ** CID 1461238: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 1312 in svdm_dp_post_config() ________________________________________________________________________________________________________ *** CID 1461238: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 1312 in svdm_dp_post_config() 1306 1307 __overridable void svdm_dp_post_config(int port) 1308 { 1309 mux_state_t mux_mode = svdm_dp_get_mux_mode(port); 1310 /* Connect the SBU and USB lines to the connector. */ 1311 if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) >>> CID 1461238: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "ppc_set_sbu(port, 1);". 1312 ppc_set_sbu(port, 1); 1313 usb_mux_set(port, mux_mode, USB_SWITCH_CONNECT, 1314 polarity_rm_dts(pd_get_polarity(port))); 1315 1316 dp_flags[port] |= DP_FLAGS_DP_ON; 1317 if (!(dp_flags[port] & DP_FLAGS_HPD_HI_PENDING)) ** CID 1461237: Control flow issues (DEADCODE) /3rdparty/chromeec/common/motion_sense.c: 446 in motion_sense_switch_sensor_rate() ________________________________________________________________________________________________________ *** CID 1461237: Control flow issues (DEADCODE) /3rdparty/chromeec/common/motion_sense.c: 446 in motion_sense_switch_sensor_rate() 440 /* No sensor activated, reset host interval interval to 0. */ 441 ap_event_interval = 0; 442 } 443 444 /* disable the body detection since AP is suspended */ 445 if (IS_ENABLED(CONFIG_BODY_DETECTION)) { >>> CID 1461237: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "static _Bool was_enabled;". 446 static bool was_enabled; 447 448 switch (sensor_active) { 449 case SENSOR_ACTIVE_S3: 450 was_enabled = body_detect_get_enable(); 451 body_detect_set_enable(false); ** CID 1461236: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/chargen.c: 95 in command_chargen() ________________________________________________________________________________________________________ *** CID 1461236: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/chargen.c: 95 in command_chargen() 89 continue; 90 91 watchdog_reload(); 92 prev_watchdog_time.val = current_time.val; 93 } 94 >>> CID 1461236: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && c == 48" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 95 if (IS_ENABLED(CONFIG_ZEPHYR) && c == '0') 96 watchdog_reload(); 97 98 putc_(c++); 99 100 if (seq_number && (++seq_counter == seq_number)) ** CID 1461235: Control flow issues (DEADCODE) /3rdparty/chromeec/common/panic_output.c: 182 in get_panic_data_start() ________________________________________________________________________________________________________ *** CID 1461235: Control flow issues (DEADCODE) /3rdparty/chromeec/common/panic_output.c: 182 in get_panic_data_start() 176 uintptr_t get_panic_data_start(void) 177 { 178 if (pdata_ptr->magic != PANIC_DATA_MAGIC) 179 return 0; 180 181 if (IS_ENABLED(CONFIG_ZEPHYR)) >>> CID 1461235: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return (uintptr_t)pdata_ptr;". 182 return (uintptr_t)pdata_ptr; 183 184 return ((uintptr_t)CONFIG_PANIC_DATA_BASE 185 + CONFIG_PANIC_DATA_SIZE 186 - pdata_ptr->struct_size); 187 } ** CID 1461234: Control flow issues (DEADCODE) /3rdparty/chromeec/common/system.c: 850 in system_get_board_version() ________________________________________________________________________________________________________ *** CID 1461234: Control flow issues (DEADCODE) /3rdparty/chromeec/common/system.c: 850 in system_get_board_version() 844 */ 845 int system_get_board_version(void) 846 { 847 int board_id; 848 849 if (IS_ENABLED(CONFIG_BOARD_VERSION_CBI)) { >>> CID 1461234: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "int error;". 850 int error; 851 852 error = cbi_get_board_version(&board_id); 853 if (error) 854 return -error; 855 ** CID 1461233: Control flow issues (DEADCODE) /3rdparty/chromeec/common/charge_manager.c: 418 in charge_manager_fill_power_info() ________________________________________________________________________________________________________ *** CID 1461233: Control flow issues (DEADCODE) /3rdparty/chromeec/common/charge_manager.c: 418 in charge_manager_fill_power_info() 412 r->type = USB_CHG_TYPE_NONE; 413 r->meas.voltage_max = 0; 414 r->meas.voltage_now = 415 r->role == USB_PD_PORT_POWER_SOURCE ? 5000 : 0; 416 /* TCPMv2 tracks source-out current in the DPM */ 417 if (IS_ENABLED(CONFIG_USB_PD_TCPMV2)) >>> CID 1461233: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "r->meas.current_max = dpm_g...". 418 r->meas.current_max = 419 dpm_get_source_current(port); 420 else 421 r->meas.current_max = 422 charge_manager_get_source_current(port); 423 r->max_power = 0; ** CID 1461232: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 896 in is_tbt_cable_superspeed() ________________________________________________________________________________________________________ *** CID 1461232: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 896 in is_tbt_cable_superspeed() 890 if (disc->identity.idh.product_type == IDH_PTYPE_ACABLE) 891 return true; 892 893 if (disc->identity.idh.product_type != IDH_PTYPE_PCABLE) 894 return false; 895 >>> CID 1461232: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && is_pd_rev3(port, TCPC_TX_SOP_PRIME)" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 896 if (IS_ENABLED(CONFIG_USB_PD_REV30) && 897 is_pd_rev3(port, TCPC_TX_SOP_PRIME)) 898 return disc->identity.product_t1.p_rev30.ss == 899 USB_R30_SS_U32_U40_GEN1 || 900 disc->identity.product_t1.p_rev30.ss == 901 USB_R30_SS_U32_U40_GEN2 || ** CID 1461231: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_common.c: 542 in usb_mux_set_safe_mode_exit() ________________________________________________________________________________________________________ *** CID 1461231: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_common.c: 542 in usb_mux_set_safe_mode_exit() 536 if (IS_ENABLED(CONFIG_USBC_SS_MUX)) 537 usb_mux_set(port, USB_PD_MUX_NONE, USB_SWITCH_CONNECT, 538 polarity_rm_dts(pd_get_polarity(port))); 539 540 /* Isolate the SBU lines. */ 541 if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) >>> CID 1461231: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "ppc_set_sbu(port, 0);". 542 ppc_set_sbu(port, 0); 543 } 544 545 static void pd_send_hard_reset(int port) 546 { 547 task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_SEND_HARD_RESET); ** CID 1461230: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 197 in pd_dfp_dp_get_pin_mode() ________________________________________________________________________________________________________ *** CID 1461230: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 197 in pd_dfp_dp_get_pin_mode() 191 /* 192 * Default dp_port_mf_allow is true, we allow mf operation 193 * if UFP_D supports it. 194 */ 195 196 if (IS_ENABLED(CONFIG_CMD_MFALLOW)) >>> CID 1461230: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "mf_pref" inside this statement: "mf_pref = (dp_status[port] ...". 197 mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) && 198 dp_port_mf_allow[port]; 199 else 200 mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); 201 202 if (!modep) ** CID 1461229: Control flow issues (DEADCODE) /3rdparty/chromeec/common/uart_buffering.c: 112 in uart_tx_char_raw() ________________________________________________________________________________________________________ *** CID 1461229: Control flow issues (DEADCODE) /3rdparty/chromeec/common/uart_buffering.c: 112 in uart_tx_char_raw() 106 tx_next_snapshot_head = tx_buf_new_tail; 107 108 tx_buf[tx_buf_head] = c; 109 tx_buf_head = tx_buf_next; 110 111 if (IS_ENABLED(CONFIG_PRESERVE_LOGS)) >>> CID 1461229: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "tx_checksum = uart_buffer_c...". 112 tx_checksum = uart_buffer_calc_checksum(); 113 #endif 114 return 0; 115 } 116 117 #ifdef CONFIG_UART_TX_DMA ** CID 1461228: Control flow issues (DEADCODE) /3rdparty/chromeec/common/system.c: 126 in system_get_sku_id() ________________________________________________________________________________________________________ *** CID 1461228: Control flow issues (DEADCODE) /3rdparty/chromeec/common/system.c: 126 in system_get_sku_id() 120 return 0; 121 } 122 123 uint32_t system_get_sku_id(void) 124 { 125 if (IS_ENABLED(CONFIG_HOSTCMD_AP_SET_SKUID)) >>> CID 1461228: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return ap_sku_id;". 126 return ap_sku_id; 127 128 return board_get_sku_id(); 129 } 130 131 /** ** CID 1461227: Control flow issues (DEADCODE) /3rdparty/chromeec/common/charger.c: 460 in charger_discharge_on_ac() ________________________________________________________________________________________________________ *** CID 1461227: Control flow issues (DEADCODE) /3rdparty/chromeec/common/charger.c: 460 in charger_discharge_on_ac() 454 enum ec_error_list charger_discharge_on_ac(int enable) 455 { 456 int chgnum; 457 int rv = EC_ERROR_UNIMPLEMENTED; 458 459 if (IS_ENABLED(CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM)) >>> CID 1461227: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return board_discharge_on_a...". 460 return board_discharge_on_ac(enable); 461 462 /* 463 * When discharge on AC is selected, cycle through all chargers to 464 * enable or disable this feature. 465 */ ** CID 1461226: Control flow issues (DEADCODE) /3rdparty/chromeec/core/cortex-m/panic.c: 427 in ignore_bus_fault() ________________________________________________________________________________________________________ *** CID 1461226: Control flow issues (DEADCODE) /3rdparty/chromeec/core/cortex-m/panic.c: 427 in ignore_bus_fault() 421 exception_panic(); 422 } 423 424 void ignore_bus_fault(int ignored) 425 { 426 if (IS_ENABLED(CHIP_FAMILY_STM32H7)) { >>> CID 1461226: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "if (ignored == 0) asm("ds...". 427 if (ignored == 0) 428 asm volatile("dsb; isb"); 429 } 430 431 /* 432 * Flash code might call this before cpu_init(), ** CID 1461225: Control flow issues (DEADCODE) /3rdparty/chromeec/common/system.c: 333 in get_jump_data() ________________________________________________________________________________________________________ *** CID 1461225: Control flow issues (DEADCODE) /3rdparty/chromeec/common/system.c: 333 in get_jump_data() 327 */ 328 if (IS_ENABLED(CONFIG_ZEPHYR)) { 329 /* 330 * For Zephyr, the panic data is not at the end of RAM so 331 * the jump data is always at the end of RAM. 332 */ >>> CID 1461225: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "addr = 536903680U;". 333 addr = CONFIG_RAM_BASE + CONFIG_RAM_SIZE; 334 } else { 335 addr = get_panic_data_start(); 336 if (!addr) 337 addr = CONFIG_RAM_BASE + CONFIG_RAM_SIZE; 338 } ** CID 1461224: Control flow issues (DEADCODE) /3rdparty/chromeec/common/keyboard_scan.c: 616 in board_keyboard_row_refresh() ________________________________________________________________________________________________________ *** CID 1461224: Control flow issues (DEADCODE) /3rdparty/chromeec/common/keyboard_scan.c: 616 in board_keyboard_row_refresh() 610 } 611 612 static uint8_t keyboard_mask_refresh; 613 __overridable uint8_t board_keyboard_row_refresh(void) 614 { 615 if (IS_ENABLED(CONFIG_KEYBOARD_REFRESH_ROW3)) >>> CID 1461224: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "return 3;". 616 return 3; 617 else 618 return 2; 619 } 620 621 #ifdef CONFIG_KEYBOARD_BOOT_KEYS ** CID 1461223: (DEADCODE) /3rdparty/chromeec/util/genvif.c: 3379 in init_vif_component_pd_source_fields() /3rdparty/chromeec/util/genvif.c: 3384 in init_vif_component_pd_source_fields() ________________________________________________________________________________________________________ *** CID 1461223: (DEADCODE) /3rdparty/chromeec/util/genvif.c: 3379 in init_vif_component_pd_source_fields() 3373 switch (resp) { 3374 case 0: 3375 set_vif_field(&vif_fields[PD_OCP_Method], 3376 vif_component_name[PD_OCP_Method], 3377 "0", "Over-Current Response"); 3378 break; >>> CID 1461223: (DEADCODE) >>> Execution cannot reach this statement: "case 1:". 3379 case 1: 3380 set_vif_field(&vif_fields[PD_OCP_Method], 3381 vif_component_name[PD_OCP_Method], 3382 "1", "Under-Voltage Response"); 3383 break; 3384 case 2: /3rdparty/chromeec/util/genvif.c: 3384 in init_vif_component_pd_source_fields() 3378 break; 3379 case 1: 3380 set_vif_field(&vif_fields[PD_OCP_Method], 3381 vif_component_name[PD_OCP_Method], 3382 "1", "Under-Voltage Response"); 3383 break; >>> CID 1461223: (DEADCODE) >>> Execution cannot reach this statement: "case 2:". 3384 case 2: 3385 set_vif_field(&vif_fields[PD_OCP_Method], 3386 vif_component_name[PD_OCP_Method], 3387 "2", "Both"); 3388 break; 3389 default: ** CID 1461222: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/motion_sense.c: 970 in motion_sense_task() ________________________________________________________________________________________________________ *** CID 1461222: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/motion_sense.c: 970 in motion_sense_task() 964 /* 965 * Ask the host to flush the queue if 966 * - a flush event has been queued. 967 * - the queue is almost full, 968 * - we haven't done it for a while. 969 */ >>> CID 1461222: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && (motion_sense_fifo_bypass_needed() || event & (768U /* (1U << 8 + 1) / !!((1U << 8 + 1) & 65535) | (1U << 8) / !!((1U << 8) & 65535) */) || motion_sense_fifo_over_thres() || (ap_event_interval > 0 && time_after(ts_begin_task.le.lo, ts_last_int.le.lo + ap_event_interval)))" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 970 if (IS_ENABLED(CONFIG_ACCEL_FIFO) && 971 (motion_sense_fifo_bypass_needed() || 972 event & (TASK_EVENT_MOTION_ODR_CHANGE | 973 TASK_EVENT_MOTION_FLUSH_PENDING) || 974 motion_sense_fifo_over_thres() || 975 (ap_event_interval > 0 && ** CID 1461221: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 1241 in svdm_dp_get_mux_mode() ________________________________________________________________________________________________________ *** CID 1461221: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_alt_mode_dfp.c: 1241 in svdm_dp_get_mux_mode() 1235 { 1236 int pin_mode = get_dp_pin_mode(port); 1237 /* Default dp_port_mf_allow is true */ 1238 int mf_pref; 1239 1240 if (IS_ENABLED(CONFIG_CMD_MFALLOW)) >>> CID 1461221: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "mf_pref" inside this statement: "mf_pref = (dp_status[port] ...". 1241 mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]) && 1242 dp_port_mf_allow[port]; 1243 else 1244 mf_pref = PD_VDO_DPSTS_MF_PREF(dp_status[port]); 1245 1246 /* ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

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coreboot July 2021