Hello,
Recently I have decided to give a try to coreboot for first time and
flashed my ThinkPad T420, but a few weeks ago I have swapped the USB
controller on the back, next to the battery, with a FireWire/USB controller
(40GAB5809-G200) from another T420. Nothing special, since some models have
been shipped like this. The controller is no longer accessible on my laptop.
It seems like it may have been detected as an "SD Host Controller" or not
detected at all. I will probably have to remove the chip and compare the
output of lspci and lshw. If nothing has changed, I will probably have to
return the stock BIOS and compare the results again. I have also tried to
load some of the firewire kernel modules manually with modprobe.
The operating systems I have tested so far are Arch Linux and Xubuntu. I am
willing to provide more useful information, boot into a fresh Windows
install, flash the chip again or whatever else. Correct me if I am wrong,
but if I go back to the stock BIOS, the next time I flash, I will have to
disassemble the laptop again and otherwise I must be fine with flashing
internally, right?
Thanks
Dear coreboot community,
I have encountered problem with silicon init on Tiger Lake RVP platform.
I managed to resolve previous issues with memory initialization and now
hitting an error with TCSS init. The FSP asserts on IOM ready check,
which is 0. The configuration has selected CONFIG_USE_INTEL_FSP_MP_INIT
(without MP PPI service).
When the CONFIG_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI is
selected, then the FSP-S returns smoothly (at least from one of the
phases I guess) and resets after clearing MCEs in coreboot's CPU init:
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
Clearing out pending MCEs
Setting up local APIC...
apic_id: 0x00 done.
Turbo is available but hidden
Turbo is available and visible
CPU #0 initialized
Initializing CPU #2
Initializing CPU #6
Initializing CPU #7
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
CPU: vendor Intel device 806c0
CPU: family 06, model 8c, stepping 00
Clearing out pending MCEs
Cl (tutaj następuje reset)
Any ideas what may cause these issues? When I clean this up, I will
upstream the DDR4 variant of TGL UP3 RVP.
--
Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com
Hi all,
that we had another case of a missing-device-below-chip in a devicetree
made me write a patch for `sconfig` [1]. Now that it's checking for the
issue, that uncovered a few (31) more cases [2] that need to be fixed
before upstream can benefit from the patch. Please help to fix the
devicetrees.
Note, `sconfig` currently doesn't print the file name of override trees,
e.g. when it says
SCONFIG mainboard/.../devicetree.cb
line 10: end: syntax error
that might as well refer to line 10 in an override tree.
Nico
[1] https://review.coreboot.org/c/coreboot/+/51119
[2] https://qa.coreboot.org/job/coreboot-gerrit/164572/
Failing boards:
board.AMD_BILBY
board.AMD_CEREME
board.AMD_MANDOLIN
board.GETAC_P470
board.GOOGLE_BRYA0
board.GOOGLE_FALCO
board.GOOGLE_PEPPY
board.GOOGLE_WOLF
board.KONTRON_BSL6
board.LENOVO_R500
board.LENOVO_T430S
board.LENOVO_T431S
board.LENOVO_T520
board.LENOVO_T530
board.LENOVO_W530
board.LENOVO_X1
board.LENOVO_X220
board.LENOVO_X220I
board.LENOVO_X220_MRC_BIN
board.LENOVO_X220_OPTION_TABLE_DEBUG_TPM_EXTENDED_CBFS
board.LENOVO_X230
board.LENOVO_X230S
board.LENOVO_X230T
board.LENOVO_X301
board.LENOVO_X60
board.RODA_RK886EX
board.SIEMENS_BOXER26
Hi!
We developed our CRB motherboard on Intel Atom C3538 (4 core) Denverton_NS processor. Faced with the following problem.
For part of processors with the same SKU and steping (Atom C3538), lapic #4 in devicetree.cb needed (95%), and for the other part lapic #0 (5%).
Intel confirmed that it might be so and that's okay ...
Part of devicetree.cb:
device cpu_cluster 0 on
device lapic 4 on end
end
If we do not specify lapic id correctly in devicetree.cb, freeBSD OS does not BOOT (Unix like).
FreeBSD BOOT log (set lapic #4 in devicetree.cb but need lapic #0):
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
APIC: Found table at 0x7f769420
APIC: Using the MADT enumerator.
MADT: Found CPU APIC ID 0 ACPI ID 0: enabled
SMP: Added CPU 0 (AP)
MADT: Found CPU APIC ID 4 ACPI ID 1: enabled
SMP: Added CPU 4 (AP)
MADT: Found CPU APIC ID 12 ACPI ID 2: enabled
SMP: Added CPU 12 (AP)
MADT: Found CPU APIC ID 16 ACPI ID 3: enabled
SMP: Added CPU 16 (AP)
MADT: Found CPU APIC ID 24 ACPI ID 4: enabled
SMP: Added CPU 24 (AP)
Copyright (c) 1992-2019 The FreeBSD Project.
Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1994
The Regents of the University of California. All rights reserved.
FreeBSD is a registered trademark of The FreeBSD Foundation.
FreeBSD 11.3-RELEASE #0 r349754: Fri Jul 5 04:45:24 UTC 2019
root@releng2.nyi.freebsd.org:/usr/obj/usr/src/sys/GENERIC amd64
FreeBSD clang version 8.0.0 (tags/RELEASE_800/final 356365) (based on LLVM 8.0.0)
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
Table 'HPET' at 0x7f7694a0
ACPI: No SRAT table found
PPIM 0: PA=0xa0000, VA=0xffffffff82410000, size=0x10000, mode=0
VT(vga): resolution 640x480
Preloaded elf kernel "/boot/kernel/kernel" at 0xffffffff8226d000.
Calibrating TSC clock ... TSC clock: 2100071708 Hz
CPU: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz (2100.07-MHz K8-class CPU)
Origin="GenuineIntel" Id=0x506f1 Family=0x6 Model=0x5f Stepping=1
Features=0xbfebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,DTS,ACPI,MMX,FXSR,SSE,SSE2,SS,HTT,TM,PBE>
Features2=0x4ff8ebbf<SSE3,PCLMULQDQ,DTES64,MON,DS_CPL,VMX,EST,TM2,SSSE3,SDBG,CX16,xTPR,PDCM,SSE4.1,SSE4.2,x2APIC,MOVBE,POPCNT,TSCDLT,AESNI,XSAVE,OSXSAVE,RDRAND>
AMD Features=0x2c100800<SYSCALL,NX,Page1GB,RDTSCP,LM>
AMD Features2=0x101<LAHF,Prefetch>
Structured Extended Features=0x2294e283<FSGSBASE,TSCADJ,SMEP,ERMS,NFPUSG,MPX,PQE,RDSEED,SMAP,CLFLUSHOPT,PROCTRACE,SHA>
Structured Extended Features3=0xac000400<MD_CLEAR,IBPB,STIBP,ARCH_CAP,SSBD>
XSAVE Features=0xf<XSAVEOPT,XSAVEC,XINUSE,XSAVES>
IA32_ARCH_CAPS=0x69<RDCL_NO,SKIP_L1DFL_VME>
VT-x: Basic Features=0xda0400<SMM,INS/OUTS,TRUE>
Pin-Based Controls=0xff<ExtINT,NMI,VNMI,PreTmr,PostIntr>
Primary Processor Controls=0xfff9fffe<INTWIN,TSCOff,HLT,INVLPG,MWAIT,RDPMC,RDTSC,CR3-LD,CR3-ST,CR8-LD,CR8-ST,TPR,NMIWIN,MOV-DR,IO,IOmap,MTF,MSRmap,MONITOR,PAUSE>
Secondary Processor Controls=0x1d6fff<APIC,EPT,DT,RDTSCP,x2APIC,VPID,WBINVD,UG,APIC-reg,VID,PAUSE-loop,RDRAND,VMFUNC,VMCS,XSAVES>
Exit Controls=0xda0400<PAT-LD,EFER-SV,PTMR-SV>
Entry Controls=0xda0400
EPT Features=0x6334141<XO,PW4,UC,WB,2M,1G,INVEPT,AD,single,all>
VPID Features=0xf01<INVVPID,individual,single,all,single-globals>
TSC: P-state invariant, performance statistics
DTLB: 4k pages, fully associative, 32 entries
Data TLB: 4 KBytes pages, 4-way set associative, 512 entries
Instruction TLB: 4 KByte pages, fully associative, 48 entries
DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
L2 cache: 2048 kbytes, 16-way associative, 64 bytes/line
real memory = 8589934592 (8192 MB)
Physical memory chunk(s):
0x0000000000010000 - 0x000000000009bfff, 573440 bytes (140 pages)
0x0000000000100000 - 0x00000000001fffff, 1048576 bytes (256 pages)
0x0000000002400000 - 0x000000007f74ffff, 2100625408 bytes (512848 pages)
0x0000000100000000 - 0x000000027012efff, 6175256576 bytes (1507631 pages)
avail memory = 8220336128 (7839 MB)
Table 'FACP' at 0x7f768070
Table 'SSDT' at 0x7f768170
Table 'MCFG' at 0x7f7693e0
Table 'APIC' at 0x7f769420
Table 'HPET' at 0x7f7694a0
ACPI: No DMAR table found
Event timer "LAPIC" quality 600
ACPI APIC Table: <COREv4 COREBOOT>
WARNING: L1 data cache covers less APIC IDs than a core
0 < 1
Package ID shift: 5
L2 cache ID shift: 2
L1 cache ID shift: 1
Core ID shift: 1
panic: AP #4 (PHY# 0) failed!
cpuid = 0
KDB: stack backtrace:
#0 0xffffffff80b4c4b7 at kdb_backtrace+0x67
#1 0xffffffff80b054ce at vpanic+0x17e
#2 0xffffffff80b05343 at panic+0x43
#3 0xffffffff80f752a4 at native_start_all_aps+0x344
#4 0xffffffff80f74c4f at cpu_mp_start+0x2ef
#5 0xffffffff80b5cb76 at mp_start+0xa6
#6 0xffffffff80aa0b48 at mi_startup+0x118
#7 0xffffffff8031202c at btext+0x2c
Uptime: 1s
Other Linux OS boot but show an incorrect number of cores (5 instead of 4) and offline processor cores appear (see log).
Ubuntu 18.04 LTS (GNU/Linux 4.15.0-20-generic x86_64)
# lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 5
On-line CPU(s) list: 0,2-4
Off-line CPU(s) list: 1
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 95
Model name: Intel(R) Atom(TM) CPU C3538 @ 2.10GHz
Stepping: 1
CPU MHz: 2097.502
CPU max MHz: 2100.0000
CPU min MHz: 800.0000
BogoMIPS: 4200.00
Virtualization: VT-x
L1d cache: 24K
L1i cache: 32K
L2 cache: 2048K
NUMA node0 CPU(s): 0,2-4
What can be done in this situation? How to make a universal version of devicetree.cb?
Hi,
I'm stuck in a problem where coreboot fails to write the MRC cache in the
SPI Flash.
Below is the log output:
FMAP: area RW_MRC_CACHE found @ 810000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
SPI Transaction Error at Flash Offset 810000 HSFSTS = 0x01046003
REGF metadata allocation failed: 1949 data blocks 4096 total blocks
MRC: failed to update 'RW_MRC_CACHE'.
Any clues?
Thanks,
Sumo
Hi Nico,
Thanks for your email & response.
The problem originally I had was that on PortC, DP/HDMI did not work for
the external display in the OS, In BIOS it looked good,
so I configured PortC as an eDP interface then the external display started
working in the OS.
Now at runtime when there is no external display, the VBIOS is causing
delay, so I want to disable PortC for eDP at runtime when there is no
external display connected.
So am trying to find which MMIO register gets set when there is external
Display connected to DisplayPort
Thanks
Rao
On Fri, Jul 30, 2021 at 3:29 PM Rao G <grao.v80(a)gmail.com> wrote:
> Hi Nico,
>
> Thanks for your response, though I enabled Bits 29,28,27 in 0x61110h, the
> values in 0x61114h returned 0,
> I have configured the port as eDP in VBIOS not as HDMI/DP, will that
> make a difference?
> For eDP which MMIO register need to be checked?
>
> Thanks
> Rao
>
> On Fri, Jul 30, 2021 at 2:47 PM Nico Huber <nico.h(a)gmx.de> wrote:
>
>> Hello Rao,
>>
>> On 30.07.21 13:53, Rao G wrote:
>> > trying to see the MMIO or VBIOS data when a external display device is
>> > plugged/unplugged with DP/HDMI interface, which MMIO register is set or
>> > cleared
>>
>> I think you are looking at the right register (last one below).
>>
>> >
>> > Any inputs are appreciated, some of the registers tried on Port B/Port C
>> > are given below. when Display is connected and when Display is not
>> > connected, both these instances
>> > return the same data. Looking for register/bit that sets/clears when
>> > external display is connected/disconnected
>> >
>> > printk(BIOS_DEBUG, "Intel Gfx BAR GTTMMADR\n");
>> > printk(BIOS_DEBUG, " DP_B %X\n", read32(bar+0x180000+0x64100));
>> > printk(BIOS_DEBUG, " DP_C %X\n", read32(bar+0x180000+0x64200));
>> > printk(BIOS_DEBUG, " HDMIC %X\n", read32(bar+0x180000+0x61160));
>> > printk(BIOS_DEBUG, " HDMIB %X\n", read32(bar+0x180000+0x61140));
>> > printk(BIOS_DEBUG, " Hotplug control %X\n",
>> read32(bar+0x180000+0x61164));
>> > printk(BIOS_DEBUG, " pipeA control %X\n", read32(bar+0x180000+0x61204));
>> > printk(BIOS_DEBUG, " pipeB control %X\n", read32(bar+0x180000+0x61304));
>> > printk(BIOS_DEBUG, " porthot plug stat %X\n",
>> read32(bar+0x180000+0x61114));
>>
>> According to the datasheet, the bits in this register should change but
>> only if enabled in PORT_HOTPLUG_EN (0x61110).
>>
>> Nico
>>
>> NB. There is also libgfxinit support under review [1]. In case you are
>> trying to do some native graphics init ;)
>>
>> [1] https://review.coreboot.org/q/topic:%2522baytrail-libgfxinit%2522
>>
>
$ cat defconfig
...
CONFIG_ADD_FSP_BINARIES=y
...
There is *no* "fspt.bin" file in this chromebook recovery bios file used as source.
$ make
...
src/soc/intel/apollolake/fspcar.c:3:10: fatal error: FsptUpd.h: No such file or directory
#include <FsptUpd.h>
^~~~~~~~~~~
compilation terminated.
make: *** [Makefile:379: build/bootblock/soc/intel/apollolake/fspcar.o] Error 1
What Makefile is that? There is no such line 379.
$ find -name FsptUpd.h
...
./3rdparty/fsp/ApolloLakeFspBinPkg/Include/FsptUpd.h
...
$ less src/soc/intel/alderlake/Kconfig
...
config FSP_HEADER_PATH
string "Location of FSP headers"
default "src/vendorcode/intel/fsp/fsp2_0/alderlake/"
$ less src/drivers/intel/fsp2_0/Kconfig
...
config FSP_T_FILE
string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD
depends on ADD_FSP_BINARIES
depends on FSP_CAR
default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD
help
The path and filename of the Intel FSP-T binary for this platform.
$ make nconfig
...
> Generic Drivers
...
(src/vendorcode/intel/fsp/fsp2_0/glk) Location of FSP headers
How did that get there? Not me...
$ ll src/vendorcode/intel/fsp/fsp2_0/glk
total 116
drwxr-x--- 2 james james 4096 Oct 29 2020 .
drwxr-x--- 9 james james 4096 Jun 14 19:04 ..
-rw-r----- 1 james james 45977 Oct 29 2020 FspmUpd.h
-rw-r----- 1 james james 57332 Oct 29 2020 FspsUpd.h
-rw-r----- 1 james james 1967 Oct 29 2020 FspUpd.h
Why is src/soc/intel/apollolake/fspcar.c being built here? It seems that no fspt.bin file is needed.
James
Hello,
Does anyone know if coreboot supports the ASRock H110M-DVS R3.0
mainboard? The documentation doesn't mention the revision number but the
links are all for the R2.0 board and I can only find R3.0 boards for sale.
Thanks,
Alex
Issue #314 has been reported by akjuxr3 akjuxr3.
----------------------------------------
Bug #314: Please disable 'administrator approval' on ticket.coreboot.orghttps://ticket.coreboot.org/issues/314
* Author: akjuxr3 akjuxr3
* Status: New
* Priority: Normal
* Assignee:
* Category: infrastructure
* Target version:
----------------------------------------
Please disable this 'administrator approval' on ticket.coreboot.org. It feels like discrimination. Before i have written the first word on ticket.coreboot.org i have to be approved by someone by hand without this person knowing anything from me. I had to wait several days for this approval. Its completely unclear what is been tracked. Have the IP-address used for registration been tracked? Have the used email-address been tracked? E-mail-address-discrimination is illegal in many countries and this is completely breaking the freedom of choice! Username? Choosing (user)names is up to the user and making decision based on what names are 'allowed' to enter a platform is the most racist thing possible.
Conclusion: This 'administrator approval' is sort of discrimination i have not seen for years on free projects! There is no data available at the registration process that could or should be used to decide who is allowed to report a bug in the coreboot project. Please disable this discrimination that is stopping people for days or even forever to report a coreboot issue.
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