coreboot October 2020

coreboot@coreboot.org
  • 37 participants
  • 32 discussions

A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538).
by dponamorev@gmail.com
4 weeks, 1 day

Reserve Device DRAM
by Bryan Angelo
8 months, 3 weeks

IRQ routing: how to do the mainboard_picr_data/_intr_data structures?
by Mike Banon
10 months

Coreboot Picasso FSP questions
by chen.kenyy@inventec.com
10 months, 1 week

Flashing coreboot and Intel Flash Descriptor Erase Issue
by Balaji Sivakumar
10 months, 2 weeks

Flashing coreboot and Intel Flash Descriptor Erase Issue
by Balaji Sivakumar
10 months, 2 weeks

AMD AGESA: Missing PCI bridge 00:15.2 on Asus F2A85-M PRO
by Paul Menzel
10 months, 2 weeks

Native RAM init
by Alif Ilhan
10 months, 3 weeks

amd_blobs submodule update issue when using git sup alias and how to fix it
by Felix Held
10 months, 4 weeks

Universal Payload Project
by Paul Menzel
11 months
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