coreboot February 2023

coreboot@coreboot.org

28 participants
51 discussions

[coreboot - Feature #433] (New) Unify TPM drivers in coreboot
by Michał Żygowski 24 Apr '24

24 Apr '24

Issue #433 has been reported by Michał Żygowski. ---------------------------------------- Feature #433: Unify TPM drivers in coreboot https://ticket.coreboot.org/issues/433 * Author: Michał Żygowski * Status: New * Priority: Normal * Target version: none * Start date: 2022-10-24 ---------------------------------------- Add an option to compile all drivers for TPM 1.2, 2.0 TIS and CRB. The motivation is to not build multiple coreboot ROMs for each possible TPM supported by the platform. The tasks would include: - runtime TPM detection (probing TPM_INTF_CAPABILITY and TPM_INTERFACE_ID) - rename the TPM driver functions, make them static and expose them as a driver structure, e.g. struct tpm_driver { void (*init)(void); int (*open)(void); int (*close)(void); int (*sendrecv)(const uint8_t *sendbuf, size_t send_size, uint8_t *recvbuf, size_t *recv_len); } - based on the detected TPM, hook the tpm_driver functions to provide the global TPM API: tis_open, tis_close, tis_init, tis_sendrecv. Some additional API to get vendor/device name could also be considered. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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QEMU x86 i440fx/piix4 build fails for >= 32MB ROMs - Assertion IS_HOST_SPACE_ADDRESS(host_space_address) failed
by Mike Banon 21 Feb '24

21 Feb '24

If I use a default config for i440fx/piix4, building a 16MB ROM works fine, but 32MB or 64MB doesn't work anymore: ... CC postcar/southbridge/intel/common/rtc.o LINK cbfs/fallback/postcar.debug OBJCOPY cbfs/fallback/romstage.elf CREATE build/mainboard/emulation/qemu-i440fx/cbfs-file.vqaXlP.out (from /home/my_custom_path_to/coreboot/.config) CC+STRIP src/lib/cbfs_master_header.c OBJCOPY cbfs/fallback/bootblock.elf OBJCOPY bootblock.raw.elf OBJCOPY bootblock.raw.bin Created CBFS (capacity = 33553892 bytes) BOOTBLOCK CBFS cbfs_master_header CBFS fallback/romstage cbfstool: /home/my_custom_path_to/coreboot/util/cbfstool/cbfstool.c:1145: cbfstool_convert_mkstage: Assertion `IS_HOST_SPACE_ADDRESS(host_space_address)' failed. make: *** [Makefile.inc:1116: build/coreboot.pre] Aborted -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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Coreboot chat room
by Arne 24 Apr '23

24 Apr '23

Hi, I just created a XMPP chat room about coreboot on our public XMPP server and I would be happy to make it to an official coreboot chatroom. The server is running since 2,5 years and will stay online for at least the next years. Maybe you like to join. So the main question is, can I write in the chatroom description "official coreboot chatroom"? I would also offer the coreboot delevopers a free XMPP chat account on https://ocean.monocles.de/apps/registration/ or https://ocean.monocles.eu/apps/registration/ Thanks for your project and best regards, Arne

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[GSOC 2023] Libpayload based memtest payload
by Joursoir 24 Mar '23

24 Mar '23

Hello everyone, I'm interested in participating in GSoC 2023. I would like to take part in the development of the coreboot, moreover I already have a bunch of commits in the flashrom. I find the "Libpayload based memtest payload" project interesting and have a few questions about it. 1) This project was added a few years ago, also coreboot payload of memtest based on memtest from 2019 (however, in 2022 memtest86+ v6 is released). So, maybe something has changed since that time and not reflected in the docs? I found such ticket: https://ticket.coreboot.org/issues/184 2) Do I understand correctly, that this payload should be memtest-fork with a difference that will be built on libpayload and a design that will allow multiple architectures to be added? 3) There are no mentors at the moment :( I would appreciate any feedback. -- Joursoir

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I need you help.
by email＠danwin1210.de 14 Mar '23

14 Mar '23

Hello. I would like to install Coreboot on my Lenovo x230, but I don't know how to do that. Please tell me how to do it. I have done a lot of research on my own, but I just can't figure it out. I am not a computer educated person. I don't have a rasberry pie. Do I need it? And what are skulls and heads, and what is the difference between them and coreboot?

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Coreboot - Intel NUC
by Sandro 09 Mar '23

09 Mar '23

Hello, I am contacting you to ask for your opinion. Weeks ago I bought an Intel NUC 11 N5105 (BNUC11ATKC40002 ). Since this board does not have any SATA port, I thought that I could use a SilverStone SST-ECS07 connected to the M.2 slot. When I try to set up the sata adapter connected to my main PC ( ASUS Mainboard ROG Crosshair VIII Hero WI-FI), I have no problems seeing the drives and their partitions.... As soon as I try the same but in the NUC, then the drives are not found......lots of problems booting, and most of the time I am not even able to enter the original Intel BIOS. I reached the Intel discord server and I was able to get some feedback from a NUC team member. You can see the communication with him at: https://discord.com/channels/554824368740630529/1076245516406493195 He was able to confirm the same issues on his side, that it is a problem with this specific model BIOS. And that on other models it works. Sadly, he also gave me no realistic hopes of receiving a BIOS fix from Intel. Since I cannot return the products back I am really sad to have just wasted lots of money on these things and not being able to use them. This is when I came in contact with Coreboot.... this gave me a small light of hope.... Since I really do not know anything about this subject, neither if this would work on this specific motherboard..... I decided to ask for some opinions from you. Hopefully you could give me some good news :) Thank you very much and I wish you a good day. Best regards, Sandro

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[coreboot - Refactoring #460] (New) Make mainboards using the variant concept
by Felix Singer 09 Mar '23

09 Mar '23

Issue #460 has been reported by Felix Singer. ---------------------------------------- Refactoring #460: Make mainboards using the variant concept https://ticket.coreboot.org/issues/460 * Author: Felix Singer * Status: New * Priority: Normal * Target version: none * Start date: 2023-02-14 ---------------------------------------- * asrock/ivybridge * asrock/b75pro3-m * asrock/h77pro4-m * asrock/haswell * asrock/b85m_pro4 * asrock/h81m-hds -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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How To Get Coreboot On Dev One
by Sergio 07 Mar '23

07 Mar '23

Hello, Is there a service that you provide or know of that can change my HP Dev one to coreboot? I am new to Linux so pardon my ignorance... Thank you in advance, Sergio

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Re: Deprecation of the Intel Quark SoC
by Łukasz Jeleń 02 Mar '23

02 Mar '23

Hi, My background is low level ARM and I want to get familiar with low level x86. I bought galileo v1 because it is cheap, small and handy x86 board. I have built coreboot code. It does not boot "out of the box". I had to add rmu.bin into coreboot.rom. With this logging on uart works. It seems SD/MMC controller also works. Now I'm struggling with: [INFO ] CBFS: Found 'fspm.bin' @0x31c40 size 0x2f000 in mcache @0x80004f84 [ERROR] CBFS ERROR: 'fspm.bin' allocation failure [EMERG] FSPM not available or failed to load! Regards, Łukasz

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Unable to get S3 resume to work on new port
by Kevin Keijzer 01 Mar '23

01 Mar '23

Hello, I'm working on a port for a new board; the ASRock B75M-ITX. A friend of mine did the initial porting [1] based on the existing B75 Pro3-M and autoport. I then took over the board as I intend to build an HTPC around it. Everything works fine, with the exception of resuming from S3. The board goes to sleep fine, but when I resume it, I'm greeted with the payload. (As this board does not have a serial port, I don't have an easy way to get logs, but everything looks like it just does a cold boot because DRAM is reset.) Then I found out that on the ASRock B75 Pro3-M port, which has been in coreboot since 2017, S3 resume also does not work [2]. It is suggested there to find the proper DRAM_RESET_GATE_GPIO, so I tried that. I've compiled and flashed roms with DRAM_RESET_GATE_GPIO set in Kconfig from 0 to 75, but in all cases the board just reboots instead of resumes. So I'm not too sure what to try next. Does anyone have any suggestions? [1] https://review.coreboot.org/c/coreboot/+/73097 [2] https://review.coreboot.org/c/coreboot/+/20227 -- With kind regards, Kevin Keijzer

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coreboot February 2023