coreboot February 2023

coreboot@coreboot.org

28 participants
52 discussions

Unable to get S3 resume to work on new port
by Kevin Keijzer 01 Mar '23

01 Mar '23

Hello, I'm working on a port for a new board; the ASRock B75M-ITX. A friend of mine did the initial porting [1] based on the existing B75 Pro3-M and autoport. I then took over the board as I intend to build an HTPC around it. Everything works fine, with the exception of resuming from S3. The board goes to sleep fine, but when I resume it, I'm greeted with the payload. (As this board does not have a serial port, I don't have an easy way to get logs, but everything looks like it just does a cold boot because DRAM is reset.) Then I found out that on the ASRock B75 Pro3-M port, which has been in coreboot since 2017, S3 resume also does not work [2]. It is suggested there to find the proper DRAM_RESET_GATE_GPIO, so I tried that. I've compiled and flashed roms with DRAM_RESET_GATE_GPIO set in Kconfig from 0 to 75, but in all cases the board just reboots instead of resumes. So I'm not too sure what to try next. Does anyone have any suggestions? [1] https://review.coreboot.org/c/coreboot/+/73097 [2] https://review.coreboot.org/c/coreboot/+/20227 -- With kind regards, Kevin Keijzer

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disable efficient-cores or performance-cores in Intel 12th gen processors
by baptx 27 Feb '23

27 Feb '23

Hello, For people who use the 12th generation of Intel Core processors, they may want to disable efficient-cores in the BIOS to improve performance ( https://www.reddit.com/r/intel/comments/thp7jh/disabling_the_efficiency_cor…), is it supported by coreboot or Dasharo? Some people may also want to disable performance-cores instead to save more battery ( https://www.reddit.com/r/overclocking/comments/x0xu1c/can_you_disable_perfo…), is it supported also? If some of these disabling option are not available, is there any plan to support them and is there a workaround currently? Thanks.

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Participation in GSoC '23
by Komal S 27 Feb '23

27 Feb '23

Hello All! This is Komal Sambhus here, a second year student from Mumbai, India. I am interested in participating in GSoC 2023 and working for coreboot. While going through the ideas list, the following projects interested me: -Provide Toolchain binaries -Fix POST code handling I have already built coreboot on my Ubuntu 20.04 system and have taken up this issue from the scanbuild index as mentioned in the Projects page. https://coreboot.org/scan-build/ASROCK_G41M_VS3_R2_0-scanbuild/ Are there any tasks relating to these ideas that I must complete or any additional skills that I must acquire before the application process begins? I have worked with embedded systems such as the BeagleBone Black, but am new to coreboot. Thanking You in advance, Komal

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[GSoC] Provide toolchain binaries
by Raysan Alawami 26 Feb '23

26 Feb '23

Hello everyone, I am Raysan Alawami and I am from Saudi Arabia. I plan on participating in GSoC and working on the first idea in the project idea list (see https://doc.coreboot.org/contributing/project_ideas.html#provide-toolchain-…). I have spent quite some time learning and writing small bash scripts, so I think that I can pull this one off. I have a question regarding your target platforms. Do you guys have any specific Linux distros in mind that you want to be supported in the packaging script? At the moment, I intend to support Ubuntu, and Windows or Mac OS for now. I am looking for popular Liunx distros that you guys think should be supported. Also, regarding the testing and verification of the packages, Can I get a tldr on how my scripts will be tested using QEMU/Docker? Or how you guys expect to be able to test them? I want to know a little more about the process so that I can figure out how much of it I can automate using the packaging script, and possibly another script meant for installing the packages on the target platforms for testing the packages. Finally, I have not had the chance to build build coreboot and boot it due to circumstances beyond my control, but I will be sure to post my serial output results before I apply. Thanks, Raysan

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COREBOOT and FSP CONFIGURATION for INTEL TIGERLAKE BOARD
by Renuka Pande 26 Feb '23

26 Feb '23

Hi, I am trying to configure coreboot and fsp for Intel Tigerlake Board. I am facing the following issues: While building coreboot, in the menuconfig command, in mainboard section, if the ON BOARD EC is selected as INTEL EC, when make command is given, it is giving "Makefile:215" error. If the ON BOARD EC is selected as Chrome EC, then only the make is successful. But it is displaying the following warning: "coreboot has been built without Intel Firmware Descriptor. . . . " The mainboard vendor and model are selected as Intel and Tigerlake UP3 RVP respectively. Can you please help in solving this issue? It would be of great help if you could explain how to build coreboot and fsp for Tigerlake Board. Thanking you in anticipation. Thanks and Regards, Renuka

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[GSoC] Fully support building coreboot with the Clang compiler
by Shivam Gupta 26 Feb '23

26 Feb '23

Hi Patrick, I would like to understand "Fully support building coreboot with the Clang compiler project" and apply for this project this year. Till now I completed the build process by referring to https://doc.coreboot.org/tutorial/part1.html and read about getting started documentation. Then I tried building coreboot with clang, it shows the following error messages at the end - https://gist.github.com/xgupta/48ecf80bdcced796307051f50737c45a What should be the first step to support clang compiler or can you please suggest some related issues to work on before the application period start? I do have llvm/clang contributing experience ( https://reviews.llvm.org/people/revisions/19845/) but very new to firmware and coreboot. Thanks, Shivam

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participation for GSoC '23
by Vihas Makwana 25 Feb '23

25 Feb '23

Hello Coreboot fellows, My name is Vihas Makwana, and I'm a software developer by profession. I came across coreboot while going through the "Organizations" for GSoC 2023. By going through the Project Ideas [1], following ideas caught my attention: -- Port payloads to ARM, AArch64 or RISC-V [2] -- Fix POST code handling [3] -- Fully support building coreboot with the Clang compiler [4] Out of these, I'm inclined towards [2] and [3], as I have a bit of experience with ARM Assembly and I also contribute to linux kernel (I have been quite here for sometime now). For the upcoming few days, I'm planning to go through coreboot's internals and architecture. Looking forward to this :) -- [1] https://doc.coreboot.org/contributing/project_ideas.html [2] https://doc.coreboot.org/contributing/project_ideas.html#port-payloads-to-a… [3] https://doc.coreboot.org/contributing/project_ideas.html#fix-post-code-hand… [4] https://doc.coreboot.org/contributing/project_ideas.html#fully-support-buil… -- Thanks, Vihas

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Need Help
by Reihane kamaly 23 Feb '23

23 Feb '23

Hello, My name is Seiede Reyhane Kamali and I am a Phd student. For my project, I need to run different configurations of coreboot. I read all the tutorials and tried them but I still can't figure out how to run different configurations. I will appreciate it if you can help me with this issue. Thanks in advance,Reyhane

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coreboot participates in GSoC '23
by Felix Singer 23 Feb '23

23 Feb '23

Hello coreboot fellows, coreboot has been accepted to Google Summer of Code 2023 [1]! We officially would like to encourage interested GSoC students to talk to us and discuss possible projects. This could be one of our existing ideas or a new idea you have on your mind. You can find a list of our community forums in our documentation [2]. We prepared a list of projects [3] and we started brainstorming on more project ideas [4]. No matter whether you want to participate as a GSoC student or mentor, if you are interested in anything or if you want to share an idea then please let us know. Don't hesitate talking to us :) So, what's next? Let's have a look at the timeline [5]: * Discussing possible projects (February 22th - March 19th) * Submitting your application (March 20th - April 4th) Please read our GSoC guide [6]. It explains our expectations and also points you to useful pages to get you started with coreboot. We highly recommend reading it. Are you interested in being a mentor? Great! Please also have a look at our GSoC guide [6] and contact Felix Singer. Would you like to support in a different way than being a mentor? Sure! You could help with code reviews, discussing projects and working them out (e.g. their scope and tasks) or just answering questions in our chat rooms and mailing list. We are looking forward to get in touch and discuss projects with you! Your GSoC admins, Felix, Martin and David --- [1] https://opensource.googleblog.com/2023/02/mentor-organizations-announced-fo… [2] https://doc.coreboot.org/community/forums.html [3] https://doc.coreboot.org/contributing/project_ideas.html [4] https://docs.google.com/document/d/1LU8CTITfqhJU_G_XHwvSkHAQQWed0_FLWPPoBfc… [5] https://developers.google.com/open-source/gsoc/timeline [6] https://doc.coreboot.org/contributing/gsoc.html

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[coreboot - Bug #448] Thinkpad T440P ACPI Battery Value Issues
by Karsten Schnier 23 Feb '23

23 Feb '23

Issue #448 has been updated by Karsten Schnier. Description updated Related links updated ---------------------------------------- Bug #448: Thinkpad T440P ACPI Battery Value Issues https://ticket.coreboot.org/issues/448#change-1438 * Author: Karsten Schnier * Status: New * Priority: Normal * Target version: none * Start date: 2023-01-11 * Affected versions: master * Related links: https://github.com/linrunner/TLP/issues/657 * Affected hardware: Thinkpad T440p * Affected OS: Artix / Arch Linux ---------------------------------------- Hello, I have been having some issues with TLP on my corebooted T440p. I am running artix linux with grub on top of coreboot (self compiled libreboot). I have had issues with the ACPI battery readings. Coreboot does not provide power readings, but instead only current readings. More details can be found in the TLP github issue: https://github.com/linrunner/TLP/issues/657#issuecomment-1293730559. This causes TLP to not recognize the thinkpad and go to default mode. Additional, it prevents recalibration of the battery even when the thinkpad battery driver is forced. Is this due to misconfiguration in the coreboot build or issues with coreboot itself? Finally, is there a method to change the /sys/class/dmi/id/product_version string? As of now coreboot only reports "1.0". This prevents some methods of board identification from working. Thank you! -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot February 2023