coreboot August 2016

coreboot@coreboot.org

53 participants
132 discussions

Lenovo T410 Coreboot
by A. Veek 14 Dec '18

14 Dec '18

2 1

Re: [coreboot] No VGA output on e350m1 after flashing. what to do?
by Reiner Luett 12 Sep '17

12 Sep '17

Hi! On 30.06.2013 19:28, Christian Weinz wrote: > Maybe I didn't include the VGA option in the make menuconfig process. > How can I solve this problem? You need to add the VGA Option ROM (VGA BIOS -> Add VGA BIOS image). I've extracted it from the UEFI, but you also could use these: http://www.coreboot.org/index.php?title=ASRock_E350M1&oldid=11114 at the end of the page or you also may be able to use the default AMD fam14 (Persimmon) vbios. You will need to agree to the click through: http://wwwd.amd.com/support/vbioslic.nsf/userverify?openform http://www.coreboot.org/AMD_DB-FT1_PERSIMMON It's a pity, that bios_extract didn't work for now. You could use the AMI Aptio EFI MMTool with wine: http://win-lite.de/benutzer/fernando/BIOS-Tools/AMI_Aptio_EFI_MMTool_v4.50.… You need to extract OntarioEFIVbios with PCI ID 1002,9802 as Option ROM. Regards, Reiner --

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ASUS KCMA-D8 workstation board port offer
by Timothy Pearson 20 Jan '17

20 Jan '17

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 All, After reviewing some of the comments on the ASUS KGPE-D16 being essentially too large of a system and too expensive for many people, and the fact that modern, blob-free systems are not really available in the mid-range arena, Raptor Engineering would like to offer to create a native initalization blob-free port for the ASUS KCMA-D8, which is essentially the KGPE-D16's ATX-compatible "little brother". We would be asking $15,000 for the port, including upstreaming to the master coreboot tree. We already have extensive experience with these Family 10h/15h boards, and would be able to create a port of similar quality to the existing KGPE-D16 source in terms of both code quality and overall functionality. If this is something you might be interested in please let me know. We are able to accept multiple payments from various sources for the same project (within limits), so if this is something your local Linux groups or similar might be interested in we should be able to keep the cost on any one individual or organization to a reasonable level. Thank you for your consideration, - -- Timothy Pearson Raptor Engineering +1 (415) 727-8645 (direct line) +1 (512) 690-0200 (switchboard) http://www.raptorengineeringinc.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iQEcBAEBAgAGBQJWQROpAAoJEK+E3vEXDOFbR2cH/3FTqGFH+cU/HVrBUPcoKjii h9OC7SGeXdyoLZvob/YayG+g47Yppkg2um4pAC7dmGl/OXtkGh13hlsrQ8BNiYcz g0kQUdNKYh9dmBC3YnlxU6a7psh473TdyuLILrl7/8WgI8DZnRtjy62Oo5k6XAKW jfYb/bGC8I3tArYrgQDmFxz2dOejuTZit56I+mbWNtvbuQov2BDmrPPMLRuEvG3M QHCAo/Pjaajzl4rmtrgu0GHcxHsgAnJcnrcPkFYeSDKt7QxSTNOB6NqhcnYdh1SY RiA5Z/3enuDs+XNhS+6qMeKOcrEuf+Ccs7sGsgq5tWm20JA+bBoByvrXhHqVUxU= =DKfR -----END PGP SIGNATURE-----

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Re: [coreboot] F2A-85M: Different VGA BIOS needed after CPU Upgrade?
by Daniel Kulesz 08 Jan '17

08 Jan '17

Hi John, > It sounds to me as though the PCI id's of the graphics card for the > upgraded CPU may be different (I could be totally wrong about that, so I > defer to others on the list if I'm barking up the wrong tree) and your > coreboot image may need to be updated accordingly. Of course, it could > also be the video BIOS that's the problem as you've suggested. Thank you for the hint. I inspected that, but the PCI-IDs actually look the same: 00:01.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Trinity [Radeon HD 7480D] [1002:9993] (A4-5300) and 00:01.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Richland [Radeon HD 8670D] (prog-if 00 [VGA controller]) (A10-6700) Looks like the VGA BIOS is really different: # diff vgabios_a4-5300.bin vgabios_a10_6700.bin Binary files vgabios_a4-5300.bin and vgabios_a10_6700.bin differ Guess I will have to to "update" the VGA BIOS then. Cheers, Daniel > > Hi Daniel, > > > Kind Regards, > > John. > > > On 28/06/16 09:24, Daniel Kulesz via coreboot wrote: > > Hi folks, > > > > I upgraded the CPU in my F2A-85M from a A4-5300 (Trinity) to a A10-6700 (Richland). The board had Coreboot installed before with the VGA BIOS extracted from the A4-5300. However, I did not get any video output when trying to boot after the upgrade, so I replaced the flash chip with a backup with the vendor BIOS that works. > > > > Is it likely that the A10-6700 needs a different VGA BIOS or does this this rather look like a different issue? I don't want to experiment too much because the BIOS chips are hardware-wise pretty fragile (even when using the extractor tool). > > > > Cheers, Daniel > >

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Linux 4.7 kernel payload with CoreBoot 4.4
by Trammell Hudson 12 Dec '16

12 Dec '16

The Linux 4.7 kernel payload crashes early in the boot process with CoreBoot 4.4. I traced it to these instructions that are finding a safe spot to decompress the rest of the kernel and patched around it with a hard coded location: diff -u --recursive /home/hudson/build/clean/linux-4.7/arch/x86/boot/compressed/head_64.S ./linux-4.7/arch/x86/boot/compressed/head_64.S --- /home/hudson/build/clean/linux-4.7/arch/x86/boot/compressed/head_64.S 2016-07-24 15:23:50.000000000 -0400 +++ ./linux-4.7/arch/x86/boot/compressed/head_64.S 2016-08-05 12:07:11.399854225 -0400 @@ -340,9 +357,15 @@ 1: /* Target address to relocate to for decompression */ +#if 0 movl BP_init_size(%rsi), %ebx subl $_end, %ebx addq %rbp, %rbx +#else + // coreboot does not populate the init_size boot param? + // fake it with a hard coded value + movl $0x97b000, %ebx +#endif /* Set up the stack */ leaq boot_stack_end(%rbx), %rsp It seems that the Linux kernel bzImage is supposed to set this value, rather than coreboot, so my comment is likely incorrect. Dumping linux-4.7/arch/x86/boot/header.o, it looks like init_siez is supposed to be 0xcf5000, so I wonder if %rsi is pointing to the wrong location. In 4.6.4 the computed address was hardcoded: movl $LOAD_PHYSICAL_ADDR, %ebx /* Target address to relocate to for decompression */ addl $z_extract_offset, %ebx 3e: bb 00 00 00 01 mov $0x1000000,%ebx 43: 81 c3 00 00 00 00 add $0x0,%ebx -- Trammell

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FOSDEM 2017
by Carl-Daniel Hailfinger 10 Dec '16

10 Dec '16

Hi, FOSDEM 2017 deadlines are soon. Do we want to have a full developer room, a talk or just a stand? Unfortunately I won't be able to attend, so someone else will have to be the formal contact for organizing our stand/devroom/talk. I will help with submitting proposals if this is desired by the person organizing our stand/devroom/... Who is willing to take care of our FOSDEM 2017 presence? https://fosdem.org/2017/news/2016-07-20-call-for-participation/ Deadlines: Developer Rooms: 9 September Main Track Talks: 10 October Stands: 31 October Lightning talks: 25 November Regards, Carl-Daniel

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t420 CPU Upgrade
by chub＠tuta.io 28 Aug '16

28 Aug '16

https://www.coreboot.org/Board:lenovo/t420 How stable is the i7-3720qm CPU Upgrade in the t420? You guys have it listed under the tested portion. I want to grab myself one, but would want to see if it's worth my time to upgrade the CPU, or just go with something more powerful.

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Re: [coreboot] t420 CPU Upgrade
by Zoran Stojsavljevic 28 Aug '16

28 Aug '16

> If you have any other reading material on the entire process I would love to see some more. I will be not able to comply to entire process, but here is a bit more... I guess, important below: (finding CPUID [CPUID 0x306A9 (SR0MM)] on the following www page): http://www.cpu-world.com/CPUs/Core_i7/Intel-Core%20i7-3720QM%20(BGA)%20Mobi… Then, please, read this, in order to determine the latest MCU (seems microcode-m12306a9_00000019): https://www.coreboot.org/pipermail/coreboot/2014-January/077013.html Good Luck! :-) Zoran On Sat, Aug 27, 2016 at 8:55 AM, <chub(a)tuta.io> wrote: > Awesome response to my question, thanks for breaking it all down. I'm not > as savvy as I'd like to be when doing these sort of modifications, so I'm > trying to wrap my head around all of this. > > Where would one go about finding this MCU to be entered at config. I > really hope I can learn to understand this more to be fully prepared to > tackle this job. > > If you have any other reading material on the entire process I would love > to see some more. It seems slightly too technical for me thus leading to > my hesitancy towards flashing this. > > -- > Securely sent with Tutanota. Claim your encrypted mailbox today! > https://tutanota.com > > 26. Aug 2016 22:57 by zoran.stojsavljevic(a)gmail.com: > > Let us try to understand what is i7-3720QM for itself? To find out, we'll > ask our good friend ark.intel.com: > http://ark.intel.com/products/64891/Intel-Core-i7-3720QM- > Processor-6M-Cache-up-to-3_60-GHz > > Important points: 4 (Quad) Core, 8 HTs, TDP 45W, DDR3/DDR3L 1333/1666MHz, > GFX base FREQ 650MHz, GFX Device ID 0x0166 . > > As I see from: https://www.coreboot.org/Board:lenovo/t420 > vBIOS (64KB) file pci8086,0166.rom does exist, so GFX wise Coreboot is > supported. I guess, IVB FSP does support as well i7-3720QM, with built-in > MRC algorithms for DDR3 (1.5V) and DDR3L (1.35V) 1333/1666MHz. > > The only one thing here to take care of is new MCU to be entered in > config: it is after all sku specific (new sku demands new MCU). > > And one more important point, economy wise, this sku costs around $350 > USD. If you do have these monies, IVB is 61% more PM efficient then its > counterpart SNB (currently present in yout T420 laptop). :-) > > Good Luck! > Zoran > > On Sat, Aug 27, 2016 at 6:08 AM, <chub(a)tuta.io> wrote: > >> https://www.coreboot.org/Board:lenovo/t420 >> >> How stable is the i7-3720qm CPU Upgrade in the t420? You guys have it >> listed under the tested portion. I want to grab myself one, but would want >> to see if it's worth my time to upgrade the CPU, or just go with something >> more powerful. >> >> >> >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> https://www.coreboot.org/mailman/listinfo/coreboot >> > >

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Re: [coreboot] Intel EMT/RMT tool with Coreboot
by Zoran Stojsavljevic 28 Aug '16

28 Aug '16

Hello Mayuri, I am not mistaken, RMT stands for Rank Margin Tool (related to DDR3/DDR4): http://www.freepatentsonline.com/7689879.pdf I am afraid, actually, the fastest/only way for you is to contact INTEL support. Good luck with that. You'll certainly need it!? ;-) Zoran On Sat, Aug 27, 2016 at 4:18 PM, Mayuri Tendulkar < mayuri.tendulkar(a)aricent.com> wrote: > Hi Team > > > > I am exploring usage of Intel memory related tools with coreboot for Intel > BayTrail processors. > > > > As per their guide, it works on Valley View BIOS with some MRC settings. > > > > Has anybody explored on this? > > > > Regards > > Mayuri > "DISCLAIMER: This message is proprietary to Aricent and is intended solely > for the use of the individual to whom it is addressed. It may contain > privileged or confidential information and should not be circulated or used > for any purpose other than for what it is intended. If you have received > this message in error, please notify the originator immediately. If you are > not the intended recipient, you are notified that you are strictly > prohibited from using, copying, altering, or disclosing the contents of > this message. Aricent accepts no responsibility for loss or damage arising > from the use of the information transmitted by this email including damage > from virus." > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Intel EMT/RMT tool with Coreboot
by Mayuri Tendulkar 27 Aug '16

27 Aug '16

Hi Team I am exploring usage of Intel memory related tools with coreboot for Intel BayTrail processors. As per their guide, it works on Valley View BIOS with some MRC settings. Has anybody explored on this? Regards Mayuri "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."

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coreboot August 2016