coreboot December 2021

coreboot@coreboot.org

45 participants
45 discussions

by bernd1-1＠web.de

Hi. I go through this tutorial: https://doc.coreboot.org/tutorial/part1.html I'm on Step 5 - Configure the build > Check your configuration (optional step): I entered $ make savedefconfig $ cat defconfig I have changed my mind. Now I'd like to install SeaBIOS instead of coreinfo. What do I need to do? How do I change it? Regards, Bernd

1 day, 1 hour

Git reports an interesting error message

by Gregg Levine

Hello! I just tried to synch my local tree with what's stored back there, and instead of watching it update I saw this one: fatal: unable to access 'https://review.coreboot.org/coreboot.git/': SSL certificate problem: certificate has expired Huh? Is everyone else aware of this? ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

3 days, 10 hours

My Asus P2B-LS is still having fun with coreboot/SeaBIOS/flashrom. Now I have questions.

by Keith Hui

Previously on the resource allocator discussion, I was about to test Arthur's fix for PARALLEL_MP when all my boards suddenly failed to come up. I still refuse to let this legend die, so I managed to get it going again, and look what it did for me in return. First, I plugged the flash chip with vendor firmware to rule out hardware failure. Came up just fine. Excellent! Swapped in my coreboot chip and tried to flash my copy of coreboot (which is still carrying PARALLEL_MP and the fix. It worked!). flashrom knows it has the 440BX chipset but can't seem to convince itself it will work. See the attached log. I have to calmly tell it "laptop=this is not a laptop" and then it works as usual. I don't remember ever having to do this before. Why? If I have a clue I can code up and submit a patch. Back to how it failed to boot in the first place. The hard disk booting stalled after SeaBIOS. Took me hours but eventually I found a line in my serial log that there has been a DMA timeout. Turning UDMA off in devicetree.cb and flash again made it boot again. So I would have to revert 576315e1 (aka CB:40961), but I'm hesitant because that seemed like the reasonable thing to do and it should have worked. So I'm also unsure why it didn't. Thanks Keith

1 week, 6 days

"Private" changes on Gerrit are now disabled and removed

by Patrick Georgi

Hi everybody, it came to my attention that changes marked "private" on Gerrit are hidden in the UI but easily accessible through gitiles and with "git fetch". I don't think it matters for most cases, but since we advertised it as being accessible for the owner and individual reviewers, I didn't want to keep things exposed, especially not after there's an announcement that such access is possible (as through this email). Therefore I: - disabled the "private" CL feature in the Gerrit UI, so you can't mark changes as private - created per-account git bundles[1] of their private CLs. Since I don't want to spam a few hundred users with stuff they might not care about, this is a pull transaction: if you want them, reach out to me. - removed the private commits and references from the coreboot.git repo. You might still see the changes in the UI but that's due to its aggressive caching: The UI actually honors the private flag, so that's not a concern and all other means of accessing commits access the repo and will fail on these now-gone commits. https://review.coreboot.org/c/coreboot/+/59229 also proposes updating the docs to remove mentions of the "private change" feature. As an alternative we could also decide to re-enable the feature but with documentation pointing out that there are ways for motivated unauthenticated users to access these commits, which makes them more of a structuring feature (keep things out of sight until they're ready). In that case I could also reinstate the commits I deleted from the repo. Thoughts? Best regards, Patrick [1] https://git-scm.com/docs/git-bundle

2 weeks, 5 days

Re: My Asus P2B-LS is still having fun with coreboot/SeaBIOS/flashrom. Now I have questions.

by Branden Waldner

Hi > I have to calmly tell it "laptop=this is not a laptop" and then it works as usual. I don't remember > ever having to do this before. Why? If I have a clue I can code up and submit a patch. If I recall correctly both my p2b and p2-99 boards do that while running vendor firmware, though I don't recall ever seeing it while running coreboot (which I just checked to verify it still doesn't show up). > Back to how it failed to boot in the first place. The hard disk booting stalled after SeaBIOS. Took > me hours but eventually I found a line in my serial log that there has been a DMA timeout. > Turning UDMA off in devicetree.cb and flash again made it boot again. So I would have to revert > 576315e1 (aka CB:40961), but I'm hesitant because that seemed like the reasonable thing to do > and it should have worked. So I'm also unsure why it didn't. I've had the occasional issue with my p2-99 in the past, but I've always got it booting again after reseating chips (flash/memory/cpu card). I guess I should be making sure to have the serial link set up more often, I normally only use it when I have a known bad version of coreboot flashed. I actually have the cable connected between the two boards right now, which seems to work decently for testing. Branden

3 weeks, 1 day

[coreboot - Feature #334] (New) Tianocore payload support ft232h and or oxford cards for debug serial output

by coreboot＠fe80.eu

Issue #334 has been reported by xinhua wang. ---------------------------------------- Feature #334: Tianocore payload support ft232h and or oxford cards for debug serial output https://ticket.coreboot.org/issues/334 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Tianocore payload support ft232h and or oxford cards for debug serial output -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 weeks, 2 days

[coreboot - Bug #333] (New) Tianocore - Virtualbox (manuall install to suppo or https://github.com/AdnanHodzic/displaylink-debian install causes /sbin/update-secureboot-policy --enroll-key to be run with no ability to cancel unless renamed the /sbin/update-secureboot-policy file

by coreboot＠fe80.eu

Issue #333 has been reported by xinhua wang. ---------------------------------------- Bug #333: Tianocore - Virtualbox (manuall install to suppo or https://github.com/AdnanHodzic/displaylink-debian install causes /sbin/update-secureboot-policy --enroll-key to be run with no ability to cancel unless renamed the /sbin/update-secureboot-policy file https://ticket.coreboot.org/issues/333 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Tianocore - Virtualbox (manuall install to support windows 11) or https://github.com/AdnanHodzic/displaylink-debian install causes /sbin/update-secureboot-policy --enroll-key to be run with no ability to cancel unless renamed the /sbin/update-secureboot-policy file -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 weeks, 2 days

[coreboot - Bug #332] (New) I selected payload Tianocore Upstream (not UEFIPayload) but its still using MrChromebox UEFIPayload files?

by coreboot＠fe80.eu

Issue #332 has been reported by xinhua wang. ---------------------------------------- Bug #332: I selected payload Tianocore Upstream (not UEFIPayload) but its still using MrChromebox UEFIPayload files? https://ticket.coreboot.org/issues/332 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- make V=1 -d Cloning Tianocore from Git Reaping winning child 0x559abd8daf20 PID 142498 git clone --branch uefipayload_202107 https://github.com/mrchromebox/edk2 /mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore; \ cd /mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore; \ git remote add upstream https://github.com/tianocore/edk2 Live child 0x559abd8daf20 (/mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore) PID 142499 Cloning into '/mnt/cb-trying-upstream/coreboot/payloads/external any ideas, thx -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 weeks, 2 days

[coreboot - Feature #331] (New) Add detail wiki how to use oxford serial card?

by coreboot＠fe80.eu

Issue #331 has been reported by xinhua wang. ---------------------------------------- Feature #331: Add detail wiki how to use oxford serial card? https://ticket.coreboot.org/issues/331 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Add detail wiki how to use oxford serial card? For example, early pci settings.. how to determine what mmio to use, etc for the green one, I only see [ 0.364949] 0000:01:00.0: ttyS4 at MMIO 0x83401000 (irq = 16, base_baud = 4000000) is a 16C950/954 [ 0.365132] 0000:01:00.0: ttyS5 at MMIO 0x83401200 (irq = 16, base_baud = 4000000) is a 16C950/954 then I am lost at what to do, I tried plug in 0x83401000, and select 0 index but it does not do anything I tested the ttyS4 with another computer and my cable, adapter works. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 weeks, 2 days

[coreboot - Feature #330] (New) Add support for the red oxford debug card 1415:c120

by coreboot＠fe80.eu

Issue #330 has been reported by xinhua wang. ---------------------------------------- Feature #330: Add support for the red oxford debug card 1415:c120 https://ticket.coreboot.org/issues/330 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Add support for the red oxford debug card 1415:c120 The green one is correct pciid (same as wiki, but the red one is different), there was no mention was this and got tricked and lost money buying the wrong one. (unless there is some way to add support) thx -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

3 weeks, 2 days

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coreboot December 2021