coreboot December 2021

coreboot@coreboot.org

45 participants
46 discussions

[coreboot - Feature #334] (New) Tianocore payload support ft232h and or oxford cards for debug serial output
by coreboot＠fe80.eu 31 Dec '21

31 Dec '21

Issue #334 has been reported by xinhua wang. ---------------------------------------- Feature #334: Tianocore payload support ft232h and or oxford cards for debug serial output https://ticket.coreboot.org/issues/334 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Tianocore payload support ft232h and or oxford cards for debug serial output -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #333] (New) Tianocore - Virtualbox (manuall install to suppo or https://github.com/AdnanHodzic/displaylink-debian install causes /sbin/update-secureboot-policy --enroll-key to be run with no ability to cancel unless renamed the /sbin/update-secureboot-policy file
by coreboot＠fe80.eu 31 Dec '21

31 Dec '21

Issue #333 has been reported by xinhua wang. ---------------------------------------- Bug #333: Tianocore - Virtualbox (manuall install to suppo or https://github.com/AdnanHodzic/displaylink-debian install causes /sbin/update-secureboot-policy --enroll-key to be run with no ability to cancel unless renamed the /sbin/update-secureboot-policy file https://ticket.coreboot.org/issues/333 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Tianocore - Virtualbox (manuall install to support windows 11) or https://github.com/AdnanHodzic/displaylink-debian install causes /sbin/update-secureboot-policy --enroll-key to be run with no ability to cancel unless renamed the /sbin/update-secureboot-policy file -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #332] (New) I selected payload Tianocore Upstream (not UEFIPayload) but its still using MrChromebox UEFIPayload files?
by coreboot＠fe80.eu 31 Dec '21

31 Dec '21

Issue #332 has been reported by xinhua wang. ---------------------------------------- Bug #332: I selected payload Tianocore Upstream (not UEFIPayload) but its still using MrChromebox UEFIPayload files? https://ticket.coreboot.org/issues/332 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- make V=1 -d Cloning Tianocore from Git Reaping winning child 0x559abd8daf20 PID 142498 git clone --branch uefipayload_202107 https://github.com/mrchromebox/edk2 /mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore; \ cd /mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore; \ git remote add upstream https://github.com/tianocore/edk2 Live child 0x559abd8daf20 (/mnt/cb-trying-upstream/coreboot/payloads/external/tianocore/tianocore) PID 142499 Cloning into '/mnt/cb-trying-upstream/coreboot/payloads/external any ideas, thx -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #331] (New) Add detail wiki how to use oxford serial card?
by coreboot＠fe80.eu 31 Dec '21

31 Dec '21

Issue #331 has been reported by xinhua wang. ---------------------------------------- Feature #331: Add detail wiki how to use oxford serial card? https://ticket.coreboot.org/issues/331 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Add detail wiki how to use oxford serial card? For example, early pci settings.. how to determine what mmio to use, etc for the green one, I only see [ 0.364949] 0000:01:00.0: ttyS4 at MMIO 0x83401000 (irq = 16, base_baud = 4000000) is a 16C950/954 [ 0.365132] 0000:01:00.0: ttyS5 at MMIO 0x83401200 (irq = 16, base_baud = 4000000) is a 16C950/954 then I am lost at what to do, I tried plug in 0x83401000, and select 0 index but it does not do anything I tested the ttyS4 with another computer and my cable, adapter works. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #330] (New) Add support for the red oxford debug card 1415:c120
by coreboot＠fe80.eu 31 Dec '21

31 Dec '21

Issue #330 has been reported by xinhua wang. ---------------------------------------- Feature #330: Add support for the red oxford debug card 1415:c120 https://ticket.coreboot.org/issues/330 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Add support for the red oxford debug card 1415:c120 The green one is correct pciid (same as wiki, but the red one is different), there was no mention was this and got tricked and lost money buying the wrong one. (unless there is some way to add support) thx -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #329] (New) Add progress feature so it doesn't look "hung" when running make on slow internet connections
by coreboot＠fe80.eu 31 Dec '21

31 Dec '21

Issue #329 has been reported by xinhua wang. ---------------------------------------- Feature #329: Add progress feature so it doesn't look "hung" when running make on slow internet connections https://ticket.coreboot.org/issues/329 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- edit the makefile.inc so the submodules chromeec, etc will show something (I had to use V=1 and -d to show it), forgetthis:=$(if $(GIT),$(shell git submodule update --progress --init $(quiet_errors))) forgetthis:=$(if $(GIT),$(shell git submodule update --init --progress )) (add --progress) when i ran make it just hang before for hours after I found its download at 60kb/s thats why no idea how to integrate that or make it as default, as you would need V=1 and -d too ? -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Feature #328] (New) Add RAM disk/filesystem in SPI flash for tianocore
by coreboot＠fe80.eu 30 Dec '21

30 Dec '21

Issue #328 has been reported by xinhua wang. ---------------------------------------- Feature #328: Add RAM disk/filesystem in SPI flash for tianocore https://ticket.coreboot.org/issues/328 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- Add RAM disk/filesystem in SPI flash for tianocore -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #327] (New) MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR
by coreboot＠fe80.eu 30 Dec '21

30 Dec '21

Issue #327 has been reported by xinhua wang. ---------------------------------------- Bug #327: MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR https://ticket.coreboot.org/issues/327 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- https://review.coreboot.org/c/coreboot/+/27711/7/src/drivers/intel/gma/acpi… this line .. OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) the 0x2000 will cause BSOD ACPI_BIOS_ERROR when booting installer, os, etc When set to 0x1000 windows UEFI tianocore mode boots fine -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #326] (New) raminit fails after 58188 review.coreboot.org
by coreboot＠fe80.eu 30 Dec '21

30 Dec '21

Issue #326 has been reported by xinhua wang. ---------------------------------------- Bug #326: raminit fails after 58188 review.coreboot.org https://ticket.coreboot.org/issues/326 * Author: xinhua wang * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- For this addition.. https://review.coreboot.org/c/coreboot/+/58188 What is the cause of this? ft232h log with raminit debug enabled https://pastebin.com/kHC0bXLs Read MPR training failed: 1, 2, 0 raminit failed ---- If I remove the patches in here (top of message) it boots fine ft232h log with raminit debug enabled https://pastebin.com/e8xhet1V Any ideas? Thx If I need more debugging options please tell me how to enable it, thx -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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How should we handle different endianness in cbtable?
by Igor Bagnucki 23 Dec '21

23 Dec '21

Dear coreboot community, as a part of coreboot port for Talos II POWER9 architecture, we are porting the cbmem tool. [1] This platform can switch between the big-endian and the little-endian. coreboot operates in big-endian but in theory it could also operate in little-endian, and the OS can also operate in both - little-endian and big-endian. This creates a situation where cbmem tries to read cbtable in different endianness than the cbtable was created. Therefore, cbmem needs to convert the endianness, and it needs to differentiate if the conversion is required or not. There are several ways we could differentiate if it is required to convert endianness or not. What would be the best approach to this problem? 1. Save endianness information in the cbtable header. For example, the signature on the big-endian coreboot could be “OIBL” instead “LBIO”. This solution would be very portable as the other tools looking for the cbtable but not expecting the big-endian format would simply not find the table instead of trying to read it and crashing. However, this change would need to be introduced in multiple places in coreboot as the signature is hardcoded in multiple where it was needed. 2. Add preprocessor checks to enable endianness conversion only on defined platforms. It would be easy to implement, but if the BIOS and the OS can have different endianness, then it could break for cbtable written in little-endian mode. 3. Recognize the correct endianness by checking some property of cbtable header. For example, header size property value could be checked if it reads as 0x18 or 0x18000000, but this solution requires very little changes but feels hacky and susceptible to changes in cbtable header format. 4. Add command-line option to cbmem so the user can choose what endianness should be used. I’m not sure about this solution, because it pushes the responsibility to recognize endianness to the user. [1] https://github.com/Dasharo/coreboot/pull/62 -- Igor Bagnucki Embedded Firmware Developer https://3mdeb.com | @3mdeb_com

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coreboot December 2021