coreboot December 2021

coreboot@coreboot.org

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46 discussions

[PATCH] CHROMIUM: i2c: Add device property for probing
by Paul Menzel 22 Dec '21

22 Dec '21

From: Furquan Shaikh <furquan(a)google.com> Dear Linux folks, Google Chromebooks are often built with devices sourced from different vendors. These need to be probed. To deal with this, the firmware – in this case coreboot – tags such optional devices accordingly – I think this is commit fbf2c79b (drivers/i2c/generic: Add config for marking device as probed) – and Chromium OS’ Linux kernel has the patch at hand applied to act accordingly. Right after the merge, Dmitry created a revert, which was actively discussed for two days but wasn’t applied. That means, millions of devices shipped with such a firmware and Linux kernel. To support these devices with upstream Linux kernel, is there an alternative to applying the patch to the Linux kernel, and to support the shipped devices? Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/16742/ [2]: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/… --------------- 8< -------------------------- >8 --------------- Add a new device property to indicate if an I2C device should be probed before being added. If this property is present and set then the I2C core layer will use i2c_new_probed_device() instead of i2c_new_device(). This can be used to provide devices in ACPI or DT that may not be present on the board. For example, multiple trackpad vendors can be supported on a single board with a unified firmware image this way by having their device address be probed before being added. This property is styled after the PCI Host Bridge probe property (bindings/pci/host-generic-pci.txt:linuxk,pci-probe-only) and is a linux specific directive to alter device probing. BUG=b:110013532 TEST=tested on soraka with 4.14 kernel: 1) add "linux,probed=1" device property to the touchscreen ACPI device on soraka and ensure that the device is probed before being added. tested on yorp with 4.14 kernel: 1) I2C devices without the "linux,probed=1" device property are still functional. Original-change-Id: I9cf689f7b75ef445c1f0e9f7ec143fa695eb398e Original-signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-reviewed-on: https://chromium-review.googlesource.com/388767 Original-reviewed-by: Benson Leung <bleung(a)chromium.org> Change-Id: I54015fe102f2834f6a094d9e650c166a0cc0583b Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/1100544 Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-by: Justin TerAvest <teravest(a)chromium.org> Conflicts: drivers/i2c/i2c-core-of.c [rebase419(groeck): Context conflicts] Signed-off-by: Guenter Roeck <groeck(a)chromium.org> [rebase510(groeck): Context conflicts] Signed-off-by: Guenter Roeck <groeck(a)chromium.org> Change-Id: Id10adae00b381e62813fd6b8ce7c6c50f140c31b --- Documentation/devicetree/bindings/i2c/i2c.txt | 5 +++++ drivers/i2c/i2c-core-acpi.c | 12 +++++++++++- drivers/i2c/i2c-core-of.c | 10 +++++++++- 3 files changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt index b864916e087f..4921ee57f4c1 100644 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c.txt @@ -133,6 +133,11 @@ wants to support one of the below features, it should adapt these bindings. - wakeup-source device can be used as a wakeup source. +- linux,probed + If this property is present, then the I2C device will be + probed before being added using i2c_new_scanned_device, else + linux will instantiate the I2C device normally. + Binding may contain optional "interrupts" property, describing interrupts used by the device. I2C core will assign "irq" interrupt (or the very first interrupt if not using interrupt names) as primary interrupt for the slave. diff --git a/drivers/i2c/i2c-core-acpi.c b/drivers/i2c/i2c-core-acpi.c index 92c1cc07ed46..c970d99e4438 100644 --- a/drivers/i2c/i2c-core-acpi.c +++ b/drivers/i2c/i2c-core-acpi.c @@ -254,10 +254,20 @@ static void i2c_acpi_register_device(struct i2c_adapter *adapter, struct acpi_device *adev, struct i2c_board_info *info) { + struct i2c_client *client; + adev->power.flags.ignore_parent = true; acpi_device_set_enumerated(adev); - if (IS_ERR(i2c_new_client_device(adapter, info))) + if (!acpi_dev_get_property(adev, "linux,probed", ACPI_TYPE_ANY, NULL)) { + unsigned short addrs[] = { info->addr, I2C_CLIENT_END }; + + client = i2c_new_scanned_device(adapter, info, addrs, NULL); + } else { + client = i2c_new_client_device(adapter, info); + } + + if (IS_ERR(client)) adev->power.flags.ignore_parent = false; } diff --git a/drivers/i2c/i2c-core-of.c b/drivers/i2c/i2c-core-of.c index 3ed74aa4b44b..fd375ce38a9e 100644 --- a/drivers/i2c/i2c-core-of.c +++ b/drivers/i2c/i2c-core-of.c @@ -75,7 +75,15 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap, if (ret) return ERR_PTR(ret); - client = i2c_new_client_device(adap, &info); + /* Allow device property to enable probing before init */ + if (of_get_property(node, "linux,probed", NULL)) { + unsigned short addrs[] = { info.addr, I2C_CLIENT_END }; + + client = i2c_new_scanned_device(adap, &info, addrs, NULL); + } else { + client = i2c_new_client_device(adap, &info); + } + if (IS_ERR(client)) dev_err(&adap->dev, "of_i2c: Failure registering %pOF\n", node); -- 2.34.1

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Sublime Text Syntax Highlighting
by Raul Rangel 18 Dec '21

18 Dec '21

Hey all, If you use Sublime Text, I wanted to point out the [Coreboot Syntax](https://packagecontrol.io/packages/Coreboot%20syntax) package. It includes Device Tree support and I recently added ASL support. Let me know if you encounter any strange highlighting issues. Raul

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Gigabyte H61M-DS2 support?
by ratatouille gamer 17 Dec '21

17 Dec '21

Hello is just a question. Is possible to H61M-DS2 sandybridge future support The OEM BIOS is a shit don't have UEFI support i just want a Tianocore or linuxboot use in H61M-DS2 but i'm not a programmer i am just a Noob with Intelectual problems low QI

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Intel or AMD NTB - Non Transparent Bridge support and hardware
by Jeremy Jackson 14 Dec '21

14 Dec '21

Hi, Just seeing some nice 2 node HA cluster systems on the market, that have HTB seemingly just by connecting a PCIe port directly between AMD Epyc CPUs. It occurred to me that 2 commodity motherboards could be connected by crossover SlimSAS, OcuLink, MiniSAS HD, or any of the SFF-nnnn cables used for PCIe. I think support of the BIOS would be required to configure the PCIe port into NTB mode. Has anyone run across this while working on Coreboot? It seems faster and cheaper than Infiniband cards... and more available given pervasive supply chain issues these days. Regards, Jeremy

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spkmodem output
by Keith Emery 10 Dec '21

10 Dec '21

I had a bit of a brainwave regarding what might be happening with this spkmodem output. I was hoping to collect peoples thoughts in regards to weather I might be at least possibly on the right track. When I enable spkmodem in the coreboot config, I get output from the PC speaker. But spkmodem-recv interprets the tones as consistent gibberish. The output is consistent with a mismatch in the baud rates, but there appears no apparent way to select anything different in the spkmodem-recv software. If the CPU is running coreboot as fast as possible while receiving those instructions from a relatively slow SPI bus. Is it possible that I've somehow overclocked the SPI bus, leading to a mismatch in the baud rates?

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EFI menu using UART console
by Rao G 10 Dec '21

10 Dec '21

Hi All, Good morning! EFI Payload in coreboot has enabled MdeModulePkg/Universal/SerialDxe/SerialDxe.inf in .dsc/.fdf file There is a *SerialRead *function in this DXE Driver, am trying to access F2 from UART Console but this does not work, How to enable this feature? Who is invoking SerialRead from the platform? Thanks for your time! Best Regards Ranga

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Intel released first documentation on the PSE for Elkhart Lake SoC
by Zeh, Werner 09 Dec '21

09 Dec '21

Dear coreboot community. As you know we are currently in discussion with Intel to get the PSE and its documentation on the Elkhart Lake SoC publicly available. Intel have now released some docs in this regard which can be accessed freely (see [1] and [2]). Feel free to use them as your use case requests. Though it might be not fully complete it is a good starting point to dig into and get a wider understanding of the PSE and its internals. There are other referenced documents mentioned in these two which are available, too. Just change the referenced doc number in the link and you will get the other docs as well. Have fun Werner [1] https://cdrdv2.intel.com/v1/dl/getContent/636112 [2] https://cdrdv2.intel.com/v1/dl/getContent/636723

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FOSDEM'22 Open Source Firmware, BMC and Bootloader devroom CFP
by Mike Banon 07 Dec '21

07 Dec '21

Dear friends, on behalf of 3mdeb I invite you to participate in "FOSDEM'22 Open Source Firmware, BMC and Bootloader" online devroom! It will take place on 5th February (Saturday), however - the talk proposals should be submitted before 24th December UTC, so it is time to act. The devroom will focus on various topics related to the open source firmware, BMC and bootloaders including security issues. It will help to get together all interested people in one place, present and discuss current developments and issues haunting the community. Additionally, it will foster awareness among attendees about pre-OS topics. So, if you'd like to have your moment of fame - by sharing your deep knowledge with fellow firmware hackers from all over the world - please follow the instructions at [1] page below: it contains the detailed submission instructions and also gives a list of the possible topics [1] https://lists.fosdem.org/pipermail/fosdem/2021q4/003320.html -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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Does PCI driver code belong in coreboot (ARM)?
by Paul Menzel 07 Dec '21

07 Dec '21

Dear coreboot folks, Currently, work is underway to add PCI support to ARM platforms [1][2]. If I remember correctly, coreboot’s goal to only do minimal hardware initialization originally meant, that the payload/OS does PCI initialization. Only due to shortcomings in the Linux kernel many years ago, PCI initialization was added to coreboot. (Nowadays, the Linux kernel is likely fixed.) For ARM there are dedicated drivers in the Linux kernel [3]. Should PCI support be added to coreboot for ARM, so it’s aligned with x86? Should coreboot stay minimal on ARM, for example PCI code adds 100 ms delay [4]? PCI drivers then have to be added to the payloads, which could be a minimal Linux kernel, so that booting from drives connected over PCI is possible? Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/57861 "Documentation/RFC: Generalize PCI support in coreboot" [2]: https://review.coreboot.org/c/coreboot/+/56791 "soc/mediatek: Add PCIe support" [3]: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/dri… [4]: https://review.coreboot.org/c/coreboot/+/56791/6/src/soc/mediatek/common/pc…

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GA-B75M-D3H Black Screen
by Moisés Simón 06 Dec '21

06 Dec '21

Hi, Im trying to install coreboot on ga-b75m-d3h. I always get a black screen (no beeping). I have included vgabios.bin, tried VGA text mod , libgfxinit... Still no screen output. I have installed coreboot on thinkpads before. Not suere what the problem here is. I have tried flashing internally and externally. This is my config file: https://pastebin.com/paeAERzt Regards - - - Sent from a phone, apologies for poor formatting.

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coreboot December 2021