coreboot December 2021

coreboot@coreboot.org

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46 discussions

[ANNOUNCE] SeaBIOS 1.15.0
by Kevin O'Connor 03 Dec '21

03 Dec '21

The 1.15.0 version of SeaBIOS has now been released. For more information on the release, please see: http://seabios.org/Releases New in this release: * Improved support for USB devices with multiple interfaces. * Support for USB XHCI devices using direct MMIO access (instead of PCI). * NVMe improvements. * Increased "f-segment" RAM allocations for BIOS tables. * Several bug fixes and code cleanups. For information on obtaining SeaBIOS, please see: http://seabios.org/Download ===== git shortlog -n rel-1.14.0..rel-1.15.0 ===== Gerd Hoffmann (9): output: add support for uppercase hex numbers dsdt: add support for pnp ids as strings usb: add boot prio support for mmio host adapters usb/xhci: split xhci setup into generic and pci parts usb/xhci: add support for mmio host adapters (via acpi). usb boot: add xhci mmio example nvme: improve namespace allocation nvme: drive desc should not include the newline Increase BUILD_MIN_BIOSTABLE for large roms Alexander Graf (4): nvme: Record maximum allowed request size nvme: Allow to set PRP2 nvme: Pass large I/O requests as PRP lists nvme: Split requests by maximum allowed size Stefan Berger (4): tcgbios: Fix details in log entries Add implementations for sha256, sha384, and sha512 tcgbios: Use The proper sha function for each PCR bank tcgbios: Disable platform hierarchy in case of failure Volker Rümelin (2): stacks: call check_irqs() in run_thread() stacks: call check_irqs() after switch_next() Alex Martens via SeaBIOS (1): nvme: fix missing newline on sq full print Daniel P. Berrangé (1): smbios: avoid integer overflow when adding SMBIOS type 0 table David Woodhouse (1): nvme: Clean up nvme_cmd_readwrite() Kevin O'Connor (1): docs: Note v1.15.0 release Matt DeVillier (1): usb.c: Fix devices using non-primary interface descriptor Mike Banon (1): Support booting USB drives with a write protect switch enabled Sergei Trofimovich (1): vgasrc: ignore .node.gnu.property (binutils-2.36 support) Stefan Ott via SeaBIOS (1): usb-hid: Increase MAX_KBD_EVENT weitaowang-oc(a)zhaoxin.com (1): USB:Fix xHCI initail fail by using longer reset and CNR clear timeout value

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How to enable lspci device heci/intel me to show up?
by J c 02 Dec '21

02 Dec '21

How to enable lspci device heci/intel me to show up? I have the me jumper set to normal Fdo jumper removed On retail bios i see the mei device but not on coreboot On intelmetool both shows mei device but why is it not initalized on the pci bus? I need it for enable graphics acceleration on hd4000 for osx. Thx

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How to enable lspci device heci/intel me to show up?
by J c 02 Dec '21

02 Dec '21

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Gopdriver into coreboot
by Rao G 02 Dec '21

02 Dec '21

Hi All, Trying to figure out how the GOP driver is enabled/added in the coreboot tree. IntelGraphicsPeim.efi IntelGopDriver.efi Above 2 drivers part of FSP? Intel is providing DisCon tool to configure VBT, this tool is a replacement for BMP which is EOL Thanks for your time! Best Regards Ranga

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[coreboot - Support #324] (New) samsung r580
by coreboot＠fe80.eu 01 Dec '21

01 Dec '21

Issue #324 has been reported by kostya kuznetsov. ---------------------------------------- Support #324: samsung r580 https://ticket.coreboot.org/issues/324 * Author: kostya kuznetsov * Status: New * Priority: Normal * Assignee: * Category: * Target version: ---------------------------------------- model: np r580 js09 cpu: Intel(R) Core(TM) i3 CPU M 330 north bridge : Intel SLGZS (BD82HM55) gpu: GeForce GT 330M mother board: Bremen-M rev:1.3(100321)-8 lspci -tvnn -+-[0000:3f]-+-00.0 Intel Corporation Core Processor QuickPath Architecture Generic Non-core Registers [8086:2c62] | +-00.1 Intel Corporation Core Processor QuickPath Architecture System Address Decoder [8086:2d01] | +-02.0 Intel Corporation Core Processor QPI Link 0 [8086:2d10] | +-02.1 Intel Corporation 1st Generation Core i3/5/7 Processor QPI Physical 0 [8086:2d11] | +-02.2 Intel Corporation 1st Generation Core i3/5/7 Processor Reserved [8086:2d12] | \-02.3 Intel Corporation 1st Generation Core i3/5/7 Processor Reserved [8086:2d13] \-[0000:00]-+-00.0 Intel Corporation Core Processor DRAM Controller [8086:0044] +-01.0-[02]--+-00.0 NVIDIA Corporation GT216M [GeForce GT 330M] [10de:0a29] | \-00.1 NVIDIA Corporation GT216 HDMI Audio Controller [10de:0be2] +-1a.0 Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b3c] +-1b.0 Intel Corporation 5 Series/3400 Series Chipset High Definition Audio [8086:3b56] +-1c.0-[03-04]----00.0 Qualcomm Atheros AR9285 Wireless Network Adapter (PCI-Express) [168c:002b] +-1c.2-[05-06]-- +-1c.3-[07-08]----00.0 Marvell Technology Group Ltd. Yukon Optima 88E8059 [PCIe Gigabit Ethernet Controller with AVB] [11ab:4381] +-1d.0 Intel Corporation 5 Series/3400 Series Chipset USB2 Enhanced Host Controller [8086:3b34] +-1e.0-[09]-- +-1f.0 Intel Corporation HM55 Chipset LPC Interface Controller [8086:3b09] +-1f.2 Intel Corporation 5 Series/3400 Series Chipset 4 port SATA AHCI Controller [8086:3b29] \-1f.3 Intel Corporation 5 Series/3400 Series Chipset SMBus Controller [8086:3b30] flashrom -p internal -V flashrom v1.2 on Linux 5.15.5-zen1-1-zen (x86_64) flashrom is free software, get the source code at https://flashrom.org flashrom was built with libpci 3.6.4, GCC 9.3.0, little endian Command line (3 args): flashrom -p internal -V Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns). Initializing internal programmer /sys/class/mtd/mtd0 does not exist No coreboot table found. Using Internal DMI decoder. DMI string chassis-type: "Laptop" Laptop detected via DMI. DMI string system-manufacturer: "SAMSUNG ELECTRONICS CO., LTD." DMI string system-product-name: "R580/R590 " DMI string system-version: "Not Applicable" DMI string baseboard-manufacturer: "SAMSUNG ELECTRONICS CO., LTD." DMI string baseboard-product-name: "R580/R590 " DMI string baseboard-version: "Not Applicable" Found chipset "Intel HM55" with PCI ID 8086:3b09. Enabling flash write... Root Complex Register Block address = 0xfed1c000 Error accessing ICH RCRB, 0x4000 bytes at 0x00000000fed1c000 /dev/mem mmap failed: Operation not permitted FAILED! FATAL ERROR! Error: Programmer initialization failed. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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i440bx PARALLEL_MP testing WAS: Re: Suggestion for deprecation: LEGACY_SMP_INIT & RESOURCE_ALLOCATOR_V3
by Branden Waldner 01 Dec '21

01 Dec '21

On 11/30/21, Keith Hui <buurin(a)gmail.com> wrote: > I suffered an unexpected exception after applying the patch train. > Serial log at the end of this email. I probably could leave out > bootblock/romstage/postcar, but it's here for completeness. Next: > bisect. I had a similar result testing on my P2B. I'm working on recovering it and I was planning on trying a build with log level spew on the P2-99 since it is easy for me to recover with the way I have it setup right now. Branden Waldner

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coreboot December 2021