coreboot August 2016

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132 discussions

ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 25 Aug '16

25 Aug '16

The ASUS KGPE-D16 fails verification for branch master as of commit 70385968cea517ed20dc3f3f665d92096acc768c The following tests failed: BOOT_FAILURE Commits since last successful test: 7038596 soc/intel/skylake: Bump up bootblock size to 48K a6914d2 soc/intel/skylake: align chromium Chrome OS config See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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Can boards wake up from S3/4/5 by specific keystroke
by Zheng Bao 25 Aug '16

25 Aug '16

All, Some customers says ThinkCentre M6600q (lenovo) has the feature of wake up the system by pressing ALT-P on USB keyboard. I am wondering how it is implemented? Is it done in chipset, BIOS, or a special keyboard? Or when the BIOS wakeup, it reads the keystroke to see if it matches the pre-defined key. Does it sounds reasonable? Zheng

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Re: [coreboot] Test hardware initialization in emulator
by Zoran Stojsavljevic 24 Aug '16

24 Aug '16

> Now I wanted to learn the "hard" part, mainly RAM initialization and PCI enumeration. Hard part, indeed, I should say. RAM init = MRC (INTEL IP), PCIe enumeration, also IP, also part of FSP (there are open source alternatives to PCIe enumeration). To really learn these, you should either have/obtain source code, either to do reverse engineering. None of these are easy. Maybe, upon getting HW, you should a bit explore algorithms inside FSP using JTAG debugger (solely for the learning experiences/purposes). Just a thought. Zoran On Wed, Aug 24, 2016 at 11:31 AM, Rishav Ambasta <kooolrishav(a)gmail.com> wrote: > I am exploring Coreboot. > I had bought a Minnowboard, which will take some time to arrive. > Meanwhile I wanted to carry out the learning on an emulator. > I had compiled a ROM for QEMU and it ran successfully. I even tried with > different payloads (which I hear is the easy part of the boot process) > Now I wanted to learn the "hard" part, mainly RAM initialization and PCI > enumeration. > > I had generated a ROM using the Minnowboard FSP, but I was not able to > boot QEMU using it. > > Need suggestions on how can one, trace or at-least log the steps in the > boot-block stage, ROM stage and RAM stage of Minnowboard on an Emulator. > > Regards, > *Rishav Ambasta* > > *Save Plants, Save Life ...* > > > -- > coreboot mailing list: coreboot(a)coreboot.org > https://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] coreboot image signature
by John Lewis 24 Aug '16

24 Aug '16

Zoran, I'm a bit confused as to where you are coming from with this - you can search for ASCII/hex strings using something as light as hexedit. No need to install a more full-blown hex editor especially. I'm not a fan of using sledgehammers to crack nuts. John. On 24/08/16 09:54, Zoran Stojsavljevic wrote: > > Please see https://www.coreboot.org/CBFS > > Hello John, > > From the pointer:*/_magic_/*/_is a 32 bit number that identifies the > ROM as a CBFS type. *The magic number is 0x4F524243, which is 'ORBC' > in ASCII*._/ > > I did install on my F24 VM (in order to verify this info) wxHexEditor > source code package (wxHexEditor-v0.23-src.tar.bz2): > http://www.wxhexeditor.org/home.php > > Please, you can all try it, there are some environmental > catches/packages and CCP flags (CCPFLAGS) to be added, but it is > fairly manageable. Here is how GUI looks like: > > Inline image 1 > > Interesting enough, wxHexAuthor Erdem (U. Altinyurt) is a jobless > computer engineer, born and living since 1981,in Istanbul, Turkey. Why > Erdem is jobless, that is the (crucial) question??? ;-) > > Zoran > > On Fri, Aug 19, 2016 at 11:49 AM, John Lewis <jlewis(a)johnlewis.ie > <mailto:jlewis@johnlewis.ie>> wrote: > > Hi Benoit, > > Please see https://www.coreboot.org/CBFS > > Kind Regards, > > John. > > > On 19/08/16 10:43, Benoit SANSONI wrote: >> Hi all, >> >> I would like to know if it is possible, via a signature or a >> magic number, in the coreboot.rom file to recognize that it is a >> "coreboot" file. >> I did not find anything in the Makefile.inc. >> >> Thanks in advance >> >> > > > -- > coreboot mailing list: coreboot(a)coreboot.org > <mailto:coreboot@coreboot.org> > https://www.coreboot.org/mailman/listinfo/coreboot > <https://www.coreboot.org/mailman/listinfo/coreboot> > >

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Test hardware initialization in emulator
by Rishav Ambasta 24 Aug '16

24 Aug '16

I am exploring Coreboot. I had bought a Minnowboard, which will take some time to arrive. Meanwhile I wanted to carry out the learning on an emulator. I had compiled a ROM for QEMU and it ran successfully. I even tried with different payloads (which I hear is the easy part of the boot process) Now I wanted to learn the "hard" part, mainly RAM initialization and PCI enumeration. I had generated a ROM using the Minnowboard FSP, but I was not able to boot QEMU using it. Need suggestions on how can one, trace or at-least log the steps in the boot-block stage, ROM stage and RAM stage of Minnowboard on an Emulator. Regards, *Rishav Ambasta* *Save Plants, Save Life ...*

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Re: [coreboot] coreboot image signature
by John Lewis 24 Aug '16

24 Aug '16

Hi Benoit, Please see https://www.coreboot.org/CBFS Kind Regards, John. On 19/08/16 10:43, Benoit SANSONI wrote: > Hi all, > > I would like to know if it is possible, via a signature or a magic > number, in the coreboot.rom file to recognize that it is a "coreboot" > file. > I did not find anything in the Makefile.inc. > > Thanks in advance > >

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New on blogs.coreboot.org: [GSoC] Better RISC-V support, wrap-up
by WordPress 23 Aug '16

23 Aug '16

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ASUS KGPE-D16 Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 23 Aug '16

23 Aug '16

The ASUS KGPE-D16 fails verification for branch master as of commit d9ff75f2cb944d3536f7a502c1c7519843c06618 The following tests failed: BOOT_FAILURE Commits since last successful test: See attached log for details This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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ASUS KFSN4-DRE (K8) Automated Test Failure [master]
by Raptor Engineering Automated Coreboot Test Stand 23 Aug '16

23 Aug '16

The ASUS KFSN4-DRE (K8) fails verification for branch master as of commit 64444268e2eecf235af9dd77b5f6cee8c0365fc5 The following tests failed: BOOT_FAILURE Commits since last successful test: 6444426 mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cb 5a85951 3rdparty/blobs: Update to get AGESA binary for pcengines/apu2 97e0a65 intel/skylake: Do not halt in poweroff if in SMM 63e424c google/chromeec: Ensure data is ready before reading it 3828e55 intel/apollolake: Do not halt in poweroff if in SMM <10 commits skipped> 7b2c781 soc/intel/apollolake: use SPI flash boot_device_rw() for ealy stages 6f11559 drivers/spi: provide optional implementation of boot_device_rw() 5180dd2 drivers/spi: include SPI flash modules for all stages c0a823c drivers/spi: ensure SPI flash is boot device for coreboot tables 2e03fbc util/lint: Add a tool to verify a single newline at the end of files See attached log for details This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE (K8) test stand Want to test on your own equipment? Check out https://www.raptorengineering.com/content/REACTS/intro.html Raptor Engineering also offers coreboot consulting services! Please visit https://www.raptorengineering.com for more information Please contact Timothy Pearson at Raptor Engineering <tpearson(a)raptorengineering.com> regarding any issues stemming from this notification

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New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 23 Aug '16

23 Aug '16

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 52 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1361875: Memory - illegal accesses (BUFFER_SIZE_WARNING) /src/soc/intel/apollolake/meminit.c: 311 in save_lpddr4_dimm_info() ________________________________________________________________________________________________________ *** CID 1361875: Memory - illegal accesses (BUFFER_SIZE_WARNING) /src/soc/intel/apollolake/meminit.c: 311 in save_lpddr4_dimm_info() 305 dest_dimm->dimm_size = src_dimm->SizeInMb; 306 dest_dimm->ddr_type = memory_info_hob->MemoryType; 307 dest_dimm->ddr_frequency = 308 memory_info_hob->MemoryFrequencyInMHz; 309 dest_dimm->channel_num = channel_info->ChannelId; 310 dest_dimm->dimm_num = src_dimm->DimmId; >>> CID 1361875: Memory - illegal accesses (BUFFER_SIZE_WARNING) >>> Calling strncpy with a maximum size argument of 19 bytes on destination array "dest_dimm->module_part_number" of size 19 bytes might leave the destination string unterminated. 311 strncpy((char *)dest_dimm->module_part_number, 312 lp4cfg->skus[mem_sku].part_num, 313 sizeof(dest_dimm->module_part_number)); 314 315 switch (memory_info_hob->DataWidth) { 316 case 8: ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0… To manage Coverity Scan email notifications for "coreboot(a)coreboot.org", click https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

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coreboot August 2016