coreboot February 2013

coreboot@coreboot.org

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790 discussions

New patch to review for coreboot: c5c03ce Intel e7505: provide get_top_of_ram
by Kyösti Mälkki 27 Feb '13

27 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2550 -gerrit commit c5c03ce1dfb950e17b08bc923b7598be6668b5db Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 3 11:36:44 2012 +0300 Intel e7505: provide get_top_of_ram This is required to enable EARLY_CBMEM_INIT. Change-Id: I6d8caf382aa48eded81c1e94bbbcd3975ea88a1a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/e7505/raminit.c | 6 ++++++ src/northbridge/intel/e7505/raminit.h | 1 + 2 files changed, 7 insertions(+) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 2f558f5..9fba602 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1889,6 +1889,12 @@ void e7505_mch_init(const struct mem_controller *memctrl) sdram_enable(memctrl); } +unsigned long get_top_of_ram(void) +{ + u32 tolm = (pci_read_config16(MCHDEV, TOLM) & ~0x7ff) << 16; + return (unsigned long) tolm; +} + /** * Scrub and reset error counts for ECC dimms. * diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 8eb4990..f9ba796 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -20,6 +20,7 @@ void e7505_mch_scrub_ecc(unsigned long ret_addr); void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void); +unsigned long get_top_of_ram(void); /* Mainboard exports this. */ int spd_read_byte(unsigned device, unsigned address);

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New patch to review for coreboot: bbd83e4 Fix collecting timestamps
by Kyösti Mälkki 27 Feb '13

27 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2549 -gerrit commit bbd83e4260c873cf6d9a1765915ad93e0c2922c7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 28 00:32:25 2013 +0200 Fix collecting timestamps A board without HAVE_ACPI_RESUME did not build with COLLECT_TIMESTAMPS enabled. Change-Id: I9c8b575d445ac566a2ec533d73080bcccc3dfbca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 8ff0a44..bb75b8d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -45,7 +45,7 @@ romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c romstage-$(CONFIG_USBDEBUG) += usbdebug.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c cbmem.c romstage-y += compute_ip_checksum.c romstage-y += memmove.c

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New patch to review for coreboot: e1918f8 Drop SRC_ROOT from mainboard Makefile.incs
by Stefan Reinauer 27 Feb '13

27 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2548 -gerrit commit e1918f89f2dac97a2b4582d1f5d25a5b7bbaa5ae Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Feb 28 00:12:18 2013 +0100 Drop SRC_ROOT from mainboard Makefile.incs It's not used, and not needed. Change-Id: Ifca92f3606ac58fc26e09676488c3add5d84ae79 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/mainboard/emulation/qemu-armv7/Makefile.inc | 2 -- src/mainboard/google/butterfly/Makefile.inc | 2 -- src/mainboard/google/link/Makefile.inc | 4 +--- src/mainboard/google/parrot/Makefile.inc | 2 -- src/mainboard/google/snow/Makefile.inc | 6 ------ 5 files changed, 1 insertion(+), 15 deletions(-) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index cea3b15..80b392b 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -26,5 +26,3 @@ ramstage-y += timer.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c ramstage-y += uart.c - -SRC_ROOT = $(src)/mainboard/emulation/qemu-armv7a diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc index 9e753fb..5b4e74c 100644 --- a/src/mainboard/google/butterfly/Makefile.inc +++ b/src/mainboard/google/butterfly/Makefile.inc @@ -23,5 +23,3 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c - -SRC_ROOT = $(src)/mainboard/google/butterfly diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc index 3f04a30..a769d95 100644 --- a/src/mainboard/google/link/Makefile.inc +++ b/src/mainboard/google/link/Makefile.inc @@ -27,14 +27,12 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c SPD_BIN = $(obj)/spd.bin -SRC_ROOT = $(src)/mainboard/google/link - # Order of names in SPD_SOURCES is important! SPD_SOURCES = elpida_4Gb_1600_x16 SPD_SOURCES += samsung_4Gb_1600_1.35v_x16 SPD_SOURCES += micron_4Gb_1600_1.35v_x16 -SPD_DEPS := $(foreach f, $(SPD_SOURCES), $(SRC_ROOT)/$(f).spd.hex) +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) # Include spd rom data $(SPD_BIN): $(SPD_DEPS) diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index f2de43e..5ad5454 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -21,5 +21,3 @@ ramstage-y += ec.c romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c - -SRC_ROOT = $(src)/mainboard/google/parrot diff --git a/src/mainboard/google/snow/Makefile.inc b/src/mainboard/google/snow/Makefile.inc index 668e3b7..46e366f 100644 --- a/src/mainboard/google/snow/Makefile.inc +++ b/src/mainboard/google/snow/Makefile.inc @@ -24,9 +24,3 @@ romstage-y += romstage.c # ramstage-y += ec.c ramstage-y += ramstage.c ramstage-y += chromeos.c - -# romstage-$(CONFIG_CHROMEOS) += chromeos.c - -# FIXME: we should do something similar to x86 platforms for Snow SPDs - -SRC_ROOT = $(src)/mainboard/google/snow

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Patch merged into coreboot/master: 8f4647a ARMv7: drop special handling for stages.c
by gerrit＠coreboot.org 27 Feb '13

27 Feb '13

the following patch was just integrated into master: commit 8f4647a24bf19a96531af9905b23ae8a2fc2675a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 21:00:01 2013 +0100 ARMv7: drop special handling for stages.c This is a leftover from when we were debugging this code. Let's make it easier to understand. Change-Id: Ia3d0ab1504ff9dd9634d5f393d3c59fe1e43a0c0 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2543 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Feb 27 21:19:39 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 28 00:00:50 2013, giving +2 See http://review.coreboot.org/2543 for details. -gerrit

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Patch merged into coreboot/master: fd611f9 Drop CONFIG_WRITE_HIGH_TABLES
by gerrit＠coreboot.org 27 Feb '13

27 Feb '13

the following patch was just integrated into master: commit fd611f9c2c8c751069c6cd1634a3e3e523ff098b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 23:45:20 2013 +0100 Drop CONFIG_WRITE_HIGH_TABLES It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2547 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Feb 27 23:57:48 2013, giving +1 Reviewed-By: Ronald G. Minnich <rminnich(a)gmail.com> at Thu Feb 28 00:00:30 2013, giving +2 See http://review.coreboot.org/2547 for details. -gerrit

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New patch to review for coreboot: 6580c9c Drop CONFIG_WRITE_HIGH_TABLES
by Stefan Reinauer 27 Feb '13

27 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2547 -gerrit commit 6580c9c8eea8afeb1acf43aa332d3113b0b74a88 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 23:45:20 2013 +0100 Drop CONFIG_WRITE_HIGH_TABLES It's been on for all boards per default since several years now and the old code path probably doesn't even work anymore. Let's just have one consistent way of doing things. Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/Kconfig | 4 ---- src/arch/armv7/boot/coreboot_table.c | 2 -- src/arch/x86/boot/coreboot_table.c | 15 --------------- src/cpu/amd/agesa/s3_resume.c | 2 -- src/lib/hardwaremain.c | 6 ------ src/mainboard/emulation/qemu-x86/northbridge.c | 5 ----- src/mainboard/google/snow/ramstage.c | 5 ----- src/northbridge/amd/agesa/family10/northbridge.c | 4 ---- src/northbridge/amd/agesa/family12/northbridge.c | 4 ---- src/northbridge/amd/agesa/family14/northbridge.c | 4 ---- src/northbridge/amd/agesa/family15/northbridge.c | 4 ---- src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ---- src/northbridge/amd/amdfam10/northbridge.c | 7 +------ src/northbridge/amd/amdk8/northbridge.c | 6 ------ src/northbridge/amd/gx1/northbridge.c | 4 ---- src/northbridge/amd/gx2/northbridge.c | 4 ---- src/northbridge/amd/lx/northbridge.c | 4 ---- src/northbridge/intel/e7501/northbridge.c | 5 ----- src/northbridge/intel/e7505/northbridge.c | 5 ----- src/northbridge/intel/e7520/northbridge.c | 11 ++--------- src/northbridge/intel/e7525/northbridge.c | 10 +--------- src/northbridge/intel/gm45/northbridge.c | 2 -- src/northbridge/intel/i3100/northbridge.c | 6 +----- src/northbridge/intel/i440bx/northbridge.c | 7 +------ src/northbridge/intel/i440lx/northbridge.c | 10 +--------- src/northbridge/intel/i5000/northbridge.c | 5 ----- src/northbridge/intel/i82810/northbridge.c | 8 ++------ src/northbridge/intel/i82830/northbridge.c | 6 +----- src/northbridge/intel/i855/northbridge.c | 6 +----- src/northbridge/intel/i945/northbridge.c | 7 +------ src/northbridge/intel/sandybridge/northbridge.c | 2 -- src/northbridge/intel/sch/northbridge.c | 7 +------ src/northbridge/rdc/r8610/northbridge.c | 5 ----- src/northbridge/via/cn400/northbridge.c | 7 +------ src/northbridge/via/cn700/northbridge.c | 7 +------ src/northbridge/via/cx700/northbridge.c | 5 ----- src/northbridge/via/vt8601/northbridge.c | 7 +------ src/northbridge/via/vt8623/northbridge.c | 7 +------ 38 files changed, 17 insertions(+), 202 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 2dc251d..4dbc23e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -396,10 +396,6 @@ config MAX_PIRQ_LINKS menu "System tables" -config WRITE_HIGH_TABLES - bool "Write 'high' tables to avoid being overwritten in F segment" - default y - config MULTIBOOT bool "Generate Multiboot tables (for GRUB2)" default y diff --git a/src/arch/armv7/boot/coreboot_table.c b/src/arch/armv7/boot/coreboot_table.c index 55610ac..47aad36 100644 --- a/src/arch/armv7/boot/coreboot_table.c +++ b/src/arch/armv7/boot/coreboot_table.c @@ -625,12 +625,10 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, table_start, table_end - table_start); -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, table_start, table_end - table_start); -#endif /* Add reserved regions */ add_lb_reserved(mem); diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 04fba47..e456e1e 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -329,7 +329,6 @@ static void lb_strings(struct lb_header *header) } -#if CONFIG_WRITE_HIGH_TABLES static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { struct lb_record *rec; @@ -341,7 +340,6 @@ static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header forward->forward = (uint64_t)(unsigned long)next_header; return forward; } -#endif static void lb_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size) @@ -600,7 +598,6 @@ unsigned long write_coreboot_table( struct lb_header *head; struct lb_memory *mem; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n", low_table_end); head = lb_table_init(low_table_end); @@ -614,16 +611,6 @@ unsigned long write_coreboot_table( head = lb_table_init(rom_table_end); rom_table_end = (unsigned long)head; printk(BIOS_DEBUG, "rom_table_end = 0x%08lx\n", rom_table_end); -#else - if(low_table_end > (0x1000 - sizeof(struct lb_header))) { /* after 4K */ - /* We need to put lbtable on to [0xf0000,0x100000) */ - head = lb_table_init(rom_table_end); - rom_table_end = (unsigned long)head; - } else { - head = lb_table_init(low_table_end); - low_table_end = (unsigned long)head; - } -#endif printk(BIOS_DEBUG, "Adjust low_table_end from 0x%08lx to ", low_table_end); low_table_end += 0xfff; // 4K aligned @@ -663,12 +650,10 @@ unsigned long write_coreboot_table( lb_add_memory_range(mem, LB_MEM_TABLE, rom_table_start, rom_table_end-rom_table_start); -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "Adding high table area\n"); // should this be LB_MEM_ACPI? lb_add_memory_range(mem, LB_MEM_TABLE, high_tables_base, high_tables_size); -#endif /* Add reserved regions */ add_lb_reserved(mem); diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index ee9d7c9..ada4d3c 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -24,9 +24,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif #include <device/device.h> #include <device/pci.h> #ifndef __PRE_RAM__ diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 85c05f5..d2213d2 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -39,9 +39,7 @@ it with the version available from LANL. #if CONFIG_HAVE_ACPI_RESUME #include <arch/acpi.h> #endif -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif #include <coverage.h> #include <timestamp.h> @@ -113,12 +111,10 @@ void hardwaremain(int boot_complete) timestamp_stash(TS_DEVICE_DONE); -#if CONFIG_WRITE_HIGH_TABLES cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif -#endif timestamp_sync(); #if CONFIG_HAVE_ACPI_RESUME @@ -128,10 +124,8 @@ void hardwaremain(int boot_complete) timestamp_add_now(TS_CBMEM_POST); -#if CONFIG_WRITE_HIGH_TABLES if (cbmem_post_handling) cbmem_post_handling(); -#endif timestamp_add_now(TS_WRITE_TABLES); diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index 3e7fbb9..d785beb 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -9,10 +9,7 @@ #include <string.h> #include <delay.h> #include <smbios.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif #include "memory.c" @@ -38,11 +35,9 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif assign_resources(dev->link_list); } diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index a3e9236..5970357 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -18,10 +18,7 @@ */ #include <console/console.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif void hardwaremain(int boot_complete); void main(void) @@ -29,13 +26,11 @@ void main(void) console_init(); printk(BIOS_INFO, "hello from ramstage\n"); -#if CONFIG_WRITE_HIGH_TABLES /* place at top of physical memory */ high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; high_tables_base = CONFIG_SYS_SDRAM_BASE + ((CONFIG_DRAM_SIZE_MB << 20UL) * CONFIG_NR_DRAM_BANKS) - CONFIG_COREBOOT_TABLES_SIZE; -#endif hardwaremain(0); } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index cd21d9c..e0c3255 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -1036,7 +1036,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -1048,7 +1047,6 @@ static void amdfam10_domain_set_resources(device_t dev) printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)(high_tables_size / 1024), high_tables_base); } -#endif } basek = mmio_basek; } @@ -1063,7 +1061,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { @@ -1075,7 +1072,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1467fdc..2ef5563 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -722,7 +722,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, idx, basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -735,7 +734,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); (u32)(high_tables_size / 1024), high_tables_base); } -#endif } basek = mmio_basek; @@ -751,7 +749,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); ram_resource(dev, (idx | 0), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); if (high_tables_base==0) { @@ -764,7 +761,6 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n"); #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index c1685ec..3d46ad7 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -716,7 +716,6 @@ static void domain_set_resources(device_t dev) pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base == 0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -728,7 +727,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)(high_tables_size / 1024), high_tables_base); } -#endif } basek = mmio_basek; @@ -743,7 +741,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | 0), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0, mmio_basek, basek, limitk); @@ -757,7 +754,6 @@ static void domain_set_resources(device_t dev) #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek); printk(BIOS_DEBUG, " adsr - high_tables_size = %llx.\n", diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5cd76a3..36e1499 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -807,7 +807,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -819,7 +818,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)(high_tables_size / 1024), high_tables_base); } -#endif } basek = mmio_basek; } @@ -834,7 +832,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { @@ -846,7 +843,6 @@ static void domain_set_resources(device_t dev) #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 144dde7..90f8345 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -793,7 +793,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -805,7 +804,6 @@ static void domain_set_resources(device_t dev) printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", (u32)(high_tables_size / 1024), high_tables_base); } -#endif } basek = mmio_basek; } @@ -820,7 +818,6 @@ static void domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { @@ -832,7 +829,6 @@ static void domain_set_resources(device_t dev) #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index aabbae2..875f462 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -842,9 +842,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id) #endif -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void setup_uma_memory(void) { @@ -1039,7 +1037,7 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES + if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -1051,7 +1049,6 @@ static void amdfam10_domain_set_resources(device_t dev) printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_MEMORY_SIZE / 1024, high_tables_base); } -#endif } #if !CONFIG_AMDMCT #if CONFIG_HW_MEM_HOLE_SIZEK != 0 @@ -1077,7 +1074,6 @@ static void amdfam10_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { @@ -1089,7 +1085,6 @@ static void amdfam10_domain_set_resources(device_t dev) #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index 5ed7762..5c1d97a 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -817,9 +817,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id) } #endif -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void setup_uma_memory(void) { @@ -1044,7 +1042,6 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if CONFIG_WRITE_HIGH_TABLES if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA @@ -1056,7 +1053,6 @@ static void amdk8_domain_set_resources(device_t dev) printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_MEMORY_SIZE / 1024, high_tables_base); } -#endif } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) @@ -1079,7 +1075,6 @@ static void amdk8_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if CONFIG_WRITE_HIGH_TABLES printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (high_tables_base==0) { @@ -1091,7 +1086,6 @@ static void amdk8_domain_set_resources(device_t dev) #endif high_tables_size = HIGH_MEMORY_SIZE; } -#endif } #if CONFIG_GFXUMA diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index e483263..4547b8d 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -64,9 +64,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, }; -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -111,11 +109,9 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 9952374..62de416 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -271,9 +271,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_NS_GX2, }; -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -292,11 +290,9 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */ -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 3a2eb46..5909d13 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -370,9 +370,7 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = PCI_DEVICE_ID_AMD_LXBRIDGE, }; -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -391,11 +389,9 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tomk - 768); // Systop - 0xc0000 -> KB -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index ab382fa..d30c9df 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -6,10 +6,7 @@ #include <cpu/cpu.h> #include <stdlib.h> #include <string.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -87,11 +84,9 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 1b6f40d..6ee371f 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -7,10 +7,7 @@ #include <stdlib.h> #include <string.h> #include "e7505.h" - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -88,11 +85,9 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index 03aad3e..96fcc35 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -7,18 +7,14 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include "chip.h" #include "northbridge.h" #include "e7520.h" - static unsigned int max_bus; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -26,9 +22,8 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = find_pci_tolm(dev->link_list); -#if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); -#endif + /* FIXME Me temporary hack */ if(pci_tolm > 0xe0000000) pci_tolm = 0xe0000000; @@ -107,11 +102,9 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 12ee971..83757bd 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -7,18 +7,14 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include "chip.h" #include "northbridge.h" #include "e7525.h" - static unsigned int max_bus; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -26,9 +22,7 @@ static void pci_domain_set_resources(device_t dev) pci_tolm = find_pci_tolm(dev->link_list); -#if 1 printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm); -#endif /* FIXME Me temporary hack */ if(pci_tolm > 0xe0000000) pci_tolm = 0xe0000000; @@ -107,11 +101,9 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 9c1e96d..c7aa3fa 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -166,11 +166,9 @@ static void mch_domain_read_resources(device_t dev) pcie_config_size >> 10, IORESOURCE_RESERVE); } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk << 10) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 87c5e75..3e62ae4 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -29,6 +29,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include "chip.h" #include "i3100.h" @@ -36,9 +37,6 @@ static u32 max_bus; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -128,11 +126,9 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 488275d..2ab62a9 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> #include "northbridge.h" @@ -31,10 +32,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7190, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void i440bx_domain_set_resources(device_t dev) { device_t mc_dev; @@ -70,11 +67,9 @@ static void i440bx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i440lx/northbridge.c b/src/northbridge/intel/i440lx/northbridge.c index bbb621e..623071f 100644 --- a/src/northbridge/intel/i440lx/northbridge.c +++ b/src/northbridge/intel/i440lx/northbridge.c @@ -27,6 +27,7 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include <pc80/keyboard.h> #include "northbridge.h" @@ -37,9 +38,6 @@ * Maciej */ -/* TODO: - * - maybe this could print Northbridge i440LX Init? - */ static void northbridge_init(device_t dev) { printk(BIOS_SPEW, "Northbridge Init\n"); @@ -60,10 +58,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x7180, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void i440lx_domain_set_resources(device_t dev) { device_t mc_dev; @@ -99,11 +93,9 @@ static void i440lx_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i5000/northbridge.c b/src/northbridge/intel/i5000/northbridge.c index c9b99a9..cd1abc8 100644 --- a/src/northbridge/intel/i5000/northbridge.c +++ b/src/northbridge/intel/i5000/northbridge.c @@ -28,9 +28,6 @@ #include <cpu/cpu.h> #include <arch/acpi.h> #include <cbmem.h> -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { @@ -114,12 +111,10 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = tolm - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "high_tables_base: %08llx, size %lld\n", high_tables_base, high_tables_size); -#endif } static struct pci_operations intel_pci_ops = { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 07dc47b..259a9f5 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -27,6 +27,7 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include "northbridge.h" #include "i82810.h" @@ -68,10 +69,6 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -124,11 +121,10 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 768, tomk - 768); uma_resource(dev, idx++, uma_memory_base >> 10, uma_memory_size >> 10); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif + assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 8920fe7..8ee1880 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -24,6 +24,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <cbmem.h> #include <cpu/cpu.h> #include <stdlib.h> #include <string.h> @@ -49,9 +50,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3575, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -92,11 +90,9 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } static struct device_operations pci_domain_ops = { diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c index 2ff58fd..e3a3844 100644 --- a/src/northbridge/intel/i855/northbridge.c +++ b/src/northbridge/intel/i855/northbridge.c @@ -28,6 +28,7 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/x86/cache.h> #include <cpu/cpu.h> @@ -51,9 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x3580, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -107,11 +105,9 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } assign_resources(dev->link_list); } diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 63a03ad..bf3bbcb 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -26,6 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include "i945.h" @@ -80,10 +81,6 @@ static void add_fixed_resources(struct device *dev, int index) } } -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { uint32_t pci_tolm; @@ -173,11 +170,9 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk_stolen * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 4b6808a..bc63d1a 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -259,11 +259,9 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index ffeb0ed..3a71da2 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -26,6 +26,7 @@ #include <device/hypertransport.h> #include <stdlib.h> #include <string.h> +#include <cbmem.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include "sch.h" @@ -92,10 +93,6 @@ static void add_fixed_resources(struct device *dev, int index) IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { u32 pci_tolm; @@ -185,13 +182,11 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables. */ high_tables_base = tomk * 1024 - HIGH_MEMORY_SIZE; high_tables_base -= uma_memory_size; high_tables_base -= tseg_memory_base; high_tables_size = HIGH_MEMORY_SIZE; -#endif } /* diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c index 622b056..7c28d47 100644 --- a/src/northbridge/rdc/r8610/northbridge.c +++ b/src/northbridge/rdc/r8610/northbridge.c @@ -29,10 +29,7 @@ #include <stdlib.h> #include <string.h> #include <smbios.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static unsigned long get_memory_size(void) { @@ -67,11 +64,9 @@ static void cpu_pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if CONFIG_WRITE_HIGH_TABLES /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; -#endif assign_resources(dev->link_list); } diff --git a/src/northbridge/via/cn400/northbridge.c b/src/northbridge/via/cn400/northbridge.c index 088175e..bce145b 100644 --- a/src/northbridge/via/cn400/northbridge.c +++ b/src/northbridge/via/cn400/northbridge.c @@ -29,6 +29,7 @@ #include <stdlib.h> #include <string.h> #include <lib.h> +#include <cbmem.h> #include <cpu/cpu.h> #include "northbridge.h" #include "cn400.h" @@ -176,10 +177,6 @@ static void ram_reservation(device_t dev, unsigned long index, } #endif -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void cn400_domain_set_resources(device_t dev) { device_t mc_dev; @@ -206,13 +203,11 @@ static void cn400_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES /* Locate the High Tables at the Top of Low Memory below the Video RAM */ high_tables_base = ((tolmk - (CONFIG_VIDEO_MB *1024)) * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_SPEW, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 0bd06aa..2faa149 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -29,6 +29,7 @@ #include <stdlib.h> #include <string.h> #include <lib.h> +#include <cbmem.h> #include <cpu/cpu.h> #include "northbridge.h" #include "cn700.h" @@ -96,10 +97,6 @@ static const struct pci_driver memctrl_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { /* The order is important to find the correct RAM size. */ @@ -137,12 +134,10 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES high_tables_base = ((tolmk - CONFIG_VIDEO_MB * 1024) * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif /* Report the memory regions. */ idx = 10; diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index 1f045c9..69f534f 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -28,10 +28,7 @@ #include <string.h> #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> - -#if CONFIG_WRITE_HIGH_TABLES #include <cbmem.h> -#endif static void pci_domain_set_resources(device_t dev) { @@ -71,12 +68,10 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } -#if CONFIG_WRITE_HIGH_TABLES high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index 5cc7bc9..45a0ac5 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -6,6 +6,7 @@ #include <device/pci_ids.h> #include <device/hypertransport.h> #include <cpu/cpu.h> +#include <cbmem.h> #include <stdlib.h> #include <string.h> #include "northbridge.h" @@ -43,10 +44,6 @@ static const struct pci_driver northbridge_driver __pci_driver = { .device = 0x0601, /* 0x8601 is the AGP bridge? */ }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = { @@ -87,12 +84,10 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif /* Report the memory regions */ idx = 10; diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 827d3f7..f93a886 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -10,6 +10,7 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <cbmem.h> /* * This fixup is based on capturing values from an Award BIOS. Without @@ -102,10 +103,6 @@ static const struct pci_driver agp_driver __pci_driver = { .device = PCI_DEVICE_ID_VIA_8633_1, }; -#if CONFIG_WRITE_HIGH_TABLES -#include <cbmem.h> -#endif - static void pci_domain_set_resources(device_t dev) { static const uint8_t ramregs[] = {0x5a, 0x5b, 0x5c, 0x5d }; @@ -146,12 +143,10 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if CONFIG_WRITE_HIGH_TABLES high_tables_base = (tolmk * 1024) - HIGH_MEMORY_SIZE; high_tables_size = HIGH_MEMORY_SIZE; printk(BIOS_DEBUG, "tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); -#endif /* Report the memory regions */ idx = 10;

1 0

New patch to review for coreboot: 85ffe9c Unify setting i82801g IOAPIC ID
by Kyösti Mälkki 27 Feb '13

27 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2546 -gerrit commit 85ffe9cf809497193417109c290505af48d68f89 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting i82801g IOAPIC ID Remove obscure local copy of writing the ioapic registers. Change-Id: Ia703eb394991bc97aacd872ae211eefbd03e68c3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801gx/lpc.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 45d5c12..1033449 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -39,37 +39,12 @@ typedef struct southbridge_intel_i82801gx_config config_t; -static void i82801gx_enable_apic(struct device *dev) +static void i82801gx_enable_acpi(struct device *dev) { - int i; - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - - /* Enable ACPI I/O and power management. - * Set SCI IRQ to IRQ9 + /* Enable ACPI I/O range decode and ACPI power management. + * Select SCI IRQ as IRQ9. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); - for (i=0; i<3; i++) { - *ioapic_index = i; - printk(BIOS_SPEW, " reg 0x%04x:", i); - reg32 = *ioapic_data; - printk(BIOS_SPEW, " 0x%08x\n", reg32); - } - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ } static void i82801gx_enable_serial_irqs(struct device *dev) @@ -421,8 +396,10 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + i82801gx_enable_acpi(dev); + /* IO APIC initialization. */ - i82801gx_enable_apic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801gx_enable_serial_irqs(dev);

1 0

New patch to review for coreboot: 435578d Unify setting i82801e LPC
by Kyösti Mälkki 27 Feb '13

27 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2545 -gerrit commit 435578deea8cd4137a6696bf1abef8c1bb853594 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting i82801e LPC Make it more similar to i82801d LPC init. Change-Id: I7b32747ee8012c220c8628994d749999c144b716 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ex/lpc.c | 65 +++++++++++++++++++++++++----------- 1 file changed, 45 insertions(+), 20 deletions(-) diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index d0d5978..fb1586e 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -21,6 +21,45 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801ex_enable_acpi(struct device *dev) +{ + u8 gpio_cntl; + + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); + + /* Enable the GPIO bar */ + gpio_cntl = pci_read_config8(dev, GPIO_CNTL); + gpio_cntl |= GPIO_EN; + pci_write_config8(dev, GPIO_CNTL, gpio_cntl); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC configuration registers + */ +static void i82801ex_general_cntl(struct device *dev) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); + + reg32 = pci_read_config32(dev, GEN_STS); + reg32 |= (1<<1); + pci_write_config32(dev, GEN_STS, reg32); + +} + #define SERIRQ_CNTL 0x64 static void i82801ex_enable_serial_irqs(device_t dev) { @@ -237,16 +276,11 @@ static void enable_hpet(struct device *dev) static void lpc_init(struct device *dev) { uint8_t byte; - uint32_t value; int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; - /* IO APIC initialization */ - value = pci_read_config32(dev, 0xd0); - value |= (1 << 8)|(1<<7)|(1<<1); - pci_write_config32(dev, 0xd0, value); - value = pci_read_config32(dev, 0xd4); - value |= (1<<1); - pci_write_config32(dev, 0xd4, value); + i82801ex_general_cntl(dev); + + /* IO APIC initialization. */ setup_ioapic(IO_APIC_ADDR, 0); // Don't rename IO APIC ID. i82801ex_enable_serial_irqs(dev); @@ -319,20 +353,11 @@ static void i82801ex_lpc_read_resources(device_t dev) static void i82801ex_lpc_enable_resources(device_t dev) { - uint8_t acpi_cntl, gpio_cntl; - - /* Enable the normal pci resources */ + /* Enable the normal PCI resources. */ pci_dev_enable_resources(dev); - /* Enable the ACPI bar */ - acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 4); - pci_write_config8(dev, 0x44, acpi_cntl); - - /* Enable the GPIO bar */ - gpio_cntl = pci_read_config8(dev, 0x5c); - gpio_cntl |= (1 << 4); - pci_write_config8(dev, 0x5c, gpio_cntl); + /* Enable ACPI and GPIO BARs. */ + i82801ex_enable_acpi(dev); } static struct pci_operations lops_pci = {

1 0

New patch to review for coreboot: 57fbf0b Rename i82801 enable_ioapic to general_cntl
by Kyösti Mälkki 27 Feb '13

27 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2544 -gerrit commit 57fbf0b3522d77f668741b6e65681aaadef7d97d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 23:05:00 2013 +0200 Rename i82801 enable_ioapic to general_cntl The writes to IOAPIC address space is moved outside this function. New name is the PCI config register touched. Change-Id: Id7e5e63a99cbc043669bce8495886fa687756149 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ax/lpc.c | 9 ++++----- src/southbridge/intel/i82801bx/lpc.c | 10 ++++------ src/southbridge/intel/i82801cx/lpc.c | 9 ++++----- src/southbridge/intel/i82801dx/lpc.c | 9 ++++----- 4 files changed, 16 insertions(+), 21 deletions(-) diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index 1d296f4..8d4850d 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -91,7 +91,7 @@ static void i82801ax_enable_acpi(struct device *dev) * * @param dev PCI device with I/O APIC control registers */ -static void i82801ax_enable_ioapic(struct device *dev) +static void i82801ax_general_cntl(struct device *dev) { u32 reg32; @@ -101,9 +101,7 @@ static void i82801ax_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } static void i82801ax_enable_serial_irqs(struct device *dev) @@ -222,8 +220,9 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); i82801ax_enable_acpi(dev); + i82801ax_general_cntl(dev); /* IO APIC initialization. */ - i82801ax_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801ax_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 0533afb..2b36390 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -92,7 +92,7 @@ static void i82801bx_enable_acpi(struct device *dev) * * @param dev PCI device with I/O APIC control registers */ -static void i82801bx_enable_ioapic(struct device *dev) +static void i82801bx_general_cntl(struct device *dev) { u32 reg32; @@ -102,9 +102,7 @@ static void i82801bx_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } static void i82801bx_enable_serial_irqs(struct device *dev) @@ -239,9 +237,9 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); i82801bx_enable_acpi(dev); - + i82801bx_general_cntl(dev); /* IO APIC initialization. */ - i82801bx_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801bx_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index 79998bc..c6e296e 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -29,7 +29,7 @@ * * @param dev PCI device with I/O APIC control registers */ -static void i82801cx_enable_ioapic(struct device *dev) +static void i82801cx_general_cntl(struct device *dev) { u32 reg32; @@ -39,9 +39,7 @@ static void i82801cx_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } // This is how interrupts are received from the Super I/O chip @@ -150,8 +148,9 @@ static void lpc_init(struct device *dev) int pwr_on=-1; int nmi_option; + i82801cx_general_cntl(dev); /* IO APIC initialization */ - i82801cx_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801cx_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 0644569..83f6ed9 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -55,7 +55,7 @@ static void i82801dx_enable_acpi(struct device *dev) * * @param dev PCI device with I/O APIC control registers */ -static void i82801dx_enable_ioapic(struct device *dev) +static void i82801dx_general_cntl(struct device *dev) { u32 reg32; @@ -65,9 +65,7 @@ static void i82801dx_enable_ioapic(struct device *dev) reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); - printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - - set_ioapic_id(IO_APIC_ADDR, 0x02); + printk(BIOS_DEBUG, "Southbridge GEN_CNTL 0x%08x\n", reg32); } static void i82801dx_enable_serial_irqs(struct device *dev) @@ -269,8 +267,9 @@ static void lpc_init(struct device *dev) pci_write_config16(dev, PCI_COMMAND, 0x000f); i82801dx_enable_acpi(dev); + i82801dx_general_cntl(dev); /* IO APIC initialization. */ - i82801dx_enable_ioapic(dev); + set_ioapic_id(IO_APIC_ADDR, 0x02); i82801dx_enable_serial_irqs(dev);

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Patch set updated for coreboot: cea84a1 Use defines for some i82801ex/gx registers
by Kyösti Mälkki 27 Feb '13

27 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2530 -gerrit commit cea84a104165c36e1b2d9f19539e04d59e4c9dda Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 19:21:39 2013 +0200 Use defines for some i82801ex/gx registers Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ex/i82801ex.h | 7 +++++++ src/southbridge/intel/i82801ex/lpc.c | 8 +++----- src/southbridge/intel/i82801gx/i82801gx.h | 1 + src/southbridge/intel/i82801gx/lpc.c | 2 +- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..3c7321a 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -12,4 +12,11 @@ extern void i82801ex_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4) + #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..d0d5978 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,8 +12,6 @@ #include <arch/ioapic.h> #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 #define NMI_OFF 0 #define MAINBOARD_POWER_OFF 0 @@ -193,7 +191,7 @@ static void i82801ex_gpio_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); + res = find_resource(dev, GPIO_BASE); if (!res) { return; } @@ -295,10 +293,10 @@ static void i82801ex_lpc_read_resources(device_t dev) pci_dev_read_resources(dev); /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); + res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); + res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 566311f..6561399 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -80,6 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c6b76d3..45d5c12 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -49,7 +49,7 @@ static void i82801gx_enable_apic(struct device *dev) /* Enable ACPI I/O and power management. * Set SCI IRQ to IRQ9 */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; *ioapic_data = (1 << 25);

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coreboot February 2013