February 2013 - coreboot - mail.coreboot.org

New patch to review for coreboot: 8b98639 ARMv7: drop special handling for stages.c
by Stefan Reinauer Feb. 27, 2013

Feb. 27, 2013

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2543 -gerrit commit 8b9863900cde91f1327e5c68ee9a14a2708c0b29 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 21:00:01 2013 +0100 ARMv7: drop special handling for stages.c This is a leftover from when we were debugging this code. Let's make it easier to understand. Change-Id: Ia3d0ab1504ff9dd9634d5f393d3c59fe1e43a0c0 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/arch/armv7/Makefile.inc | 21 ++++++++------------- 1 file changed, 8 insertions(+), 13 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 6d4a364..33b3c4a 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -102,13 +102,8 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$< $@.tmp mv $@.tmp $@ -stages_c = $(src)/arch/armv7/stages.c -stages_o = $(obj)/arch/armv7/stages.o - -$(stages_o): $(stages_c) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $< -marm - +ramstage-y += stages.c +romstage-y += stages.c ################################################################################ # Build the coreboot_ram (stage 2) @@ -121,12 +116,12 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/coreboot_ram.ld $< endif -$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --wrap __do_div64 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif CFLAGS += \ @@ -246,20 +241,20 @@ endif ################################################################################ # Build the romstage -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage_null.ld +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) $(stages_o) -T $(objgenerated)/romstage_xip.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(stages_o) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions

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Patch merged into coreboot/master: 9c29cfa Fix microcode selection code
by gerrit＠coreboot.org Feb. 27, 2013

Feb. 27, 2013

the following patch was just integrated into master: commit 9c29cfae8cc6214478a0a555e6901779eb19ef54 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 20:24:11 2013 +0100 Fix microcode selection code The ARM CPUs we know of don't have CPU microcode updates, so don't show the selection in Kconfig. Also simplify (and fix) the microcode selection in the Makefile that would try to include microcode even though none is available. Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/2540 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed Feb 27 20:53:12 2013, giving +1 See http://review.coreboot.org/2540 for details. -gerrit

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Patch set updated for coreboot: e0853ba ARM: remove disassembly output for stages.o
by Ronald G. Minnich Feb. 27, 2013

Feb. 27, 2013

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2541 -gerrit commit e0853ba5acf0c2b36966b88ce4d90f36b6fa70f8 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 27 11:44:48 2013 -0800 ARM: remove disassembly output for stages.o It produces a confusing warning (since .o files have lots of undefined symbols) and a dump of assembly, which we really don't need to see any more. Change-Id: I381b9176dfff7d3e1c843f7f1b0c9f1c2f321fda Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 6d4a364..e0203ae 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -107,7 +107,7 @@ stages_o = $(obj)/arch/armv7/stages.o $(stages_o): $(stages_c) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $< -marm + $(CC) -I. $(INCLUDES) -c -o $@ $< -marm ################################################################################

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New patch to review for coreboot: 335be49 ARM: remove disassembly output for stages.o
by Ronald G. Minnich Feb. 27, 2013

Feb. 27, 2013

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2541 -gerrit commit 335be4903dc30cdb4d247c4332360b3d4e10ceb3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 27 11:44:48 2013 -0800 ARM: remove disassembly output for stages.o It produces a confusing warning (since .o files have lots of undefined symbols) and a dump of assembly, which we really don't need to see any more. Change-Id: I381b9176dfff7d3e1c843f7f1b0c9f1c2f321fda Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/armv7/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 6d4a364..ae527d4 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -107,7 +107,7 @@ stages_o = $(obj)/arch/armv7/stages.o $(stages_o): $(stages_c) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $< -marm + $(CC) -I. $(INCLUDES) -c -o $@ $< -marm ################################################################################ @@ -126,7 +126,9 @@ $(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --wrap __do_div64 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else + echo "HI THERE!" $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + echo "BTTE!" endif CFLAGS += \

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Patch set updated for coreboot: c288753 Fix microcode selection code
by Stefan Reinauer Feb. 27, 2013

Feb. 27, 2013

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2540 -gerrit commit c288753c36115c47df6845544181e3364a7adfde Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 20:24:11 2013 +0100 Fix microcode selection code The ARM CPUs we know of don't have CPU microcode updates, so don't show the selection in Kconfig. Also simplify (and fix) the microcode selection in the Makefile that would try to include microcode even though none is available. Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/Kconfig | 2 +- src/cpu/Makefile.inc | 18 ++++++++---------- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index bb27da0..6177285 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -76,7 +76,7 @@ config CPU_MICROCODE_IN_CBFS default n choice - prompt "Include CPU microcode in CBFS" + prompt "Include CPU microcode in CBFS" if ARCH_X86 default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index e1efecc..b48a803 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -11,21 +11,21 @@ subdirs-y += via ## Rules for building the microcode blob in CBFS ################################################################################ -ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE), y) - -cbfs-files-y += cpu_microcode_blob.bin - -cpu_microcode_blob.bin-type = 0x53 - # External microcode file, or are we generating one ? ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL), y) +cbfs-files-y += cpu_microcode_blob.bin +cpu_microcode_blob.bin-type = 0x53 cpu_microcode_blob.bin-file = $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) -else +endif + +ifeq ($(CONFIG_CPU_MICROCODE_CBFS_GENERATE), y) +cbfs-files-y += cpu_microcode_blob.bin +cpu_microcode_blob.bin-type = 0x53 cpu_microcode_blob.bin-file = $(obj)/cpu_microcode_blob.bin endif # In case we have more than one "source" (cough) files containing microcode, we -# Link them together in one large blob, so that we get all the microcode updates +# link them together in one large blob, so that we get all the microcode updates # in one file. This makes it easier for objcopy in the final step. # The --entry=0 is just here to suppress the LD warning. It does not affect the # final microcode file. @@ -38,5 +38,3 @@ $(obj)/cpu_microcode_blob.o: $$(cpu_microcode-objs) $(obj)/cpu_microcode_blob.bin: $(obj)/cpu_microcode_blob.o @printf " MICROCODE $(subst $(obj)/,,$(@))\n" $(OBJCOPY) -j .data -O binary $< $@ - -endif

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New patch to review for coreboot: 49c56df Only offer microcode updates for x86
by Stefan Reinauer Feb. 27, 2013

Feb. 27, 2013

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2540 -gerrit commit 49c56df0de311d5950e4a18974c623d6acb3f59f Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Wed Feb 27 20:24:11 2013 +0100 Only offer microcode updates for x86 The ARM CPUs we know of don't have CPU microcode updates. Change-Id: I502d9b48d4449c1a759b5e90478ad37eef866406 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/cpu/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index bb27da0..6177285 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -76,7 +76,7 @@ config CPU_MICROCODE_IN_CBFS default n choice - prompt "Include CPU microcode in CBFS" + prompt "Include CPU microcode in CBFS" if ARCH_X86 default CPU_MICROCODE_CBFS_GENERATE if CPU_MICROCODE_IN_CBFS default CPU_MICROCODE_CBFS_NONE if !CPU_MICROCODE_IN_CBFS

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New patch to review for coreboot: a03b3cb ARM: don't try to include microcode.
by Ronald G. Minnich Feb. 27, 2013

Feb. 27, 2013

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2539 -gerrit commit a03b3cb244c76e0334076da491e082174554e41d Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 27 11:06:10 2013 -0800 ARM: don't try to include microcode. ARM's don't have it. There may be a cleaner way to do this but I got lost in the microcode configuration options. Change-Id: Ief1e4b8708fa344acb65c564e030ec6b050079c8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/cpu/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index bb27da0..ac431e1 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -3,6 +3,10 @@ # (See also src/Kconfig) if ARCH_ARMV7 +config ARCH_SPECIFIC_OPTIONS + def_bool y + select CPU_MICROCODE_CBFS_NONE + source src/cpu/armltd/Kconfig source src/cpu/samsung/Kconfig

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Patch merged into coreboot/master: eeb3632 Google/snow: update the GPIO emulation.
by gerrit＠coreboot.org Feb. 27, 2013

Feb. 27, 2013

the following patch was just integrated into master: commit eeb36326b9402aaa009c0a672c3b3ecb80300297 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 27 10:12:03 2013 -0800 Google/snow: update the GPIO emulation. Add two more GPIOs (total 6) as needed by the Google Snow laptop. These are faking out settings for now. This code is tested and working. Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/2538 Reviewed-by: Peter Stuge <peter(a)stuge.se> Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Wed Feb 27 19:21:01 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Feb 27 19:18:42 2013, giving +2 See http://review.coreboot.org/2538 for details. -gerrit

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New patch to review for coreboot: 9ccae34 Google/snow: update the GPIO emulation.
by Ronald G. Minnich Feb. 27, 2013

Feb. 27, 2013

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2538 -gerrit commit 9ccae34b1bf959792244d0d767ed8cda7613e4c1 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Feb 27 10:12:03 2013 -0800 Google/snow: update the GPIO emulation. Add two more GPIOs (total 6) as needed by the Google Snow laptop. These are faking out settings for now. This code is tested and working. Change-Id: I2077ffb8b85958eefdf54e19763d57cc1178ce89 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/google/snow/chromeos.c | 28 ++++++++++++++++++++-------- 1 file changed, 20 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c index 5f8e631..fd2006c 100644 --- a/src/mainboard/google/snow/chromeos.c +++ b/src/mainboard/google/snow/chromeos.c @@ -34,7 +34,7 @@ #include <boot/coreboot_tables.h> #include <arch/coreboot_tables.h> -#define GPIO_COUNT 4 +#define GPIO_COUNT 6 void fill_lb_gpios(struct lb_gpios *gpios) { @@ -55,18 +55,30 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[1].value = 0; strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH); - /* Developer: virtual GPIO active high */ + /* Lid: the "switch" comes from the EC */ gpios->gpios[2].port = -1; gpios->gpios[2].polarity = ACTIVE_HIGH; - gpios->gpios[2].value = 1; - strncpy((char *)gpios->gpios[2].name,"developer", - GPIO_MAX_NAME_LENGTH); + gpios->gpios[2].value = 0; + strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH); - /* Was VGA Option ROM loaded? */ - gpios->gpios[3].port = -1; /* Indicate that this is a pseudo GPIO */ + /* Power: hardcoded as not pressed */ + gpios->gpios[3].port = -1; gpios->gpios[3].polarity = ACTIVE_HIGH; gpios->gpios[3].value = 0; - strncpy((char *)gpios->gpios[3].name,"oprom", GPIO_MAX_NAME_LENGTH); + strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH); + + /* Developer: virtual GPIO active high */ + gpios->gpios[4].port = -1; + gpios->gpios[4].polarity = ACTIVE_HIGH; + gpios->gpios[4].value = 0; + strncpy((char *)gpios->gpios[4].name,"developer", + GPIO_MAX_NAME_LENGTH); + + /* Was VGA Option ROM loaded? */ + gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */ + gpios->gpios[5].polarity = ACTIVE_HIGH; + gpios->gpios[5].value = 0; + strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH); printk(BIOS_ERR, "Added %d GPIOS size %d\n", GPIO_COUNT, gpios->size);

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Patch merged into coreboot/master: fc14874 Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cb
by gerrit＠coreboot.org Feb. 27, 2013

Feb. 27, 2013

the following patch was just integrated into master: commit fc14874352a07a11d91f59ae24e0b162b85821c8 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Wed Feb 27 15:21:21 2013 +0100 Persimmon: remove HDMI Audio, PCI device 00:01.1 from devicetree.cb Commit 8487229b (Persimmon doesn't have HDMI so the GNB HD Audio should be disabled.) turned off the device in AGESA. Now remove it from devicetree.cb, too. This prevents the following boot message: PCI: Left over static devices: PCI: 00:01.1 PCI: Check your devicetree.cb. Also clarify the line's comment a bit for the Fam14 boards which still retain this device (to counter the loss of information ;-). Change-Id: Ib671ed2e0d04bdef2869e8d70208d6e55cdea3fd Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2537 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Wed Feb 27 16:59:38 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Wed Feb 27 17:05:46 2013, giving +2 See http://review.coreboot.org/2537 for details. -gerrit

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