coreboot February 2013

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Patch set updated for coreboot: c782264 AMD Inagua: buildOpts.c: Adapt whitespace to coding style
by Paul Menzel 26 Feb '13

26 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2526 -gerrit commit c78226436ebe18852db4fdae6377a4a13df091de Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 25 14:58:23 2013 +0100 AMD Inagua: buildOpts.c: Adapt whitespace to coding style Mainly replace spaces by tabs and format comments correctly. Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was unfortunately incomplete and also used spaces instead of tabs in some cases. Hopefully fix this once and for all to have a template for the other boards. [1] http://review.coreboot.org/547 Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/buildOpts.c | 374 +++++++++++++++++------------------ 1 file changed, 187 insertions(+), 187 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 49eb7bf..e310f83 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -37,23 +37,23 @@ #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE -/* Select the cpu family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -61,163 +61,163 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE -#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE +#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 /* * Agesa configuration values selection. @@ -259,7 +259,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "GnbInterface.h" /***************************************************************************** - * Define the RELEASE VERSION string + * Define the RELEASE VERSION string * * The Release Version string should identify the next planned release. * When a branch is made in preparation for a release, the release manager @@ -288,7 +288,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1333_FREQUENCY 667 ///< DDR 1333 #define DDR1600_FREQUENCY 800 ///< DDR 1600 #define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM @@ -297,22 +297,22 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = /* USER_MEMORY_TIMING_MODE */ #define TIMING_MODE_AUTO 0 ///< Use best rate possible #define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) // Instantiate all solution relevant data. #include "PlatformInstall.h" @@ -323,10 +323,10 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // @@ -396,7 +396,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { #include "mm.h" #include "mn.h" -//DA Customer table +// DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { // Hardcoded Memory Training Values

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Patch set updated for coreboot: 749d560 ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED`
by Jens Rottmann 26 Feb '13

26 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2489 -gerrit commit 749d5602284d479d275e3917aac34b77c55b052f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Feb 23 00:15:49 2013 +0100 ASRock E350M1: Let `BiosGnbPcieSlotReset()` return `AGESA_UNSUPPORTED` Quoting Jens Rottmann [1]: Nevertheless I still think this whole function is bogus for the E350M1. The function assumes GPIO21 is wired to reset APU PCIe lane 0+1 (PCIe x8, port 4+5 as Coreboot/AGESA calls it), GPIO25 resets lane 2 (PCIe x4) and GPIO02 lane 3. But the E350M1 has PCIe x16 i.e. probably APU lanes 0-3 bundled, completely different layout. They could have chosen GPIO21 to force resets, or 25 - or maybe 50 like on the Persimmon or any other they fancied or - and this is the most probable - none at all. Having BiosGnbPcieSlotReset() toggle some GPIOs without knowing what they do on the E350M1 (if anything at all) is nonsense. In my opinion this whole function should just "return AGESA_UNSUPPORTED" and good riddance. [1] http://review.coreboot.org/#/c/2445/ Change-Id: Iac66da41182e838c7e6925250cc3982adbb3e4ec Reported-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 77 +-------------------------- src/mainboard/asrock/e350m1/BiosCallOuts.h | 9 +--- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 8 +-- 3 files changed, 6 insertions(+), 88 deletions(-) diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 8aa4398..642a68e 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -525,80 +525,5 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - PCIe_SLOT_RESET_INFO *ResetInfo; - - UINT32 GpioMmioAddr; - UINT32 AcpiMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - ResetInfo = ConfigPtr; - // Get SB800 MMIO Base (AcpiMmioAddr) - WriteIo8(0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16=Data8<<8; - WriteIo8(0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16|=Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - Status = AGESA_UNSUPPORTED; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - switch (ResetInfo->ResetId) - { - case 4: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG21); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG21, Data8); // MXM_GPIO0. GPIO21 - Status = AGESA_SUCCESS; - break; - } - break; - case 6: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8); // PCIE_RST#_LAN, GPIO25 - Status = AGESA_SUCCESS; - break; - } - break; - case 7: - switch (ResetInfo->ResetControl) - { - case AssertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 &= ~(UINT8)BIT6 ; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - case DeassertSlotReset: - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG02); - Data8 |= BIT6 ; - Write64Mem8 (GpioMmioAddr+SB_GPIO_REG02, Data8); // MPCIE_RST0, GPIO02 - Status = AGESA_SUCCESS; - break; - } - break; - } - return Status; + return AGESA_UNSUPPORTED; } diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.h b/src/mainboard/asrock/e350m1/BiosCallOuts.h index 71d8fa4..9fd032f 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.h +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.h @@ -66,12 +66,5 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* PCIE slot reset control */ AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -#define SB_GPIO_REG02 2 -#define SB_GPIO_REG09 9 -#define SB_GPIO_REG10 10 -#define SB_GPIO_REG15 15 -#define SB_GPIO_REG17 17 -#define SB_GPIO_REG21 21 -#define SB_GPIO_REG25 25 -#define SB_GPIO_REG28 28 + #endif //_BIOS_CALLOUT_H_ diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index c36e50a..156c2ac 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -59,26 +59,26 @@ PCIe_PORT_DESCRIPTOR PortList [] = { { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) }, #if 1 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7) + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) }, #endif // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)

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Patch merged into coreboot/master: 89ccc92 libpayload: Add a pointer for user data on the USB MSC data structure.
by gerrit＠coreboot.org 26 Feb '13

26 Feb '13

the following patch was just integrated into master: commit 89ccc9285e3bdc3108e6d33dbe83ac9a4f048bc0 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Nov 1 18:46:05 2012 -0700 libpayload: Add a pointer for user data on the USB MSC data structure. This is so the user of libpayload can attach data to the device which it can retrieve when the device is referred to later, for instance in usbdisk_remove. Otherwise, there's no direct connection from the usbdev_t structure to any bookkeeping in the host firmware. Change-Id: I36fe693b0dcd2098e359c26744e376e73bd3a723 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2513 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.huber(a)secunet.com> Build-Tested: build bot (Jenkins) at Tue Feb 26 01:32:01 2013, giving +1 See http://review.coreboot.org/2513 for details. -gerrit

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New patch to review for coreboot: 6380ed4 Unify setting 82801a/b/c/d IOAPIC ID
by Kyösti Mälkki 26 Feb '13

26 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2532 -gerrit commit 6380ed4d17a0af3b2c5da1340c8c91355b5fe8e2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 17:24:41 2013 +0200 Unify setting 82801a/b/c/d IOAPIC ID Remove obscure local copy of writing the ioapic registers. Change-Id: I133e710639ff57c6a0ac925e30efce2ebc43b856 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ax/Kconfig | 1 + src/southbridge/intel/i82801ax/lpc.c | 39 ++++++++++++++------------ src/southbridge/intel/i82801bx/Kconfig | 1 + src/southbridge/intel/i82801bx/lpc.c | 39 ++++++++++++++------------ src/southbridge/intel/i82801cx/Kconfig | 2 +- src/southbridge/intel/i82801cx/lpc.c | 44 ++++++++++++----------------- src/southbridge/intel/i82801dx/i82801dx.h | 1 + src/southbridge/intel/i82801dx/lpc.c | 46 ++++++++++++++++--------------- 8 files changed, 87 insertions(+), 86 deletions(-) diff --git a/src/southbridge/intel/i82801ax/Kconfig b/src/southbridge/intel/i82801ax/Kconfig index 70734a7..71ae016 100644 --- a/src/southbridge/intel/i82801ax/Kconfig +++ b/src/southbridge/intel/i82801ax/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801AX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801ax/lpc.c b/src/southbridge/intel/i82801ax/lpc.c index c9404ed..1d296f4 100644 --- a/src/southbridge/intel/i82801ax/lpc.c +++ b/src/southbridge/intel/i82801ax/lpc.c @@ -70,17 +70,30 @@ typedef struct southbridge_intel_i82801ax_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801ax_enable_apic(struct device *dev) -{ - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)IO_APIC_ADDR; - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); + +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801ax_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801ax_enable_ioapic(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -90,18 +103,7 @@ static void i82801ax_enable_apic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); } static void i82801ax_enable_serial_irqs(struct device *dev) @@ -219,8 +221,9 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + i82801ax_enable_acpi(dev); /* IO APIC initialization. */ - i82801ax_enable_apic(dev); + i82801ax_enable_ioapic(dev); i82801ax_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801bx/Kconfig b/src/southbridge/intel/i82801bx/Kconfig index 00cb5bf..3d725d4 100644 --- a/src/southbridge/intel/i82801bx/Kconfig +++ b/src/southbridge/intel/i82801bx/Kconfig @@ -19,6 +19,7 @@ config SOUTHBRIDGE_INTEL_I82801BX bool + select IOAPIC select HAVE_HARD_RESET select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801bx/lpc.c b/src/southbridge/intel/i82801bx/lpc.c index 0ff44e6..0533afb 100644 --- a/src/southbridge/intel/i82801bx/lpc.c +++ b/src/southbridge/intel/i82801bx/lpc.c @@ -72,17 +72,29 @@ typedef struct southbridge_intel_i82801bx_config config_t; * Use the defined IRQ values above or set mainboard * specific IRQ values in your devicetree.cb. */ -static void i82801bx_enable_apic(struct device *dev) -{ - uint32_t reg32; - volatile uint32_t *ioapic_index = (volatile uint32_t *)IO_APIC_ADDR; - volatile uint32_t *ioapic_data = (volatile uint32_t *)(IO_APIC_ADDR + 0x10); +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801bx_enable_acpi(struct device *dev) +{ /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); /* Enable ACPI I/O range decode and ACPI power management. */ pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801bx_enable_ioapic(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ @@ -92,18 +104,7 @@ static void i82801bx_enable_apic(struct device *dev) pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - /* TODO: From i82801ca, needed/useful on other ICH? */ - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); } static void i82801bx_enable_serial_irqs(struct device *dev) @@ -237,8 +238,10 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + i82801bx_enable_acpi(dev); + /* IO APIC initialization. */ - i82801bx_enable_apic(dev); + i82801bx_enable_ioapic(dev); i82801bx_enable_serial_irqs(dev); diff --git a/src/southbridge/intel/i82801cx/Kconfig b/src/southbridge/intel/i82801cx/Kconfig index 17e90e8..3e01cb8 100644 --- a/src/southbridge/intel/i82801cx/Kconfig +++ b/src/southbridge/intel/i82801cx/Kconfig @@ -1,4 +1,4 @@ config SOUTHBRIDGE_INTEL_I82801CX bool + select IOAPIC select HAVE_HARD_RESET - diff --git a/src/southbridge/intel/i82801cx/lpc.c b/src/southbridge/intel/i82801cx/lpc.c index a1ffb8f..79998bc 100644 --- a/src/southbridge/intel/i82801cx/lpc.c +++ b/src/southbridge/intel/i82801cx/lpc.c @@ -24,34 +24,24 @@ #define MAINBOARD_POWER_ON 1 -static void i82801cx_enable_ioapic( struct device *dev) +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801cx_enable_ioapic(struct device *dev) { - uint32_t dword; - volatile uint32_t* ioapic_index = (volatile uint32_t*)IO_APIC_ADDR; - volatile uint32_t* ioapic_data = (volatile uint32_t*)(IO_APIC_ADDR + 0x10); - - dword = pci_read_config32(dev, GEN_CNTL); - dword |= (3 << 7); /* enable ioapic & disable SMBus interrupts */ - dword |= (1 <<13); /* coprocessor error enable */ - dword |= (1 << 1); /* delay transaction enable */ - dword |= (1 << 2); /* DMA collection buf enable */ - pci_write_config32(dev, GEN_CNTL, dword); - printk(BIOS_DEBUG, "ioapic southbridge enabled %x\n",dword); - - // Must program the APIC's ID before using it - - *ioapic_index = 0; // Select APIC ID register - *ioapic_data = (2<<24); - - // Hang if the ID didn't take (chip not present?) - *ioapic_index = 0; - dword = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge apic id = %x\n", (dword>>24) & 0xF); - if(dword != (2<<24)) - die(""); - - *ioapic_index = 3; // Select Boot Configuration register - *ioapic_data = 1; // Use Processor System Bus to deliver interrupts + u32 reg32; + + reg32 = pci_read_config32(dev, GEN_CNTL); + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ + pci_write_config32(dev, GEN_CNTL, reg32); + printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); + + set_ioapic_id(IO_APIC_ADDR, 0x02); } // This is how interrupts are received from the Super I/O chip diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index d9e4d38..2da7759 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -82,6 +82,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE_ADDR 0x0400 #define DEFAULT_PMBASE PMBASE_ADDR #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index fbf8e12..0644569 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -36,37 +36,38 @@ typedef struct southbridge_intel_i82801dx_config config_t; -static void i82801dx_enable_ioapic(struct device *dev) +/** + * Enable ACPI I/O range. + * + * @param dev PCI device with ACPI and PM BAR's + */ +static void i82801dx_enable_acpi(struct device *dev) { - u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); - volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - /* Set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1)); - /* Enable ACPI I/O and power management. */ - pci_write_config8(dev, ACPI_CNTL, 0x10); + /* Enable ACPI I/O range decode and ACPI power management. */ + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); +} + +/** + * Set miscellanous static southbridge features. + * + * @param dev PCI device with I/O APIC control registers + */ +static void i82801dx_enable_ioapic(struct device *dev) +{ + u32 reg32; reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (3 << 7); /* Enable IOAPIC */ - reg32 |= (1 << 13); /* Coprocessor error enable */ - reg32 |= (1 << 1); /* Delayed transaction enable */ - reg32 |= (1 << 2); /* DMA collection buffer enable */ + reg32 |= (1 << 13); /* Coprocessor error enable (COPR_ERR_EN) */ + reg32 |= (3 << 7); /* IOAPIC enable (APIC_EN) */ + reg32 |= (1 << 2); /* DMA collection buffer enable (DCB_EN) */ + reg32 |= (1 << 1); /* Delayed transaction enable (DTE) */ pci_write_config32(dev, GEN_CNTL, reg32); printk(BIOS_DEBUG, "IOAPIC Southbridge enabled %x\n", reg32); - *ioapic_index = 0; - *ioapic_data = (1 << 25); - - *ioapic_index = 0; - reg32 = *ioapic_data; - printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", reg32); - if (reg32 != (1 << 25)) - die("APIC Error\n"); - - *ioapic_index = 3; /* Select Boot Configuration register. */ - *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ + set_ioapic_id(IO_APIC_ADDR, 0x02); } static void i82801dx_enable_serial_irqs(struct device *dev) @@ -267,6 +268,7 @@ static void lpc_init(struct device *dev) /* Set the value for PCI command register. */ pci_write_config16(dev, PCI_COMMAND, 0x000f); + i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev);

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Patch set updated for coreboot: 2b68c88 IOAPIC: Divide setup_ioapic() in two parts.
by Kyösti Mälkki 26 Feb '13

26 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/300 -gerrit commit 2b68c88a9f1f20b3eb30a32562b7302050d0e891 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 31 17:24:12 2012 +0200 IOAPIC: Divide setup_ioapic() in two parts. Currently some southbridge codes implement the set_ioapic_id() part locally and do not implement the load_vectors() part at all. This change allows clean-up of those southbridges without introducing changed behaviour. Change-Id: Ic5e860b9b669ecd1e9ddac4bbb92d80bdb9c2fca Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/ioapic.h | 1 + src/arch/x86/lib/ioapic.c | 19 ++++++++++++++----- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index 01fd753..b989e52 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -39,6 +39,7 @@ #define SMI (2 << 8) #define INT (1 << 8) +void set_ioapic_id(u32 ioapic_base, u8 ioapic_id); void setup_ioapic(u32 ioapic_base, u8 ioapic_id); void clear_ioapic(u32 ioapic_base); #endif diff --git a/src/arch/x86/lib/ioapic.c b/src/arch/x86/lib/ioapic.c index fc5e307..6243f55 100644 --- a/src/arch/x86/lib/ioapic.c +++ b/src/arch/x86/lib/ioapic.c @@ -74,11 +74,9 @@ void clear_ioapic(u32 ioapic_base) } } -void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +void set_ioapic_id(u32 ioapic_base, u8 ioapic_id) { u32 bsp_lapicid = lapicid(); - u32 low, high; - u32 i, ioapic_interrupts; printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); @@ -92,6 +90,13 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) (io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) | (ioapic_id << 24)); } +} + +static void load_vectors(u32 ioapic_base) +{ + u32 bsp_lapicid = lapicid(); + u32 low, high; + u32 i, ioapic_interrupts; ioapic_interrupts = ioapic_interrupt_count(ioapic_base); @@ -123,10 +128,8 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); - low = DISABLED; high = NONE; - for (i = 1; i < ioapic_interrupts; i++) { io_apic_write(ioapic_base, i * 2 + 0x10, low); io_apic_write(ioapic_base, i * 2 + 0x11, high); @@ -135,3 +138,9 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id) i, high, low); } } + +void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +{ + set_ioapic_id(ioapic_base, ioapic_id); + load_vectors(ioapic_base); +}

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New patch to review for coreboot: 5c13922 Add more code to correclty set up native graphics.
by Ronald G. Minnich 26 Feb '13

26 Feb '13

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2531 -gerrit commit 5c1392262e0f7e7c0490f6a9f9b98fa2edb3a966 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Feb 26 10:07:40 2013 -0800 Add more code to correclty set up native graphics. The link commit was missing some of the higher level bits to enable native graphics. Add options to src/device/Kconfig to enable them. Export an mtrr function for variable mtrrs. Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/boot/coreboot_table.c | 2 +- src/cpu/x86/mtrr/mtrr.c | 2 +- src/device/Kconfig | 26 +++++++++++++---- src/device/oprom/realmode/x86.c | 4 +-- src/include/cpu/x86/mtrr.h | 7 +++++ src/northbridge/intel/sandybridge/gma.c | 49 +++++++++++++++++++++++++++------ 6 files changed, 72 insertions(+), 18 deletions(-) diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c index 04fba47..a8d3537 100644 --- a/src/arch/x86/boot/coreboot_table.c +++ b/src/arch/x86/boot/coreboot_table.c @@ -172,7 +172,7 @@ static void lb_console(struct lb_header *header) static void lb_framebuffer(struct lb_header *header) { -#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE +#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE || defined(CONFIG_MAINBOARD_DO_NATIVE_INIT) void fill_lb_framebuffer(struct lb_framebuffer *framebuffer); int vbe_mode_info_valid(void); diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a061b54..5051904 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -83,7 +83,7 @@ static void enable_var_mtrr(void) } /* setting variable mtrr, comes from linux kernel source */ -static void set_var_mtrr( +void set_var_mtrr( unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type, unsigned address_bits) { diff --git a/src/device/Kconfig b/src/device/Kconfig index 82583a4..cf4e42d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -19,12 +19,26 @@ ## menu "Devices" + +# Only set this in the mainboard +config MAINBOARD_HAS_NATIVE_VGA_INIT + bool + default n + +config MAINBOARD_DO_NATIVE_VGA_INIT + bool "use Native graphics setup code" + depends on MAINBOARD_HAS_NATIVE_VGA_INIT + default n + help + Enable mainboard code to turn on graphics, but without needing a video BIOS. + This mode is only supported on some mainboards, such as the Google Link. + # TODO: Explain differences (if any) for onboard cards. config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on (! MAINBOARD_DO_NATIVE_VGA_INIT) && PCI && !PAYLOAD_SEABIOS || EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -94,7 +108,7 @@ choice config PCI_OPTION_ROM_RUN_REALMODE prompt "Native mode" bool - depends on ARCH_X86 + depends on ARCH_X86 && ! MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, @@ -104,7 +118,7 @@ config PCI_OPTION_ROM_RUN_REALMODE config PCI_OPTION_ROM_RUN_YABEL prompt "Secure mode" bool - depends on !GEODE_VSA + depends on !GEODE_VSA && ! MAINBOARD_DO_NATIVE_VGA_INIT help If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs. @@ -282,12 +296,12 @@ config MBI_FILE endmenu menu "Display" - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT config FRAMEBUFFER_SET_VESA_MODE prompt "Set VESA framebuffer mode" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help Set VESA framebuffer mode (needed for bootsplash) @@ -425,7 +439,7 @@ config FRAMEBUFFER_VESA_MODE config FRAMEBUFFER_KEEP_VESA_MODE prompt "Keep VESA framebuffer" bool - depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT help This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 5fd11b5..6a8bdfc 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -191,7 +191,7 @@ static void setup_realmode_idt(void) write_idt_stub((void *)0xffe6e, 0x1a); } -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT vbe_mode_info_t mode_info; static int mode_info_valid; @@ -322,7 +322,7 @@ void run_bios(struct device *dev, unsigned long addr) realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0); printk(BIOS_DEBUG, "... Option ROM returned.\n"); -#if CONFIG_FRAMEBUFFER_SET_VESA_MODE +#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT if ((dev->class >> 8)== PCI_CLASS_DISPLAY_VGA) vbe_set_graphics(); #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 58bee04..0986709 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -40,6 +40,13 @@ #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) #include <device/device.h> +/* you should almost NEVER use this. */ +/* N.B. We worked on a lot of ways to make this continue as static, + * but just making it available ended up being the simplest solution. + */ +void set_var_mtrr( + unsigned int reg, unsigned long basek, unsigned long sizek, + unsigned char type, unsigned address_bits); void enable_fixed_mtrr(void); void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); void x86_setup_mtrrs(void); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 52707bd..ae6a565 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -23,6 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include "chip.h" #include "sandybridge.h" @@ -619,20 +622,49 @@ static void gma_pm_init_post_vbios(struct device *dev) static void gma_func0_init(struct device *dev) { u32 reg32; + u32 graphics_base, graphics_size; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); + /* Set up an MTRR to make anything the VBIOS does run fast. */ + /* we have agreed on MTRR #8 */ + /* the BAR for graphics space is a well known number for + * sandy and ivy. And the resource code renumbers it. + * So it's almost like having two hardcodes. + */ + graphics_base = dev->resource_list[1].base; + graphics_size = dev->resource_list[1].size; + printk(BIOS_DEBUG, "gma_func0_init: set graphics %p size 0x%x\n", + (void *)graphics_base, graphics_size); + /* the consensus is we use this mtrr */ + set_var_mtrr(8, graphics_base>>10, graphics_size>>10, MTRR_TYPE_WRCOMB, 0x24); + /* Init graphics power management */ gma_pm_init_pre_vbios(dev); /* PCI Init, will run VBIOS */ +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "Run the VBIOS init\n"); pci_dev_init(dev); +#endif /* Post VBIOS init */ gma_pm_init_post_vbios(dev); + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); + u32 iobase, mmiobase, physbase; + iobase = dev->resource_list[2].base; + mmiobase = dev->resource_list[0].base; + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); + i915lightup(physbase, iobase, mmiobase, graphics_base); +#endif + } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -660,12 +692,13 @@ static struct device_operations gma_func0_ops = { .ops_pci = &gma_pci_ops, }; -static const unsigned short gma_ids[] = { - 0x0102, 0x0106, 0x010a, 0x0112, 0x0116, 0x0122, 0x0126, 0x0156, 0x166, - 0, -}; -static const struct pci_driver gma_gt1_desktop __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices= gma_ids, +static const unsigned short pci_device_ids[] = { 0x0102, 0x0106, 0x010a, 0x0112, + 0x0116, 0x0122, 0x0126, 0x0156, + 0x0166, + 0 }; + +static const struct pci_driver pch_lpc __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, };

1 0

New patch to review for coreboot: 2a8394c Use defines for some i82801ex/gx registers
by Kyösti Mälkki 26 Feb '13

26 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2530 -gerrit commit 2a8394cfecdfcb84cc3a8a417047ac5e51b16c17 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 19:21:39 2013 +0200 Use defines for some i82801ex/gx registers Change-Id: I0069ec26278b82d61ce5bcfb94d77647dfd3254b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/intel/i82801ex/i82801ex.h | 7 +++++++ src/southbridge/intel/i82801ex/lpc.c | 8 +++----- src/southbridge/intel/i82801gx/i82801gx.h | 1 + src/southbridge/intel/i82801gx/lpc.c | 2 +- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 67fecdd..3c7321a 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -12,4 +12,11 @@ extern void i82801ex_enable(device_t dev); #define RTC_CONF 0xd8 #define GEN_PMCON_3 0xa4 +#define PMBASE 0x40 +#define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 4) +#define GPIO_BASE 0x58 +#define GPIO_CNTL 0x5C +#define GPIO_EN (1 << 4) + #endif /* I82801EX_H */ diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c index 998360c..d0d5978 100644 --- a/src/southbridge/intel/i82801ex/lpc.c +++ b/src/southbridge/intel/i82801ex/lpc.c @@ -12,8 +12,6 @@ #include <arch/ioapic.h> #include "i82801ex.h" -#define ACPI_BAR 0x40 -#define GPIO_BAR 0x58 #define NMI_OFF 0 #define MAINBOARD_POWER_OFF 0 @@ -193,7 +191,7 @@ static void i82801ex_gpio_init(device_t dev) /* Get the chip configuration */ config = dev->chip_info; /* Find the GPIO bar */ - res = find_resource(dev, GPIO_BAR); + res = find_resource(dev, GPIO_BASE); if (!res) { return; } @@ -295,10 +293,10 @@ static void i82801ex_lpc_read_resources(device_t dev) pci_dev_read_resources(dev); /* Add the ACPI BAR */ - res = pci_get_resource(dev, ACPI_BAR); + res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ - res = pci_get_resource(dev, GPIO_BAR); + res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 566311f..6561399 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -80,6 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index c6b76d3..45d5c12 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -49,7 +49,7 @@ static void i82801gx_enable_apic(struct device *dev) /* Enable ACPI I/O and power management. * Set SCI IRQ to IRQ9 */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + pci_write_config8(dev, ACPI_CNTL, ACPI_EN); *ioapic_index = 0; *ioapic_data = (1 << 25);

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Patch merged into coreboot/master: 5e70766 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt
by gerrit＠coreboot.org 26 Feb '13

26 Feb '13

the following patch was just integrated into master: commit 5e70766f14253f53190ddd49a544460c6bc1e528 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt This patch reduces unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1. It's only cosmetical, but makes them a little bit easier to compare. This is the remainder of the original http://review.coreboot.org/2464, parts of which somehow got lost in a flurry of refactoring and splitting patches. Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Reviewed-on: http://review.coreboot.org/2529 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter(a)stuge.se> Build-Tested: build bot (Jenkins) at Tue Feb 26 16:29:32 2013, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Tue Feb 26 16:53:16 2013, giving +2 See http://review.coreboot.org/2529 for details. -gerrit

1 0

New patch to review for coreboot: dddb777 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt
by Jens Rottmann 26 Feb '13

26 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2529 -gerrit commit dddb77790818a66bd761e56ec6329587cd1756c8 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 26 15:56:11 2013 +0100 AMD Fam14 boards: reduce unnecessary differences, 2nd attempt This patch reduces unnecessary differences between AMD Inagua, Persimmon, Union Station, South Station and Asrock E350M1. It's only cosmetical, but makes them a little bit easier to compare. This is the remainder of the original http://review.coreboot.org/2464, parts of which somehow got lost in a flurry of refactoring and splitting patches. Change-Id: I034228be9edaaa4122506763d7bb4158f8e0ec53 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/mainboard/amd/inagua/mainboard.c | 8 ++++---- src/mainboard/amd/persimmon/mainboard.c | 6 +++--- src/mainboard/amd/persimmon/platform_cfg.h | 4 ++-- src/mainboard/amd/south_station/mainboard.c | 6 +++--- src/mainboard/amd/union_station/mainboard.c | 6 +++--- src/mainboard/asrock/e350m1/mainboard.c | 6 +++--- 6 files changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 2e2edc3..83ac9e8 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -70,9 +70,9 @@ void set_pcie_dereset(void) } -/************************************************* - * enable the dedicated function in INAGUA board. - *************************************************/ +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -82,5 +82,5 @@ static void mainboard_enable(device_t dev) } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c index 2f7cfd1..2d4916c 100644 --- a/src/mainboard/amd/persimmon/mainboard.c +++ b/src/mainboard/amd/persimmon/mainboard.c @@ -50,9 +50,9 @@ void set_pcie_dereset(void) } -/************************************************* -* enable the dedicated function in persimmon board. -*************************************************/ +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 6590e4e..80e27ac 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -244,7 +244,7 @@ static const CODECENTRY persimmon_codec_alc269[] = {0xff, 0xffffffff} /* end of table */ }; -static const CODECTBLLIST persimmon_codec_tablelist[] = +static const CODECTBLLIST codec_tablelist[] = { {0x010ec0269, (CODECENTRY*)&persimmon_codec_alc269[0]}, {0x0FFFFFFFFUL, (CODECENTRY*)0x0FFFFFFFFUL} @@ -254,7 +254,7 @@ static const CODECTBLLIST persimmon_codec_tablelist[] = * @def AZALIA_OEM_VERB_TABLE * Mainboard specific cocec verb table list */ -#define AZALIA_OEM_VERB_TABLE (&persimmon_codec_tablelist[0]) +#define AZALIA_OEM_VERB_TABLE (&codec_tablelist[0]) /* set up an ACPI prefered power management profile */ /* from acpi.h diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c index 4d3c804..0b0f208 100644 --- a/src/mainboard/amd/south_station/mainboard.c +++ b/src/mainboard/amd/south_station/mainboard.c @@ -73,9 +73,9 @@ static void southstation_led_init(void) } -/************************************************* -* enable the dedicated function in southstation board. -*************************************************/ +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c index 57dfe44..c12e785 100644 --- a/src/mainboard/amd/union_station/mainboard.c +++ b/src/mainboard/amd/union_station/mainboard.c @@ -46,9 +46,9 @@ void set_pcie_dereset(void) } -/************************************************* -* enable the dedicated function in unionstation board. -*************************************************/ +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index 2bedff5..b92a149 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -45,9 +45,9 @@ void set_pcie_dereset(void) } -/************************************************* -* enable the dedicated function in e350m1 board. -*************************************************/ +/********************************************** + * Enable the dedicated functions of the board. + **********************************************/ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

1 0

New patch to review for coreboot: 12242d0 AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabled
by Jens Rottmann 26 Feb '13

26 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2528 -gerrit commit 12242d0cd697e6b9c04ca505fd5ed71f9ff03206 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 26 12:37:22 2013 +0100 AGESA: skip s3_resume.h if CONFIG_HAVE_ACPI_RESUME is disabled Commit 22ec9f9a introduced a check throwing an error if S3_DATA_SIZE isn't big enough. However without CONFIG_HAVE_ACPI_RESUME S3_DATA_SIZE isn't defined at all and compilation will fail if s3_resume.h is included. This patch makes it again possible turn off HAVE_ACPI_RESUME relatively easily in Parmer/Thatcher/Persimmon's Kconfig if you don't care about S3 and don't want flash writes on every boot. Change-Id: I999e4b7634bf172d8380fd14cba6f7f03468fee3 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/cpu/amd/agesa/s3_resume.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/amd/agesa/s3_resume.h b/src/cpu/amd/agesa/s3_resume.h index af5b509..441e952 100644 --- a/src/cpu/amd/agesa/s3_resume.h +++ b/src/cpu/amd/agesa/s3_resume.h @@ -20,6 +20,8 @@ #ifndef S3_RESUME_H #define S3_RESUME_H +#if CONFIG_HAVE_ACPI_RESUME + /* The size needs to be 4k aligned, which is the sector size of most flashes. */ #define S3_DATA_VOLATILE_SIZE 0x6000 #define S3_DATA_MTRR_SIZE 0x1000 @@ -48,3 +50,5 @@ void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); void OemAgesaSaveMtrr (void); #endif + +#endif

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coreboot February 2013