coreboot February 2013

coreboot@coreboot.org

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Patch merged into coreboot/master: 502533f Revert "AMD S3: Program the flash in a bigger data packet"
by gerrit＠coreboot.org 26 Feb '13

26 Feb '13

the following patch was just integrated into master: commit 502533f656d41632f3b8ec19c385e8efa8c264a6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Feb 25 10:39:48 2013 -0700 Revert "AMD S3: Program the flash in a bigger data packet" This reverts commit ca6e1f6c04c96c435bdbf30a1b88cab0e5be330b. The packet size changes ends up corrupting the flash when booting Persimmon. I did figure out that the maximum number of bytes that can be sent is actually 8 bytes according to the sb800 spec. There must be additional problems beyond that since setting the packet size to 8 still causes problems. Change-Id: Ieb24247cf79e95bb0e548c83601dfddffbf6be59 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/2509 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-by: Zheng Bao <zheng.bao(a)amd.com> Build-Tested: build bot (Jenkins) at Mon Feb 25 18:59:24 2013, giving +1 Reviewed-By: Zheng Bao <zheng.bao(a)amd.com> at Tue Feb 26 03:33:48 2013, giving +2 See http://review.coreboot.org/2509 for details. -gerrit

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New patch to review for coreboot: 1262d0e libpayload: Check for completion more often in ehci_set_periodic_schedule.
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2522 -gerrit commit 1262d0e0493d24a6230ddfef14e3883963b2eae4 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 21 02:16:13 2012 -0800 libpayload: Check for completion more often in ehci_set_periodic_schedule. This function was using mdelay in a loop to check for the completion of an USB controller operation. Since we're busy waiting anyway, we might as well wait only 1 us before checking again and potentially seeing the completion 999 us earlier than we would otherwise. Change-Id: I177b303c5503a0078c608d5f945c395691d4bd8a Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/drivers/usb/ehci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 3e57902..ec33b18 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -157,10 +157,10 @@ static int ehci_set_periodic_schedule(ehci_t *ehcic, int enable) * This shouldn't take too long, but we should timeout nevertheless. */ enable = enable ? HC_OP_PERIODIC_SCHED_STAT : 0; - int timeout = 100; /* time out after 100ms */ + int timeout = 100000; /* time out after 100ms */ while (((ehcic->operation->usbsts & HC_OP_PERIODIC_SCHED_STAT) != enable) && timeout--) - mdelay(1); + udelay(1); if (timeout < 0) { usb_debug("ehci periodic schedule status change timed out.\n"); return 1;

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New patch to review for coreboot: 0930c8a libpayload: Correct a constant used for scanning for USB controllers.
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2521 -gerrit commit 0930c8acc9df77916ce0bd651178dcc52e3e66c1 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 21 01:52:27 2012 -0800 libpayload: Correct a constant used for scanning for USB controllers. When checking to see if a PCI device exists at a particular bus/dev/func, libpayload was checking the vendor and device id fields together against a 16 bit 0xffff. The two fields together are 32 bits, however, so the check was never true, and all dev/func combinations on a particular bus would be checked. That was slightly wasteful, but had relatively small impact. Change-Id: Iad537295c33083243940b18e7a99af92857e1ef2 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/drivers/usb/usbinit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 2e466d3..74358bb 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -123,7 +123,7 @@ static void usb_scan_pci_bus(int bus) u8 header_type; pcidev_t addr = PCI_DEV(bus, dev, 0); /* Check if there's a device here at all. */ - if (pci_read_config32(addr, REG_VENDOR_ID) == 0xffff) + if (pci_read_config32(addr, REG_VENDOR_ID) == 0xffffffff) continue; header_type = pci_read_config8(addr, REG_HEADER_TYPE); /* If this is a bridge, scan the bus on the other side. */

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New patch to review for coreboot: a41ab1f libpayload: Change the measurement interval for get_cpu_speed to 2 ms.
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2520 -gerrit commit a41ab1f7bd81dee45bcf5470b950e01ec1900a85 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 21 01:01:50 2012 -0800 libpayload: Change the measurement interval for get_cpu_speed to 2 ms. The interval used to be about 55 ms which is excessively long. Coreboot only waits for 2 ms and gets a reasonable answer. That should be good enough for us as well. Change-Id: I4d4e8b25b6ba540c9e9839ed0bbaa1f04f67cce1 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/arch/x86/timer.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index ae288eb..40e81c4 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -49,6 +49,8 @@ u32 cpu_khz; unsigned int get_cpu_speed(void) { unsigned long long start, end; + const uint32_t clock_rate = 1193182; // 1.193182 MHz + const uint16_t interval = (2 * clock_rate) / 1000; // 2 ms /* Set up the PPC port - disable the speaker, enable the T2 gate. */ outb((inb(0x61) & ~0x02) | 0x01, 0x61); @@ -56,9 +58,9 @@ unsigned int get_cpu_speed(void) /* Set the PIT to Mode 0, counter 2, word access. */ outb(0xB0, 0x43); - /* Load the counter with 0xffff. */ - outb(0xff, 0x42); - outb(0xff, 0x42); + /* Load the interval into the counter. */ + outb(interval & 0xff, 0x42); + outb((interval >> 8) & 0xff, 0x42); /* Read the number of ticks during the period. */ start = rdtsc(); @@ -66,11 +68,11 @@ unsigned int get_cpu_speed(void) end = rdtsc(); /* - * The clock rate is 1193180 Hz, the number of milliseconds for a - * period of 0xffff is 1193180 / (0xFFFF * 1000) or .0182. - * Multiply that by the number of measured clocks to get the kHz value. + * The number of milliseconds for a period is + * clock_rate / (interval * 1000). Multiply that by the number of + * measured clocks to get the kHz value. */ - cpu_khz = (unsigned int)((end - start) * 1193180U / (1000 * 0xffff)); + cpu_khz = (end - start) * clock_rate / (1000 * interval); return cpu_khz; }

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New patch to review for coreboot: 3e0ff3d Intel Pantherpoint USB3 intialization
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2519 -gerrit commit 3e0ff3d8b3b2a7f08cb3a40a2b295b65d8d748c4 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Nov 13 15:07:45 2012 -0700 Intel Pantherpoint USB3 intialization Add PEI updates and ACPI updates for supporting EHCI to XHCI USB port support. Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/intel/sandybridge/pei_data.h | 12 ++++- src/southbridge/intel/bd82x6x/acpi/globalnvs.asl | 14 +++++ src/southbridge/intel/bd82x6x/acpi/pch.asl | 23 ++++---- src/southbridge/intel/bd82x6x/acpi/usb.asl | 69 ++++++++++++++++++++++++ src/southbridge/intel/bd82x6x/early_usb.c | 9 ++++ src/southbridge/intel/bd82x6x/nvs.h | 4 +- src/southbridge/intel/bd82x6x/pch.h | 6 ++- src/southbridge/intel/bd82x6x/smihandler.c | 14 +++++ 8 files changed, 139 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 8c907c1..8036d2f 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -30,8 +30,16 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +typedef struct { + uint16_t mode; // 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto + uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable + uint16_t preboot_support; // 0: No xHCI preOS driver; 1: xHCI preOS driver + uint16_t xhci_streams; // 0: Disable; 1: Enable +} pch_usb3_controller_settings; + typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 4 +#define PEI_VERSION 5 + struct pei_data { uint32_t pei_version; @@ -92,6 +100,8 @@ struct pei_data * < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude) */ uint16_t usb_port_config[16][3]; + /* See the usb3 struct above for details */ + pch_usb3_controller_settings usb3; /* SPD data array for onboard RAM. Specify address 0xf0, * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in * spd_address for a given "DIMM". diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl index 2fe092d..99edc31 100644 --- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl +++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl @@ -136,6 +136,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) GTF2, 56, // 0xa4 - GTF task file buffer for port 2 IDEM, 8, // 0xab - IDE mode (compatible / enhanced) IDET, 8, // 0xac - IDE + /* XHCI */ + Offset (0xb2), + XHCI, 8, /* IGD OpRegion */ Offset (0xb4), ASLB, 32, // 0xb4 - IGD OpRegion Base Address @@ -223,6 +226,17 @@ Method (S3GD) Store (Zero, \S33G) } +/* Set XHCI Mode enable */ +Method (XHCE) +{ + Store (One, \XHCI) +} + +/* Set XHCI Mode disable */ +Method (XHCD) +{ + Store (Zero, \XHCI) +} External (\_TZ.THRM) External (\_TZ.SKIN) diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8632ad8..2f75fdc 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -245,7 +245,7 @@ Scope(\) // PCI Express Ports 0:1c.x #include "pcie.asl" -// USB 0:1d.0 and 0:1a.0 +// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0 #include "usb.asl" // LPC Bridge 0:1f.0 @@ -259,17 +259,22 @@ Scope(\) Method (_OSC, 4) { - /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + /* Check for XHCI */ + If (LEqual (Arg0, ToUUID("7c9512a9-1705-4cb4-af7d-506a2423ab71"))) { - /* Let OS control everything */ - Return (Arg3) + Return (^XHC.POSC(Arg1, Arg2, Arg3)) } - Else + + /* Check for PCIe */ + If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { - /* Unrecognized UUID */ - CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + /* Let OS control everything */ Return (Arg3) } + + /* Else Return Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index cf3e6a0..00fae90 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -89,3 +89,72 @@ Device (EHC2) } } +Device (XHC) +{ + Name(_ADR, 0x00140000) + OperationRegion(XDEV, PCI_Config, 0, 256) + Field(XDEV, DWordAcc, NoLock, Preserve) + { + Offset(0xD0), + X2PR, 32, // XUSB2PR + PRM2, 32, // XUSB2PRM + SSEN, 32, // USB3_PSSEN + RPM3, 32, // USB3PRM + XPRT, 32, // XHCI Ports + } + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + Method(POSC,3,Serialized) + { + // Create DWord field from the Capabilities Buffer + CreateDWordField(Arg2,0,CDW1) + + // Check revision + If(LNotEqual(Arg1,One)) { + // Set unknown revision bit + Or(CDW1,0x8,CDW1) + } + + // Set failure if xHCI is disabled by BIOS + If(LEqual(XHCI, 0)) { + Or(CDW1,0x2,CDW1) + } + + // Query flag clear and xHCI in auto mode + If(LAnd(LNot(And(CDW1,0x1)),LOr(LEqual(XHCI ,2), LEqual(XHCI ,3)))) { + Store ("XHCI Switch", Debug) + Store(Zero, Local0) + And(XPRT, 0x3, Local0) + If(LOr(LEqual(Local0, 0), LEqual(Local0, 1))) { + Store(0xF, Local1) + } + ElseIf(LEqual(Local0, 2)) { + Store(0x3, Local1) + } + ElseIf(LEqual(Local0, 3)) { + Store(Zero, Local1) + } + And(RPM3, 0xFFFFFFF0, Local0) + Or(Local0, Local1, RPM3) + And(PRM2, 0xFFFFFFF0, Local0) + Or(Local0, Local1, PRM2) + And(SSEN, 0xFFFFFFF0, Local0) + Or(Local0, Local1, SSEN) + And(X2PR, 0xFFFFFFF0, Local0) + Or(Local0, Local1, X2PR) + } + Return(Arg2) + } + + // Leave USB ports on for to allow Wake from USB + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 95906e3..66970f1 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -27,6 +27,7 @@ #define PCH_EHCI1_TEMP_BAR0 0xe8000000 #define PCH_EHCI2_TEMP_BAR0 0xe8000400 +#define PCH_XHCI_TEMP_BAR0 0xe8001000 /* * Setup USB controller MMIO BAR to prevent the @@ -39,6 +40,7 @@ void enable_usb_bar(void) { device_t usb0 = PCH_EHCI1_DEV; device_t usb1 = PCH_EHCI2_DEV; + device_t usb3 = PCH_XHCI_DEV; u32 cmd; /* USB Controller 1 */ @@ -54,4 +56,11 @@ void enable_usb_bar(void) cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); + + /* USB3 Controller */ + pci_write_config32(usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0); + cmd = pci_read_config32(usb3, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb3, PCI_COMMAND, cmd); } diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index b8506d4..d315e0a 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -113,7 +113,9 @@ typedef struct { u8 gtf2[7]; u8 idem; u8 idet; - u8 rsvd11[7]; + u8 rsvd11[6]; + /* XHCI */ + u8 xhci; /* IGD OpRegion (not implemented yet) */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ u8 ibtt; /* 0xb8 - IGD boot type */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1211671..2ec33a6 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -95,6 +95,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) +#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_PCIE_DEV_SLOT 28 @@ -365,6 +366,8 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define D22IP_IDERIP 8 /* IDE-R Pin */ #define D22IP_MEI2IP 4 /* MEI #2 Pin */ #define D22IP_MEI1IP 0 /* MEI #1 Pin */ +#define D20IP 0x3128 /* 32bit */ +#define D20IP_XHCIIP 0 #define D31IR 0x3140 /* 16bit */ #define D30IR 0x3142 /* 16bit */ #define D29IR 0x3144 /* 16bit */ @@ -373,6 +376,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define D26IR 0x314c /* 16bit */ #define D25IR 0x3150 /* 16bit */ #define D22IR 0x315c /* 16bit */ +#define D20IR 0x3160 /* 16bit */ #define OIC 0x31fe /* 16bit */ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 @@ -392,7 +396,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define CG 0x341c /* 32bit */ /* Function Disable 1 RCBA 0x3418 */ -#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)|(1 << 27)) +#define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) #define PCH_DISABLE_P2P (1 << 1) #define PCH_DISABLE_SATA1 (1 << 2) #define PCH_DISABLE_SMBUS (1 << 3) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 804607c..5735a31 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -326,6 +326,17 @@ static void southbridge_gate_memory_reset(void) outl(reg32, gpiobase + GP_LVL2); } +static void xhci_sleep(u8 slp_typ) +{ + u32 reg32; + + if (slp_typ == SLP_TYP_S5) { + reg32 = pcie_read_config32(PCH_XHCI_DEV, 0x74); + reg32 |= (1 << 8 | 0x03 ); + pcie_write_config32(PCH_XHCI_DEV, 0x74, reg32); + } +} + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { u8 reg8; @@ -353,6 +364,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); slp_typ = (reg32 >> 10) & 7; + if(smm_get_gnvs()->xhci) + xhci_sleep(slp_typ); + /* Do any mainboard sleep handling */ tseg_relocate((void **)&mainboard_sleep); if (mainboard_sleep)

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New patch to review for coreboot: 31eb3a3 Intel HD Audio: clean up initialization code
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2518 -gerrit commit 31eb3a380688cec60eb3077cb372fcccdbc8f174 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Nov 14 12:25:15 2012 -0800 Intel HD Audio: clean up initialization code - Some initialization steps were done twice - One step was missing for Panther Point HDA - Added a 1ms delay after reset - Increased timeout to 1ms for all codec operations Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> --- src/southbridge/intel/bd82x6x/azalia.c | 43 ++++++++++++++++------------------ 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index a257daf..0ca58c4 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -120,10 +120,9 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) static int wait_for_ready(u32 base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ + /* Use a 1msec timeout */ - int timeout = 50; + int timeout = 1000; while(timeout--) { u32 reg32 = read32(base + HDA_ICII_REG); @@ -150,10 +149,9 @@ static int wait_for_valid(u32 base) reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ + /* Use a 1msec timeout */ - int timeout = 50; + int timeout = 1000; while(timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == @@ -254,12 +252,12 @@ static void azalia_init(struct device *dev) if (RCBA32(0x2030) & (1 << 31)) { reg32 = pci_mmio_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; - reg32 |= (1 << 24); // 25 for server + reg32 |= (1 << 24); // 2 << 24 for server reg32 |= RCBA32(0x2030) & 0xfe; pci_mmio_write_config32(dev, 0x120, reg32); reg16 = pci_mmio_read_config16(dev, 0x78); - reg16 &= ~(1 << 11); + reg16 |= (1 << 11); pci_mmio_write_config16(dev, 0x78, reg16); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); @@ -269,12 +267,9 @@ static void azalia_init(struct device *dev) pci_mmio_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | - (1 << 25) | (1 << 26))) { - reg32 = pci_mmio_read_config32(dev, 0x120); - reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); - } + reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 |= (1 << 31); + pci_mmio_write_config32(dev, 0x120, reg32); // Enable HDMI codec: reg32 = pci_read_config32(dev, 0xc4); @@ -287,15 +282,6 @@ static void azalia_init(struct device *dev) /* Additional programming steps */ reg32 = pci_read_config32(dev, 0xc4); - reg32 |= (1 << 13) | (1 << 10); - pci_write_config32(dev, 0xc4, reg32); - - reg32 = pci_read_config32(dev, 0xd0); - reg32 &= ~(1 << 31); - pci_write_config32(dev, 0xd0, reg32); - - /* Additional programming steps */ - reg32 = pci_read_config32(dev, 0xc4); reg32 |= (1 << 13); pci_write_config32(dev, 0xc4, reg32); @@ -307,6 +293,13 @@ static void azalia_init(struct device *dev) reg32 &= ~(1 << 31); pci_write_config32(dev, 0xd0, reg32); + if (dev->device == 0x1e20) { + /* Additional step on Panther Point */ + reg32 = pci_read_config32(dev, 0xc4); + reg32 |= (1 << 17); + pci_write_config32(dev, 0xc4, reg32); + } + /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); @@ -314,9 +307,13 @@ static void azalia_init(struct device *dev) pci_write_config8(dev, 0x3c, 0x0a); // unused? /* Codec Initialization Programming Sequence */ + + /* Take controller out of reset */ reg32 = read32(base + 0x08); reg32 |= (1 << 0); write32(base + 0x08, reg32); + /* Wait 1ms */ + udelay(1000); // reg8 = pci_read_config8(dev, 0x40); // Audio Control

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New patch to review for coreboot: a61b7e4 libpayload: Handle multifunction bridge devices better.
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2517 -gerrit commit a61b7e41c6cbdf01a8e459e3715520de27d2b720 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Nov 8 19:31:23 2012 -0800 libpayload: Handle multifunction bridge devices better. This change modifies the code in libpayload that scans the PCI hierarchy for USB controllers. Previously, if a devices primary function (function 0) was a bridge, then none of the other functions, if any, would be looked at. If one of the other functions was a bridge, that wouldn't be handled either. The new version looks at each function that's present no matter what, and if it discovers that it's a bridge it scans the other side. Change-Id: I37f269a4fe505fd32d9594e2daf17ddd78609c15 Signed-off-by: Gabe Black <gabeblack(a)google.com> --- payloads/libpayload/drivers/usb/usbinit.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/payloads/libpayload/drivers/usb/usbinit.c b/payloads/libpayload/drivers/usb/usbinit.c index 2e466d3..36cf5e4 100644 --- a/payloads/libpayload/drivers/usb/usbinit.c +++ b/payloads/libpayload/drivers/usb/usbinit.c @@ -126,14 +126,6 @@ static void usb_scan_pci_bus(int bus) if (pci_read_config32(addr, REG_VENDOR_ID) == 0xffff) continue; header_type = pci_read_config8(addr, REG_HEADER_TYPE); - /* If this is a bridge, scan the bus on the other side. */ - if ((header_type & ~HEADER_TYPE_MULTIFUNCTION) == - HEADER_TYPE_BRIDGE) { - int sub_bus = - pci_read_config8(addr, REG_SECONDARY_BUS); - usb_scan_pci_bus(sub_bus); - continue; - } /* * EHCI is defined by standards to be at a higher function * than the USB1 controllers. We don't want to init USB1 + @@ -141,11 +133,22 @@ static void usb_scan_pci_bus(int bus) * comes first. */ /* Check for a multifunction device. */ + int top_func = 0; if (header_type & HEADER_TYPE_MULTIFUNCTION) - for (func = 7; func > 0; func--) + top_func = 7; + for (func = top_func; func >= 0; func--) { + addr = PCI_DEV(bus, dev, func); + header_type = pci_read_config8(addr, REG_HEADER_TYPE); + /* If this is a bridge, scan the other side. */ + if ((header_type & ~HEADER_TYPE_MULTIFUNCTION) == + HEADER_TYPE_BRIDGE) { + int sub_bus = pci_read_config8(addr, + REG_SECONDARY_BUS); + usb_scan_pci_bus(sub_bus); + } else { usb_controller_initialize(bus, dev, func); - /* Initialize function 0. */ - usb_controller_initialize(bus, dev, 0); + } + } } }

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New patch to review for coreboot: 2746947 xcompile: use LINKER_SUFFIX for x-compiling
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2516 -gerrit commit 2746947a006993d6d2e3b574f302abb83d8539b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 8 17:26:29 2012 -0600 xcompile: use LINKER_SUFFIX for x-compiling The LINKER_SUFFIX environment variable was introduced but never actually used. Actually use it. Change-Id: I9edb8b63b5742e13dbf0e7b6034814acea11fc52 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index ea975ec..5d6d858 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -118,7 +118,7 @@ report_arch_toolchain() { # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) CC_${TARCH}:=${GCCPREFIX}gcc ${CFLAGS} AS_${TARCH}:=${GCCPREFIX}as ${ASFLAGS} -LD_${TARCH}:=${GCCPREFIX}ld ${LDFLAGS} +LD_${TARCH}:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS} NM_${TARCH}:=${GCCPREFIX}nm OBJCOPY_${TARCH}:=${GCCPREFIX}objcopy OBJDUMP_${TARCH}:=${GCCPREFIX}objdump

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New patch to review for coreboot: 9b73f5f smm: Update rev 0x30101 SMM revision save state
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2515 -gerrit commit 9b73f5f1a4e5d92b1f0833a07f075dbe74538aa9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 7 12:27:29 2012 -0600 smm: Update rev 0x30101 SMM revision save state According to both Haswell and the SandyBridge/Ivybridge BWGs the save state area actually starts at 0x7c00 offset from 0x8000. Update the em64t101_smm_state_save_area_t structure and introduce a define for the offset. Note: I have no idea what eptp is. It's just listed in the haswell BWG. The offsets should not be changed. Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/cpu/x86/smm/smihandler.c | 29 +++++++++++++---------- src/include/cpu/x86/smm.h | 37 ++++++++++++++++++++---------- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- 3 files changed, 43 insertions(+), 25 deletions(-) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 10f38f9..b4b7f36 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -107,6 +107,12 @@ static void smi_restore_pci_address(void) outl(pci_orig, 0xcf8); } +static inline void *smm_save_state(u32 base, int arch_offset, int node) +{ + base += SMM_SAVE_STATE_BEGIN(arch_offset) - (node * 0x400); + return (void *)base; +} + /** * @brief Interrupt handler for SMI# * @@ -117,13 +123,13 @@ void smi_handler(u32 smm_revision) { unsigned int node; smm_state_save_area_t state_save; - u32 smm_base = 0xa8000; /* ASEG */ + u32 smm_base = 0xa0000; /* ASEG */ #if CONFIG_SMM_TSEG /* Update global variable TSEG base */ if (!smi_get_tseg_base()) return; - smm_base = smi_get_tseg_base() + 0x8000; + smm_base = smi_get_tseg_base(); #else /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -151,24 +157,23 @@ void smi_handler(u32 smm_revision) case 0x00030002: case 0x00030007: state_save.type = LEGACY; - state_save.legacy_state_save = (legacy_smm_state_save_area_t *) - (smm_base + 0x7e00 - (node * 0x400)); + state_save.legacy_state_save = + smm_save_state(smm_base, 0x7e00, node); break; case 0x00030100: state_save.type = EM64T; - state_save.em64t_state_save = (em64t_smm_state_save_area_t *) - (smm_base + 0x7d00 - (node * 0x400)); - break; - case 0x00030101: /* SandyBridge/IvyBridge */ + state_save.em64t_state_save = + smm_save_state(smm_base, 0x7d00, node); + case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ state_save.type = EM64T101; state_save.em64t101_state_save = - (em64t101_smm_state_save_area_t *) - (smm_base + 0x7d00 - (node * 0x400)); + smm_save_state(smm_base, + SMM_EM64T101_ARCH_OFFSET, node); break; case 0x00030064: state_save.type = AMD64; - state_save.amd64_state_save = (amd64_smm_state_save_area_t *) - (smm_base + 0x7e00 - (node * 0x400)); + state_save.amd64_state_save = + smm_save_state(smm_base, 0x7e00, node); break; default: printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index b52a315..3ffebf4 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -27,6 +27,9 @@ /* used only by C programs so far */ #define SMM_BASE 0xa0000 +#define SMM_ENTRY_OFFSET 0x8000 +#define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x)) + #include <types.h> typedef struct { u16 es_selector; @@ -202,11 +205,17 @@ typedef struct { /* Intel Revision 30101 SMM State-Save Area - * Used in SandyBridge/IvyBridge architecture - * starts @ 0x7d00 + * The following processor architectures use this: + * - SandyBridge + * - IvyBridge + * - Haswell */ +#define SMM_EM64T101_ARCH_OFFSET 0x7c00 +#define SMM_EM64T101_SAVE_STATE_OFFSET \ + SMM_SAVE_STATE_BEGIN(SMM_EM64T101_ARCH_OFFSET) typedef struct { - u8 reserved0[208]; + u8 reserved0[256]; + u8 reserved1[208]; u32 gdtr_upper_base; u32 ldtr_upper_base; @@ -219,25 +228,29 @@ typedef struct { u64 io_rcx; u64 io_rsi; - u8 reserved1[52]; + u8 reserved2[52]; u32 shutdown_auto_restart; - u8 reserved2[8]; + u8 reserved3[8]; u32 cr4; - u8 reserved3[72]; + u8 reserved4[72]; u32 gdtr_base; - u8 reserved4[4]; - u32 idtr_base; u8 reserved5[4]; + u32 idtr_base; + u8 reserved6[4]; u32 ldtr_base; - u8 reserved6[68]; + u8 reserved7[56]; + /* EPTP fields are only on Haswell according to BWGs, but Intel was + * wise and reused the same revision number. */ + u64 eptp; + u32 eptp_en; u32 cs_base; - u8 reserved7[4]; + u8 reserved8[4]; u32 iedbase; - u8 reserved8[8]; + u8 reserved9[8]; u32 smbase; u32 smm_revision; @@ -245,7 +258,7 @@ typedef struct { u16 io_restart; u16 autohalt_restart; - u8 reserved9[24]; + u8 reserved10[24]; u64 r15; u64 r14; diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 804607c..420c5db 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -432,7 +432,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) { em64t101_smm_state_save_area_t *state; - u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00; + u32 base = smi_get_tseg_base() + SMM_EM64T101_SAVE_STATE_OFFSET; int node; /* Check all nodes looking for the one that issued the IO */

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New patch to review for coreboot: a35a2f9 Mainboard SMI S state handler was using the wrong defines
by Stefan Reinauer 26 Feb '13

26 Feb '13

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2514 -gerrit commit a35a2f918c5b9275d31ac61c2e2895dd03af8610 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Mon Nov 5 17:25:52 2012 -0700 Mainboard SMI S state handler was using the wrong defines The PCH register bit definition for sleep type is a little confusing. For example, 7 is S5. To make this simpler for the mainbaord developer, the mainboard smi sleep hander is called as mainboard_sleep(slp_typ-2). A couple mainboard SMI handlers were using the PCH define for slp_ty, so S3 code would be run for S5 and S5 code would never be run. Change-Id: Iaecf96bfd48cf00153600cd119760364fbdfc29e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/intel/emeraldlake2/smihandler.c | 6 +++--- src/mainboard/samsung/stumpy/smihandler.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/emeraldlake2/smihandler.c b/src/mainboard/intel/emeraldlake2/smihandler.c index 03c505b..acc1fde 100644 --- a/src/mainboard/intel/emeraldlake2/smihandler.c +++ b/src/mainboard/intel/emeraldlake2/smihandler.c @@ -59,11 +59,11 @@ void mainboard_smi_sleep(u8 slp_typ) u8 reg8; switch (slp_typ) { - case SLP_TYP_S3: - case SLP_TYP_S4: + case 3: + case 4: break; - case SLP_TYP_S5: + case 5: /* Turn off LED */ reg8 = inb(SIO_GPIO_BASE_SET4); reg8 |= (1 << 5); diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 660bb31..5eda0a1 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -62,8 +62,8 @@ void mainboard_smi_sleep(u8 slp_typ) u8 reg8; switch (slp_typ) { - case SLP_TYP_S3: - case SLP_TYP_S4: + case 3: + case 4: /* Blink LED */ it8772f_enter_conf(); it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); @@ -79,7 +79,7 @@ void mainboard_smi_sleep(u8 slp_typ) it8772f_exit_conf(); break; - case SLP_TYP_S5: + case 5: /* Turn off LED */ reg8 = inb(SIO_GPIO_BASE_SET4); reg8 |= (1 << 5);

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coreboot February 2013