Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2513
-gerrit
commit 7327da570507836df772695b5b64d30f075e0789
Author: Gabe Black <gabeblack(a)google.com>
Date: Thu Nov 1 18:46:05 2012 -0700
libpayload: Add a pointer for user data on the USB MSC data structure.
This is so the user of libpayload can attach data to the device which it can
retrieve when the device is referred to later, for instance in usbdisk_remove.
Otherwise, there's no direct connection from the usbdev_t structure to any
bookkeeping in the host firmware.
Change-Id: I36fe693b0dcd2098e359c26744e376e73bd3a723
Signed-off-by: Gabe Black <gabeblack(a)google.com>
---
payloads/libpayload/include/usb/usbmsc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/payloads/libpayload/include/usb/usbmsc.h b/payloads/libpayload/include/usb/usbmsc.h
index fafa6f5..5c3dadc 100644
--- a/payloads/libpayload/include/usb/usbmsc.h
+++ b/payloads/libpayload/include/usb/usbmsc.h
@@ -36,6 +36,7 @@ typedef struct {
endpoint_t *bulk_in;
endpoint_t *bulk_out;
int usbdisk_created;
+ void *data; /* For use by consumers of libpayload. */
} usbmsc_inst_t;
#define MSC_INST(dev) ((usbmsc_inst_t*)(dev)->data)
the following patch was just integrated into master:
commit a96d24d672abfd2ce91caa2d762fdce3d67da600
Author: Mike Loptien <mike.loptien(a)se-eng.com>
Date: Mon Feb 25 10:41:28 2013 -0700
AMD Southbridge: Add RTC init to lpc_init
Adding RTC init code to the Southbridge initialization
code in 'lpc_init'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same edit made to the CIMX SB800 titled
'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
ID: c4d3d which can be viewed here:
http://review.coreboot.org/#/c/2488/
Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/2510
Reviewed-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
Build-Tested: build bot (Jenkins) at Mon Feb 25 19:08:10 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 25 19:05:24 2013, giving +2
Reviewed-By: Martin Roth <martin.roth(a)se-eng.com> at Mon Feb 25 19:02:14 2013, giving +1
Reviewed-By: Dave Frodin <dave.frodin(a)se-eng.com> at Mon Feb 25 19:28:43 2013, giving +2
See http://review.coreboot.org/2510 for details.
-gerrit
the following patch was just integrated into master:
commit 7675d8a481c6cbeba418f00f2eb733d904171a41
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Sun Feb 24 15:09:11 2013 -0700
Supermicro H8SCM & H8QGI: Fix printk warnings
Changes:
- Fix printk warnings for these two platforms by getting rid of the
l length specifier and casting to unsigned int.
This gets rid of a bunch of warnings like this one:
agesawrapper.c:279, GNU Compiler 4 (gcc), Priority: Normal
format '%lu' expects argument of type 'long unsigned int',
but argument 3 has type 'UINT32' [-Wformat]
Notes:
- This is the same change that was done for Tyan s8226 in change:
ddff32eb - http://review.coreboot.org/#/c/2451/
Tyan S8226: Fix printk warnings
- I have not tested this change on either of these platforms, I have
just compiled it.
Change-Id: I46b4c13fde7473cd2a084c7c7cb5c893f1731b02
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/2502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Sun Feb 24 23:25:56 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 25 19:02:17 2013, giving +2
See http://review.coreboot.org/2502 for details.
-gerrit
the following patch was just integrated into master:
commit 4f5a433a987faeed2cf21fbfca5d2604ef2d7edb
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Sun Feb 24 14:12:32 2013 -0700
AMD Southstation: Fix final warning
Changes:
- Add #include of delay.h in mainboard.c to pick up declaration of
mdelay function.
Notes:
- This fixes this warning:
mainboard.c:69, GNU Compiler 4 (gcc), Priority: Normal
implicit declaration of function 'mdelay' [-Wimplicit-function-declaration]
Change-Id: I72f333cd87215a7fc1e62d1d7ee4b2395444b03e
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/2501
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Sun Feb 24 22:31:34 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 25 19:00:52 2013, giving +2
See http://review.coreboot.org/2501 for details.
-gerrit
the following patch was just integrated into master:
commit 4fc600442b578e3e79acb221040638ab52f600ed
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Mon Jan 21 18:43:12 2013 +0100
AMD Fam14 boards: Set P_BLK length to 6 for all processors
Currently on for example on AMD Persimmon and ASRock E350M1 Linux
complains, that the PBLK length is invalid [1].
ACPI: Invalid PBLK length [0]
Consequently, frequency scaling might not work correctly, though for
these two boards it seems to work according to PowerTOP.
Indeed, according to the ACPI specification [2], setting PBlockLength
to 0 is only allowed if there is no PBlockAddress. Otherwise it has to
be set to 6.
18.5.93 Processor (Declare Processor)
[…]
PBlockAddress provides the system I/O address for the processors
register block. Each processor can supply a different such
address. PBlockLength is the length of the processor register
block, in bytes and is either 0 (for no P_BLK) or 6. With one
exception, all processors are required to have the same
PBlockLength. The exception is that the boot processor can have
a non-zero PBlockLength when all other processors have a zero
PBlockLength. It is valid for every processor to have a
PBlockLength of 0.
And that is exactly what Linux is checking in
`drivers/acpi/processor_driver.c` [3].
static int acpi_processor_get_info(struct acpi_device *device)
{
[…]
/*
* On some boxes several processors use the same processor bus id.
* But they are located in different scope. For example:
* \_SB.SCK0.CPU0
* \_SB.SCK1.CPU0
* Rename the processor device bus id. And the new bus id will be
* generated as the following format:
* CPU+CPU ID.
*/
sprintf(acpi_device_bid(device), "CPU%X", pr->id);
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id,
pr->acpi_id));
if (!object.processor.pblk_address)
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n"));
else if (object.processor.pblk_length != 6)
printk(KERN_ERR PREFIX "Invalid PBLK length [%d]\n",
object.processor.pblk_length);
else {
pr->throttling.address = object.processor.pblk_address;
pr->throttling.duty_offset = acpi_gbl_FADT.duty_offset;
pr->throttling.duty_width = acpi_gbl_FADT.duty_width;
pr->pblk = object.processor.pblk_address;
/*
* We don't care about error returns - we just try to mark
* these reserved so that nobody else is confused into thinking
* that this region might be unused..
*
* (In particular, allocating the IO range for Cardbus)
*/
request_region(pr->throttling.address, 6, "ACPI CPU throttle");
}
[…]
}
This issue has proliferated to all AMD based boards so fix it for
all of them by setting P_BLK length to 6.
The DSDT of for example AMD Parmer and AMD Thatcher also set it
to 6 everywhere so this solution is taken instead of setting the
P_BLK system I/O base to 0 for all but the first processor which
is how it is done for earlier AMD based boards.
As note having to set this manually should not be needed and
this should be autogenerated as done for most of the Intel boards
and the AMD K8 based boards (`src/cpu/amd/model_fxx/powernow_acpi.c`).
[1] http://www.coreboot.org/pipermail/coreboot/2013-January/073636.html
[2] http://acpi.info/DOWNLOADS/ACPIspec40a.pdf
[3] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux.git;a=blob;f=drive…
Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
• ASRock E350M1:
Tested-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
• AMD Persimmon:
Tested-by: Martin Roth <martin.roth(a)se-eng.com>
Change-Id: Ie79fe4812532d124cc81747c75a4f3d88d00531c
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2189
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth(a)se-eng.com>
Build-Tested: build bot (Jenkins) at Fri Feb 22 23:16:09 2013, giving +1
See http://review.coreboot.org/2189 for details.
-gerrit
the following patch was just integrated into master:
commit a48918f75dda6f53ebdeb8c6371b6de6eb601205
Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de>
Date: Wed Feb 20 21:12:37 2013 +0100
Persimmon, Inagua: PCI devs 12.1, 13.1 (USB) don't exist, but 14.6 (GEC) does
USB ports 0-4 are handled by PCI devices 12.0 (OHCI) and 12.2 (EHCI). 12.1
simply does not exist, so remove it from devicetree.cb. While at it make the
comment more detailed. Likewise for all USB ports.
USB device 14.6 is the Broadcom GbE MAC integrated in the Hudson-E1. Add it
to devicetree.cb. It's used on Inagua (on), but not on Persimmon (off).
Change-Id: Idea27b3390fa4470f2592e79fdd633d5a218b97b
Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2463
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth(a)se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com>
Build-Tested: build bot (Jenkins) at Wed Feb 20 22:24:14 2013, giving +1
See http://review.coreboot.org/2463 for details.
-gerrit
Mike Loptien (mike.loptien(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2510
-gerrit
commit 2a14e8e643564d4762d81b6c0444037842f834d2
Author: Mike Loptien <mike.loptien(a)se-eng.com>
Date: Mon Feb 25 10:41:28 2013 -0700
AMD Southbridge: Add RTC init to lpc_init
Adding RTC init code to the Southbridge initialization
code in 'lpc_init'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same edit made to the CIMX SB800 titled
'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
ID: c4d3d which can be viewed here:
http://review.coreboot.org/#/c/2488/
Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
Signed-off-by: Mike Loptien <mike.loptien(a)se-eng.com>
---
src/southbridge/amd/agesa/hudson/lpc.c | 7 +++++++
src/southbridge/amd/cimx/sb700/late.c | 7 +++++++
src/southbridge/amd/cimx/sb900/late.c | 7 +++++++
3 files changed, 21 insertions(+)
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 86e937e..aad4eb9 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -69,6 +69,13 @@ static void lpc_init(device_t dev)
pci_write_config8(dev, 0xBB, byte);
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
}
static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index be2b8cd..4c5dde9 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -79,6 +79,13 @@ static void lpc_init(device_t dev)
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
+
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n");
}
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 85485ed..65cea69 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -101,6 +101,13 @@ static void lpc_init(device_t dev)
//- hpetInit(sb_config, &(sb_config->BuildParameters));
rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ /* Initialize the real time clock.
+ * The 0 argument tells rtc_init not to
+ * update CMOS unless it is invalid.
+ * 1 tells rtc_init to always initialize the CMOS.
+ */
+ rtc_init(0);
+
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
}
the following patch was just integrated into master:
commit 12d60247ab071e775cad6dc7fe78c2d7bc9bab45
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Thu Feb 21 15:54:50 2013 +0100
AMD boards: ACPI DSDT: Use COREBOOT for the OEM Table ID field
The DSDT header contains the fields OEMID and OEM Table ID. See
for example ACPI specification 4.0a [1]
5.2.11.1 Differentiated System Description Table (DSDT)
on page 135. There Table 5-16 contains the descriptions.
Field Byte Length Byte Offset Description
===================================================
OEMID 6 10 OEM ID
OEM Table ID 8 16 The manufacture model ID.
Currently in coreboot there is no common method what to put in
these fields.
Mostly Intel based boards populate it with "CORE " ore "COREv4"
and AMD based boards populate it with the board vendor and
model number, abbreviated appropriately to fit into these fields.
On most boards the proprietary vendor BIOS seems to leave these
fields – displayed with `sudo dmidecode` under System Information –
blank
To Be Filled By O.E.M.
and fill out the Base Board Information with the board vendor and
model name.
In [2] Jens Rottmann argues that the this is really just the table
ID used for naming it and that »99% of the DSDT code is not board
specific«.
Both approaches seem to have their advantages, but using the
second one, developers often seem to forget to update them (for
example AMD Thather).
The current situation is at least not optimal. and therefore at
least unify the string in the OEM Table ID. If unifying the
OEM ID is also a good idea this should be done too.
If later on it should be decided that the board vendor and model
should be used again, this should be somehow derived from
Kconfig.
The following command was used for the change [3].
$ git grep -l '\/\* TABLE ID \*\/' | xargs sed -i '/TABLE ID/s/"\([^"]*\)"/"COREBOOT"/'
This patch is split out from [2].
[1] http://www.acpi.info/spec40a.htm
[2] http://review.coreboot.org/#/c/2464/
[3] http://stackoverflow.com/questions/5207838/sed-regex-matching-text-between-…
Change-Id: Iec98c615ce37f928abc1b500eff5aa865d772cb2
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2472
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Build-Tested: build bot (Jenkins) at Thu Feb 21 17:01:23 2013, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 25 18:51:28 2013, giving +2
See http://review.coreboot.org/2472 for details.
-gerrit