coreboot February 2013

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New patch to review for coreboot: e4607d6 OT200: reset MFGTP7 (backlight pwm)
by Christian Gmeiner 26 Feb '13

26 Feb '13

Christian Gmeiner (christian.gmeiner(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2527 -gerrit commit e4607d6d5f494facca0ef59bfb3625abcbc0309c Author: Christian Gmeiner <christian.gmeiner(a)gmail.com> Date: Tue Feb 26 14:24:17 2013 +0100 OT200: reset MFGTP7 (backlight pwm) The CS5536 companion device has three different power domains. * working domain * standby domain * RTC domain When the system is "off" only the standby domain is powered. MFGPT[7:6] are member of the standby power domain. MFGPT7 is used to control the backlight of the device and so the timer gets used and configured during system boot. If the system does a reboot the timer stays configured and the Linux driver can not use it: "ot200-backlight: ot200-backlight.0: MFGPT 7 not availale" The cs5535-mfgpt has a function to hard-reset all MFGPTs but the system hangs after the first access to a MFGPT register - cause unknown. /* * This is a sledgehammer that resets all MFGPT timers. This is required by * some broken BIOSes which leave the system in an unstable state * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to * whether or not this secret MSR can be used to release individual timers. * Jordan tells me that he and Mitch once played w/ it, but it's unclear * what the results of that were (and they experienced some instability). */ static void reset_all_timers(void) { uint32_t val, dummy; /* The following undocumented bit resets the MFGPT timers */ val = 0xFF; dummy = 0; wrmsr(MSR_MFGPT_SETUP, val, dummy); } After playing around with this undocumented MSR it looks like I only need to set bit 7 to free the MFGPT7. BTW, all MFGPT[0:5] will be reset during pll_reset(). Change-Id: I54a8d479ce495b0fc2f54db766a8d793bbb5d704 Signed-off-by: Christian Gmeiner <christian.gmeiner(a)gmail.com> --- src/mainboard/bachmann/ot200/mainboard.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/bachmann/ot200/mainboard.c b/src/mainboard/bachmann/ot200/mainboard.c index f8aefec..ed70376 100644 --- a/src/mainboard/bachmann/ot200/mainboard.c +++ b/src/mainboard/bachmann/ot200/mainboard.c @@ -21,6 +21,7 @@ #include <device/smbus.h> #include <smbios.h> #include <console/console.h> +#include <cpu/x86/msr.h> /* overwrite a weak function to fill SMBIOS table with a custom value */ static u8 hw_rev = 0; @@ -43,6 +44,7 @@ static void init(struct device *dev) unsigned int i; u32 chksum = 0; char block[20]; + msr_t reset; device_t eeprom_dev = dev_find_slot_on_smbus(1, 0x52); if (eeprom_dev == 0) { @@ -63,6 +65,11 @@ static void init(struct device *dev) hw_rev = block[5]; printk(BIOS_DEBUG, "hw revision: %u\n", hw_rev); + + /* Reset MFGPT7 (standby power domain) */ + reset = rdmsr(0x5140002b); + reset.lo = 1 << 7; + wrmsr(0x5140002b, reset); } static void mainboard_enable(struct device *dev)

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New patch to review for coreboot: c06a8db AMD Inagua: buildOpts.c: Adapt whitespace to coding style
by Paul Menzel 26 Feb '13

26 Feb '13

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2526 -gerrit commit c06a8dbe76089d6e2f3d4c76ba074c04da21358d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 25 14:58:23 2013 +0100 AMD Inagua: buildOpts.c: Adapt whitespace to coding style Mainly replace spaces by tabs and format comments correctly. Commit »Inagua: Indent and wihtespace cleanup« (f03360f3) [1] was unfortunately incomplete and also used spaces instead of tabs in some cases. Hopefully fix this once and for all to have a template for the others boards. [1] http://review.coreboot.org/547 Change-Id: If15c797581dfefe2a57cd6f26e5bdac4cdd014dd Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/amd/inagua/buildOpts.c | 374 +++++++++++++++++------------------ 1 file changed, 187 insertions(+), 187 deletions(-) diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 49eb7bf..e310f83 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -37,23 +37,23 @@ #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE -/* Select the cpu family. */ -#define INSTALL_FAMILY_10_SUPPORT FALSE -#define INSTALL_FAMILY_12_SUPPORT FALSE -#define INSTALL_FAMILY_14_SUPPORT TRUE -#define INSTALL_FAMILY_15_SUPPORT FALSE - -/* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT FALSE -#define INSTALL_C32_SOCKET_SUPPORT FALSE -#define INSTALL_S1G3_SOCKET_SUPPORT FALSE -#define INSTALL_S1G4_SOCKET_SUPPORT FALSE -#define INSTALL_ASB2_SOCKET_SUPPORT FALSE -#define INSTALL_FS1_SOCKET_SUPPORT FALSE -#define INSTALL_FM1_SOCKET_SUPPORT FALSE -#define INSTALL_FP1_SOCKET_SUPPORT FALSE -#define INSTALL_FT1_SOCKET_SUPPORT TRUE -#define INSTALL_AM3_SOCKET_SUPPORT FALSE +/* Select the cpu family. */ +#define INSTALL_FAMILY_10_SUPPORT FALSE +#define INSTALL_FAMILY_12_SUPPORT FALSE +#define INSTALL_FAMILY_14_SUPPORT TRUE +#define INSTALL_FAMILY_15_SUPPORT FALSE + +/* Select the cpu socket type. */ +#define INSTALL_G34_SOCKET_SUPPORT FALSE +#define INSTALL_C32_SOCKET_SUPPORT FALSE +#define INSTALL_S1G3_SOCKET_SUPPORT FALSE +#define INSTALL_S1G4_SOCKET_SUPPORT FALSE +#define INSTALL_ASB2_SOCKET_SUPPORT FALSE +#define INSTALL_FS1_SOCKET_SUPPORT FALSE +#define INSTALL_FM1_SOCKET_SUPPORT FALSE +#define INSTALL_FP1_SOCKET_SUPPORT FALSE +#define INSTALL_FT1_SOCKET_SUPPORT TRUE +#define INSTALL_AM3_SOCKET_SUPPORT FALSE /* * Agesa optional capabilities selection. @@ -61,163 +61,163 @@ * Comment out or mark TRUE those features you want to REMOVE from the build. */ -#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE -#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE -#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE - -#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE -#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE - -#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE -#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE -#define BLDOPT_REMOVE_ECC_SUPPORT FALSE -//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE -#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE -#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE -#define BLDOPT_REMOVE_DQS_TRAINING FALSE -#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE -#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE -#define BLDOPT_REMOVE_ACPI_PSTATES FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE -#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE -#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE -#define BLDOPT_REMOVE_SRAT FALSE -#define BLDOPT_REMOVE_SLIT FALSE -#define BLDOPT_REMOVE_WHEA FALSE -#define BLDOPT_REMOVE_DMI TRUE -#define BLDOPT_REMOVE_HT_ASSIST TRUE -#define BLDOPT_REMOVE_ATM_MODE TRUE -//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE -//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE -#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE -//#define BLDOPT_REMOVE_C6_STATE TRUE -#define BLDOPT_REMOVE_GFX_RECOVERY TRUE -#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE +#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE +#define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE +#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE + +#define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE +#define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE + +#define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +#define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE +#define BLDOPT_REMOVE_ECC_SUPPORT FALSE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +#define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE +#define BLDOPT_REMOVE_DQS_TRAINING FALSE +#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +#define BLDOPT_REMOVE_ACPI_PSTATES FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE +#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE +#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE +#define BLDOPT_REMOVE_SRAT FALSE +#define BLDOPT_REMOVE_SLIT FALSE +#define BLDOPT_REMOVE_WHEA FALSE +#define BLDOPT_REMOVE_DMI TRUE +#define BLDOPT_REMOVE_HT_ASSIST TRUE +#define BLDOPT_REMOVE_ATM_MODE TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE +//#define BLDOPT_REMOVE_C6_STATE TRUE +#define BLDOPT_REMOVE_GFX_RECOVERY TRUE +#define BLDOPT_REMOVE_EARLY_SAMPLES TRUE /* * Agesa entry points used in this implementation. */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE - -#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS -#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER - -#define BLDCFG_VRM_CURRENT_LIMIT 24000 -//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 -#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 -#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 -#define BLDCFG_VRM_SLEW_RATE 5000 -//#define BLDCFG_VRM_NB_SLEW_RATE 5000 -//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 -//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 -#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE -//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE -#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 -//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 - -//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' -//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' -//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE -#define BLDCFG_PLAT_NUM_IO_APICS 3 -//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled -//#define BLDCFG_PLATFORM_C1E_OPDATA 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 -//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 -#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 -#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 -#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 -//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto -#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST -#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList -#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -//#define BLDCFG_STARTING_BUSNUM 0 -//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 -//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 -//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 -//#define BLDCFG_BUID_SWAP_LIST 0 -//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 -//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 -//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 -//#define BLDCFG_BUS_NUMBERS_LIST 0 -//#define BLDCFG_IGNORE_LINK_LIST 0 -//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 -//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 -//#define BLDCFG_USE_HT_ASSIST TRUE -//#define BLDCFG_USE_ATM_MODE TRUE -//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm -#define BLDCFG_S3_LATE_RESTORE FALSE -//#define BLDCFG_USE_32_BYTE_REFRESH FALSE -//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE -//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance -//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE -//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE -//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 -#define BLDCFG_CFG_GNB_HD_AUDIO TRUE -//#define BLDCFG_CFG_ABM_SUPPORT FALSE -//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 -//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 -//#define BLDCFG_MEM_INIT_PSTATE 0 -//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY -#define BLDCFG_MEMORY_MODE_UNGANGED TRUE -//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE -//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE -#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE -#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_POWER_DOWN TRUE -#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT -//#define BLDCFG_ONLINE_SPARE FALSE -//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE -#define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY -#define BLDCFG_DQS_TRAINING_CONTROL TRUE -#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE -#define BLDCFG_USE_BURST_MODE FALSE -#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE -//#define BLDCFG_ENABLE_ECC_FEATURE TRUE -//#define BLDCFG_ECC_REDIRECTION FALSE -//#define BLDCFG_SCRUB_DRAM_RATE 0 -//#define BLDCFG_SCRUB_L2_RATE 0 -//#define BLDCFG_SCRUB_L3_RATE 0 -//#define BLDCFG_SCRUB_IC_RATE 0 -//#define BLDCFG_SCRUB_DC_RATE 0 -//#define BLDCFG_ECC_SYNC_FLOOD 0 -//#define BLDCFG_ECC_SYMBOL_SIZE 0 -//#define BLDCFG_1GB_ALIGN FALSE -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO -#define BLDCFG_UMA_ALLOCATION_SIZE 0 -#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE -#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED -#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 -#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +#define BLDCFG_VRM_CURRENT_LIMIT 24000 +//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000 +#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 +#define BLDCFG_VRM_SLEW_RATE 5000 +//#define BLDCFG_VRM_NB_SLEW_RATE 5000 +//#define BLDCFG_VRM_ADDITIONAL_DELAY 0 +//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 +#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE +//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000 +//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 + +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +//#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE +#define BLDCFG_PLAT_NUM_IO_APICS 3 +//#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled +//#define BLDCFG_PLATFORM_C1E_OPDATA 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 +#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 +#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840 +#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840 +//#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE +//#define BLDCFG_STARTING_BUSNUM 0 +//#define BLDCFG_MAXIMUM_BUSNUM 0xf8 +//#define BLDCFG_ALLOCATED_BUSNUMS 0x20 +//#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0 +//#define BLDCFG_BUID_SWAP_LIST 0 +//#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0 +//#define BLDCFG_HTFABRIC_LIMITS_LIST 0 +//#define BLDCFG_HTCHAIN_LIMITS_LIST 0 +//#define BLDCFG_BUS_NUMBERS_LIST 0 +//#define BLDCFG_IGNORE_LINK_LIST 0 +//#define BLDCFG_LINK_SKIP_REGANG_LIST 0 +//#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0 +//#define BLDCFG_USE_HT_ASSIST TRUE +//#define BLDCFG_USE_ATM_MODE TRUE +//#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm +#define BLDCFG_S3_LATE_RESTORE FALSE +//#define BLDCFG_USE_32_BYTE_REFRESH FALSE +//#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE +//#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance +//#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE +//#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0 +#define BLDCFG_CFG_GNB_HD_AUDIO TRUE +//#define BLDCFG_CFG_ABM_SUPPORT FALSE +//#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0 +//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0 +//#define BLDCFG_MEM_INIT_PSTATE 0 +//#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +//#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +//#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_POWER_DOWN TRUE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT +//#define BLDCFG_ONLINE_SPARE FALSE +//#define BLDCFG_MEMORY_PARITY_ENABLE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE +//#define BLDCFG_ENABLE_ECC_FEATURE TRUE +//#define BLDCFG_ECC_REDIRECTION FALSE +//#define BLDCFG_SCRUB_DRAM_RATE 0 +//#define BLDCFG_SCRUB_L2_RATE 0 +//#define BLDCFG_SCRUB_L3_RATE 0 +//#define BLDCFG_SCRUB_IC_RATE 0 +//#define BLDCFG_SCRUB_DC_RATE 0 +//#define BLDCFG_ECC_SYNC_FLOOD 0 +//#define BLDCFG_ECC_SYMBOL_SIZE 0 +//#define BLDCFG_1GB_ALIGN FALSE +#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_SIZE 0 +#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE +#define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 /* * Agesa configuration values selection. @@ -259,7 +259,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "GnbInterface.h" /***************************************************************************** - * Define the RELEASE VERSION string + * Define the RELEASE VERSION string * * The Release Version string should identify the next planned release. * When a branch is made in preparation for a release, the release manager @@ -288,7 +288,7 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #define DDR1333_FREQUENCY 667 ///< DDR 1333 #define DDR1600_FREQUENCY 800 ///< DDR 1600 #define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE*/ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM @@ -297,22 +297,22 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = /* USER_MEMORY_TIMING_MODE */ #define TIMING_MODE_AUTO 0 ///< Use best rate possible #define TIMING_MODE_LIMITED 1 ///< Set user top limit -#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed /* POWER_DOWN_MODE */ -#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode -#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product // and BKDG content, please consult the AGESA Memory team for consultation. -#define DFLT_SCRUB_DRAM_RATE (0) -#define DFLT_SCRUB_L2_RATE (0) -#define DFLT_SCRUB_L3_RATE (0) -#define DFLT_SCRUB_IC_RATE (0) -#define DFLT_SCRUB_DC_RATE (0) -#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED -#define DFLT_VRM_SLEW_RATE (5000) +#define DFLT_SCRUB_DRAM_RATE (0) +#define DFLT_SCRUB_L2_RATE (0) +#define DFLT_SCRUB_L3_RATE (0) +#define DFLT_SCRUB_IC_RATE (0) +#define DFLT_SCRUB_DC_RATE (0) +#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED +#define DFLT_VRM_SLEW_RATE (5000) // Instantiate all solution relevant data. #include "PlatformInstall.h" @@ -323,10 +323,10 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = */ /* - * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA - * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable - * is populated, AGESA will base its settings on the data from the table. Otherwise, it will - * use its default conservative settings. + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. */ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { // @@ -396,7 +396,7 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { #include "mm.h" #include "mn.h" -//DA Customer table +// DA Customer table CONST UINT8 AGESA_MEM_TABLE_ON[][sizeof (MEM_TABLE_ALIAS)] = { // Hardcoded Memory Training Values

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New patch to review for coreboot: 1d78246 Fix socket LGA775
by Kyösti Mälkki 26 Feb '13

26 Feb '13

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2525 -gerrit commit 1d7824607872837714e340631a26a25c0f159434 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 26 13:49:56 2013 +0200 Fix socket LGA775 Models 6ex and 6fx select UDELAY_LAPIC so cannot select contradicting UDELAY_TSC here. Model 1067x requires speedstep. Change-Id: I69d3ec8085912dfbe5fe31c81fa0a437228fa48f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/socket_LGA775/Kconfig | 1 - src/cpu/intel/socket_LGA775/Makefile.inc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index dfb3181..e5c687a 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -14,7 +14,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy select CPU_INTEL_MODEL_1067X select MMX select SSE - select UDELAY_TSC select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 100b4d8..ea68ab1 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,5 +13,6 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +subdirs-y += ../speedstep cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc

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Patch set updated for coreboot: 2cb3675 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio
by Jens Rottmann 26 Feb '13

26 Feb '13

Jens Rottmann (JRottmann(a)LiPPERTembedded.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2454 -gerrit commit 2cb3675e5f92acea85a3c1d75bf4f30693d18370 Author: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> Date: Tue Feb 19 15:01:06 2013 +0100 AMD SB800: don't switch clock from 14 to 48 MHz for smscsuperio The power up default for the 14M_25M_48M_OSC switchable clock output ball of the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz, which is the correct value for almost all SIOs. However, not for 'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not configurable for other clock speeds. A wrong SIO clock supply results in funny RS232 output (wrong bit speed) and non-working PS/2. We could switch back to 14 MHz in the mainboard's romstage.c, but then the clock frequency would change twice. The resulting short 48 MHz burst causes a handful of rubbish characters on RS232 on every boot until the SIO clock has stabilized again. This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz. This does not affect any boards currently in the repository (yet). Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4 Signed-off-by: Jens Rottmann <JRottmann(a)LiPPERTembedded.de> --- src/southbridge/amd/cimx/sb800/bootblock.c | 13 ++++++++++--- src/superio/Kconfig | 3 +++ src/superio/smsc/Kconfig | 1 + 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 0a339b0..030ddc6 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -97,10 +97,17 @@ static void enable_clocks(void) reg8 &= ~(1 << 1); outb(reg8, 0xCD7); - // Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz) + // Program SB800 MiscClkCntrl register to configure clock output on the + // 14M_25M_48M_OSC ball usually used for the Super-I/O. + // Almost all SIOs need 48 MHz, only the SMSC SCH311x wants 14 MHz, + // which is the SB800's power up default. We could switch back to 14 + // in the mainboard's romstage.c, but then the clock frequency would + // change twice. reg32 = *acpi_mmio; - reg32 &= ~((1 << 0) | (1 << 2)); - reg32 |= 1 << 1; + reg32 &= ~((1 << 2) | (3 << 0)); // enable, 14 MHz (power up default) +#if !CONFIG_SUPERIO_WANTS_14MHZ_CLOCK + reg32 |= 2 << 0; // Device_CLK1_sel = 48 MHz +#endif *acpi_mmio = reg32; } diff --git a/src/superio/Kconfig b/src/superio/Kconfig index 00fee97..d0ca249 100644 --- a/src/superio/Kconfig +++ b/src/superio/Kconfig @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +config SUPERIO_WANTS_14MHZ_CLOCK + bool + source src/superio/fintek/Kconfig source src/superio/intel/Kconfig source src/superio/ite/Kconfig diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 8d66fc5..1a3b709 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -44,6 +44,7 @@ config SUPERIO_SMSC_MEC1308 bool config SUPERIO_SMSC_SMSCSUPERIO bool + select SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_SIO1036 bool config SUPERIO_SMSC_SCH4037

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Patch set updated for coreboot: 5ffb6d6 documentation: Complete the AMD-S3.txt
by Zheng Bao 26 Feb '13

26 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2483 -gerrit commit 5ffb6d6e4cadd548cfd9017a48a1d40f216e570e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Feb 26 18:10:52 2013 +0800 documentation: Complete the AMD-S3.txt Fix some typos and finish empty sections. Change-Id: I08cc971e763252b035ab8ed2118180140e34ac72 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- documentation/AMD-S3.txt | 37 +++++++++++++++++++++++++++++++------ 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt index 1ef87c0..48d4c8f 100644 --- a/documentation/AMD-S3.txt +++ b/documentation/AMD-S3.txt @@ -13,7 +13,7 @@ /_/ \_\_| |_|_____/ |_____/ |____/ - S3 in Coreboot (V 1.1) + S3 in Coreboot (V 1.2) ---------------------------------------- Zheng Bao <zheng.bao(a)amd.com> @@ -22,7 +22,7 @@ Introduction ============ This document is about how the feature S3 is implemented on coreboot, -specificly on AMD platform. This topic deals with ACPI spec, hardware, +specifically on AMD platform. This topic deals with ACPI spec, hardware, BIOS, OS. We try to help coreboot users to realize their own S3. S3 in a nutshell @@ -103,20 +103,45 @@ Lifecycle of booting, sleeping and waking Coreboot and Ubuntu ============================================================= 1. Cold boot. For a system with S3 feature, the BIOS needs to save some data to -non-volitile storage at cold boot stage. What data need to be save are +non-volatile storage at cold boot stage. What data need to be save are provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets the VolatileStorage and NvStorage, which are where the data are located. It is the wrappers's responsibility to save the data.[3][4] -Currently, the wrappers allocate a CBFS modules in BIOS image. Todo +Currently, the wrappers allocate a CBFS modules in BIOS image. To do that, the wrapper needs to have the ability to write flash chips. It is not as comprehensive as flashrom. But for the SST chip on Parmer, MX chip on Thather, coreboot works well.[5] 2. OS goes in S3. - -3. BIOS detect S3 wakeup +For Linux, besides the kernel needs to do some saving, most distributions +run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d. + # ls /usr/lib/pm-utils/sleep.d + 000kernel-change 49bluetooth 90clock 95led + 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler + 00powersave 60_wpa_supplicant 95anacron 99video + 01PulseAudio 75modules 95hdparm-apm +The script with lower prefix runs before the one with higher prefix. +99video is the last one. +Those scripts have hooks called hibernate, suspend, thaw, resume. For +each script, suspend is called when system sleeps and wakeup is called +when system wakeups. + +3. Firmware detects S3 wakeup +As we mentioned, Firmware detects the SLP_TYPx to find out if the board +wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called +as they are during cold boot. AmdInitResume and AmdS3LateRestore are +called only during resume. For whole ramstage, Coreboot goes through +almost the same way as cold boot, other than not calling the AmdInitMid, +AmdInitLate and AmdS3Save, and restoring all the MTRRs. +At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, +written by OS, and jump. 4. OS resumes. +When Linux resumes, all the sleeping scripts call their resume +hooks. If we are more lucky, all the scripts can go through. More +chances that the 99video hangs or fails to get the display +back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is unset in +Coreboot/Kconfig. That needs more troubleshooting. Reference

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Patch set updated for coreboot: 61f0d1c documentation: Complete the AMD-S3.txt
by Zheng Bao 26 Feb '13

26 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2483 -gerrit commit 61f0d1cf8c817c587df52f17c77be02a4684db90 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Feb 26 16:20:11 2013 +0800 documentation: Complete the AMD-S3.txt Fix some typos and finish empty sections. Change-Id: I08cc971e763252b035ab8ed2118180140e34ac72 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- documentation/AMD-S3.txt | 33 +++++++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/documentation/AMD-S3.txt b/documentation/AMD-S3.txt index 1ef87c0..14f444a 100644 --- a/documentation/AMD-S3.txt +++ b/documentation/AMD-S3.txt @@ -13,7 +13,7 @@ /_/ \_\_| |_|_____/ |_____/ |____/ - S3 in Coreboot (V 1.1) + S3 in Coreboot (V 1.2) ---------------------------------------- Zheng Bao <zheng.bao(a)amd.com> @@ -22,7 +22,7 @@ Introduction ============ This document is about how the feature S3 is implemented on coreboot, -specificly on AMD platform. This topic deals with ACPI spec, hardware, +specifically on AMD platform. This topic deals with ACPI spec, hardware, BIOS, OS. We try to help coreboot users to realize their own S3. S3 in a nutshell @@ -103,20 +103,41 @@ Lifecycle of booting, sleeping and waking Coreboot and Ubuntu ============================================================= 1. Cold boot. For a system with S3 feature, the BIOS needs to save some data to -non-volitile storage at cold boot stage. What data need to be save are +non-volatile storage at cold boot stage. What data need to be save are provided by AmdS3Save. After the wrapper calls the AmdS3Save, it gets the VolatileStorage and NvStorage, which are where the data are located. It is the wrappers's responsibility to save the data.[3][4] -Currently, the wrappers allocate a CBFS modules in BIOS image. Todo +Currently, the wrappers allocate a CBFS modules in BIOS image. To do that, the wrapper needs to have the ability to write flash chips. It is not as comprehensive as flashrom. But for the SST chip on Parmer, MX chip on Thather, coreboot works well.[5] 2. OS goes in S3. - -3. BIOS detect S3 wakeup +For Linux, besides the kernel needs to do some saving, most distributions +run some scripts. For Ubuntu, scripts are located at /usr/lib/pm-utils/sleep.d. + # ls /usr/lib/pm-utils/sleep.d + 000kernel-change 49bluetooth 90clock 95led + 00logging 55NetworkManager 94cpufreq 98video-quirk-db-handler + 00powersave 60_wpa_supplicant 95anacron 99video + 01PulseAudio 75modules 95hdparm-apm +The script with lower prefix runs before the one with higher prefix. +99video is the last one. + +3. Firmware detects S3 wakeup +As we mentioned, Firmware detects the SLP_TYPx to find out if the board +wakes up. In romstage.c, AmdInitReset and AmdInitEarly are called +as they are during cold boot. AmdInitResume and AmdS3LateRestore are +called only during resume. For whole ramstage, Coreboot goes through +almost the same way as cold boot, other than not calling the AmdInitMid, +AmdInitLate and AmdS3Save, and restoring all the MTRRs. +At last step of coreboot stage, coreboot finds out the wakeup vector in FADT, +written by OS, and jump. 4. OS resumes. +When Linux resume, all the sleeping scripts continues. If we are more lucky, +all the scripts can go through. More chances that the 99video hangs or fails +to get the display back. Sometimes it can fixed if CONFIG_S3_VGA_ROM_RUN is +unset in Coreboot/Kconfig. That needs more troubleshooting. Reference

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New patch to review for coreboot: 281a6b1 gitconfig: Give up commiting when non-ascii character is in commit message.
by Zheng Bao 26 Feb '13

26 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2524 -gerrit commit 281a6b1b4bd4257044d436b5a714379677717b5e Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Feb 26 14:48:57 2013 +0800 gitconfig: Give up commiting when non-ascii character is in commit message. ' ' is 0x20, '~' is 0x7E. The character not between ' ' and '~' could be treated as non-ascii one, which makes the project less global. Change-Id: If0bbc4bb6b1f8a0d123d00e2b8e6b29cc78abda0 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/gitconfig/commit-msg | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 1a4e865..c1e1893 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -37,6 +37,12 @@ add_ChangeId() { exit 1 fi + if LANG= grep '[^ -~]' "$MSG" > /dev/null + then + echo "Aborting commit due to non-ascii characters in commit message." + exit 1 + fi + # Does Change-Id: already exist? if so, exit (no change). if grep -i '^Change-Id: I[0-9a-f]\{40\}$' "$MSG" >/dev/null then

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New patch to review for coreboot: 5b7b02b gitconfig: Give up commiting if the commit message is empty.
by Zheng Bao 26 Feb '13

26 Feb '13

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2523 -gerrit commit 5b7b02b81c02e952af11fe958a5529df5529fd10 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Tue Feb 26 14:40:35 2013 +0800 gitconfig: Give up commiting if the commit message is empty. With or without this change, git itself gives up commiting and prints the same error message. This just makes the commit-msg take more responsible. It also helps us how to give up commiting. Change-Id: I8b6e9eb258dde43776a4d55b4d198b2cc42535f0 Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/gitconfig/commit-msg | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/gitconfig/commit-msg b/util/gitconfig/commit-msg index 82f0581..1a4e865 100755 --- a/util/gitconfig/commit-msg +++ b/util/gitconfig/commit-msg @@ -33,7 +33,8 @@ add_ChangeId() { ' "$MSG" | git stripspace` if test -z "$clean_message" then - return + echo "Aborting commit due to empty commit message." + exit 1 fi # Does Change-Id: already exist? if so, exit (no change).

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Patch merged into coreboot/master: 37ef52d libpayload: Correct a constant used for scanning for USB controllers.
by gerrit＠coreboot.org 26 Feb '13

26 Feb '13

the following patch was just integrated into master: commit 37ef52d44b3d527d6a4fb84eaffa4260b7521d4a Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 21 01:52:27 2012 -0800 libpayload: Correct a constant used for scanning for USB controllers. When checking to see if a PCI device exists at a particular bus/dev/func, libpayload was checking the vendor and device id fields together against a 16 bit 0xffff. The two fields together are 32 bits, however, so the check was never true, and all dev/func combinations on a particular bus would be checked. That was slightly wasteful, but had relatively small impact. Change-Id: Iad537295c33083243940b18e7a99af92857e1ef2 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2521 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 26 02:35:54 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Feb 26 07:39:06 2013, giving +2 See http://review.coreboot.org/2521 for details. -gerrit

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Patch merged into coreboot/master: b4523bb libpayload: Change the measurement interval for get_cpu_speed to 2 ms.
by gerrit＠coreboot.org 26 Feb '13

26 Feb '13

the following patch was just integrated into master: commit b4523bb691037f78a0823299ef44c0e350e17759 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 21 01:01:50 2012 -0800 libpayload: Change the measurement interval for get_cpu_speed to 2 ms. The interval used to be about 55 ms which is excessively long. Coreboot only waits for 2 ms and gets a reasonable answer. That should be good enough for us as well. Change-Id: I4d4e8b25b6ba540c9e9839ed0bbaa1f04f67cce1 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: http://review.coreboot.org/2520 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 26 02:27:48 2013, giving +1 Reviewed-By: Anton Kochkov <anton.kochkov(a)gmail.com> at Tue Feb 26 07:37:15 2013, giving +2 See http://review.coreboot.org/2520 for details. -gerrit

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coreboot February 2013