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[coreboot - Bug #121] T520: Hangs in OS
by Anastasios Koutian 16 Mar '24

16 Mar '24

Issue #121 has been updated by Anastasios Koutian. Anastasios Koutian wrote in #note-86: > Martin Zwicknagl wrote in #note-46: > > Hello, > > > > I can report, that I had NO freezes for a month now. > > > > During a RAM upgrade to 16GB I have replaced one 2GB Samsung SODIMM (2GB 1Rx8 PC3-10600s-09-10-ZZZ, M471B5773CHS-CH9 1149) > > with a SODIMM [Crucial CT102464BF160B 8GB Speicher (DDR3L, 1600 MT/s, PC3L-12800, SODIMM, 204-Pin)]. > > The laptop is now using two identical Crucial SODIMMs. > > > > The problem is gone. I do not need any ``intel_idle.max_cstate`` tricks anymore. My T520 is using all cores, hyperthreading, all cstates (and turbo boost). > > > > I think ticket 178 is also solved. Who can close 178? > > > > Cheeers > > Martin > > Hello all, > > I installed the exact same SODIMMs (Crucial CT102464BF160B) as the message quoted above and achieved four days continuous uptime with no issues. > I eventually had to reboot due to a necessary update, so it might be a premature conclusion. I will keep the system running for as long as I can to confirm. > > I haven't gotten around to comparing with MSRs on stock firmware yet, but will once I have spare time. After testing for two weeks, it became clear that the problem is still present, but with different symptoms: the system freezes for a short time and then reboots. Previously, it would freeze indefinitely. ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1794 * Author: Firstname Lastname * Status: In Progress * Priority: Normal * Category: chipset configuration * Start date: 2017-06-09 * Affected hardware: SNB, IVY * Affected OS: - ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) defconfig (699 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #327] MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR
by Joel Linn 16 Mar '24

16 Mar '24

Issue #327 has been updated by Joel Linn. Works, setting 0x400 also boots the Win11 PE environment that BSODs with 0x2000 ---------------------------------------- Bug #327: MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR https://ticket.coreboot.org/issues/327#change-1793 * Author: xinhua wang * Status: New * Priority: Normal * Start date: 2021-12-30 ---------------------------------------- https://review.coreboot.org/c/coreboot/+/27711/7/src/drivers/intel/gma/acpi… this line .. OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) the 0x2000 will cause BSOD ACPI_BIOS_ERROR when booting installer, os, etc When set to 0x1000 windows UEFI tianocore mode boots fine ---Files-------------------------------- dmesg.txt (76.9 KB) results.log (204 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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v24.02.01: error creating smc biosinfo
by Christoph Zechner 16 Mar '24

16 Mar '24

Hi, while building coreboot for a LGA1151 board, we encountered the following error: TOOL Creating SMC BIOSINFO metadata E: Unsupported coreboot minor version E: Error creating 'build/mainboard/supermicro/x11-lga1151-series/smcbiosinfo.bin' make: *** [util/supermicro/Makefile.mk:22: build/mainboard/supermicro/x11-lga1151-series/smcbiosinfo.bin] Error 1 content of build/build.h: ... #define COREBOOT_ORIGIN_GIT_REVISION "Unknown" #define COREBOOT_EXTRA_VERSION "" #define COREBOOT_MAJOR_VERSION 24 #define COREBOOT_MINOR_VERSION 202 ... content of.coreboot-version: 24.02.01-0a280ff747 Find a patch attached that fixes parsing the minor version in genbuild_h.sh. Best regards Christoph Zechner

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[coreboot - Bug #327] MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR
by Patrick Rudolph 16 Mar '24

16 Mar '24

Issue #327 has been updated by Patrick Rudolph. Please test https://review.coreboot.org/c/coreboot/+/81295 In case this doesn't fix the problem please attach to windows kernel using windbg and provide more details about the failing code. ---------------------------------------- Bug #327: MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR https://ticket.coreboot.org/issues/327#change-1792 * Author: xinhua wang * Status: New * Priority: Normal * Start date: 2021-12-30 ---------------------------------------- https://review.coreboot.org/c/coreboot/+/27711/7/src/drivers/intel/gma/acpi… this line .. OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) the 0x2000 will cause BSOD ACPI_BIOS_ERROR when booting installer, os, etc When set to 0x1000 windows UEFI tianocore mode boots fine ---Files-------------------------------- dmesg.txt (76.9 KB) results.log (204 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #327] MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR
by Patrick Rudolph 16 Mar '24

16 Mar '24

Issue #327 has been updated by Patrick Rudolph. It looks like 0x2000 is the correct size for the total opregion (MBOX1-MBOX5). Since ACPI only uses MBOX3, the size should be reduced to 0x400. ---------------------------------------- Bug #327: MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR https://ticket.coreboot.org/issues/327#change-1791 * Author: xinhua wang * Status: New * Priority: Normal * Start date: 2021-12-30 ---------------------------------------- https://review.coreboot.org/c/coreboot/+/27711/7/src/drivers/intel/gma/acpi… this line .. OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) the 0x2000 will cause BSOD ACPI_BIOS_ERROR when booting installer, os, etc When set to 0x1000 windows UEFI tianocore mode boots fine ---Files-------------------------------- dmesg.txt (76.9 KB) results.log (204 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #327] MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR
by Joel Linn 16 Mar '24

16 Mar '24

Issue #327 has been updated by Joel Linn. I can also confirm this, I get *ACPI_BIOS_ERROR 0x1000 0x0 0x0 0x2000* and applying the mentioned change does the trick for me. Sandy Bridge H61 Express i3-3220, no secondary GPU, libgfxinit ---------------------------------------- Bug #327: MBOX3, OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes windows uefi tianocore BSOD ACPI_BIOS_ERROR https://ticket.coreboot.org/issues/327#change-1790 * Author: xinhua wang * Status: New * Priority: Normal * Start date: 2021-12-30 ---------------------------------------- https://review.coreboot.org/c/coreboot/+/27711/7/src/drivers/intel/gma/acpi… this line .. OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) the 0x2000 will cause BSOD ACPI_BIOS_ERROR when booting installer, os, etc When set to 0x1000 windows UEFI tianocore mode boots fine ---Files-------------------------------- dmesg.txt (76.9 KB) results.log (204 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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The coreboot master branch has been deleted
by Martin Roth 13 Mar '24

13 Mar '24

Hello All, It's been mentioned a few times previously that we were going to delete the master branch after switching the default branch to 'main'. This process is now completed - the master branch is gone. One positive of this is that people can no longer push patches to the master branch in confusion, however anyone who hasn't updated scripts or git pointers in the past 6 months is now going to see failures. This could absolutely include the coreboot project as well. We've recently found settings that were still pointing at the master branch. If you see any oddness or issues that could be related to the master branch, please let the admins or leadership know. Thanks much. Martin

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GRUB2_SECONDARY_PAYLOAD: max possible module set + unavailable modules
by Mike Banon 10 Mar '24

10 Mar '24

Good day! I am trying to ensure the best feature set for a GRUB2 secondary payload of SeaBIOS. First of all, I checked what GRUB2 modules I have in a fully-updated Artix (arch without systemd) installation: ls -al /boot/grub/i386-pc/ | cut -c44- | awk '{ print substr( $0, 1, length($0)-4 ) }' | tr '\n' ' ' Then I tried using this list as a value for CONFIG_GRUB2_EXTRA_MODULES (could not set it with 'make menuconfig' because it was way too long, so had to edit a ./coreboot/.config manually) - but for some reason not all GRUB2 modules are available: while trying to build, I constantly got the errors like: ... config.status: creating grub ./grub-mkstandalone: error: cannot open `grub-core//pxechain.mod': No such file or directory. make[2]: *** [Makefile:15040: default_payload.elf] Error 1 make[1]: *** [Makefile:45: grub2] Error 2 make: *** [payloads/external/Makefile.mk:276: grub2] Error 2 - and had to remove the "missing modules" from this variable one-by-one. Eventually I got the max possible GRUB2 module set - please see attachments (without any modules at all, img/grub2 occupies 472 KB at CBFS; with all these modules - 710 KB). However, what worries me is why these modules are unavailable at coreboot+SeaBIOS version of GRUB2 : biosdisk bufio cacheinfo cbtable command core drivemap font freedos fs gfxterm legacycfg legacy_password_test load lsapm moddep modinf ntldr partmap plan9 pxechain pxe sendkey truecrypt vbe vga vga_text video_fb video Some of those missing ones could be valuable - like a truecrypt module... Do you know why they are missing and how to debug this? -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

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looking for someone to help on coreboot port to visionfive2 board
by ron minnich 07 Mar '24

07 Mar '24

during a recent RISE meeting, I conveyed the good news that Max and 9elements had released the SiFive unmatched port and it was upstreamed! That was great. People seemed interested. Next request: Starfive visionfive2. Now, we do have an oreboot port, so there is a code base to reference. If somebody would like to look at getting this board ported, it would be a big help.

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2024-03-06 - coreboot Leadership Meeting minutes
by mina＠coreboot.org 07 Mar '24

07 Mar '24

# 2024-03-06 - coreboot Leadership Meeting minutes ## Announcement: OSFF ByteTalks - [https://osfw.foundation/events/bytetalks-vol.-1/]. OSFC will be in Bochum Germany - September 3-5 - [https://www.osfc.io/]. ## Attendees: Martin Roth, Mina Asante, Julius Werner, Daniel Maslowski, Jonathan Hall, Matt Devillier, Nicholas Chin, Nico Huber, Jay Talbott, Felix Singer, Werner Zeh, Marshall Dawson, Felix Held, David Hendricks, Jules Irenge, Max Brune. ## Open Action Items * 2024-03-06 * [Open] Martin: To update documentation on gerrit contributing guidelines. * https://doc.coreboot.org/contributing/index.html * 2024-01-10 * [Open] Werner: Push patch based on https://ticket.coreboot.org/issues/522 * Nico: https://review.coreboot.org/q/topic:enforce_region_api * Open Daniel: Look at how we want to localize (non console) strings for coreboot. Long term project. ## Minutes ### [Martin] -1 should be a privilege for coreboot reviewers along with +2 rights. * Since 2016, all registered users have had -1 rights. Back then, we didn’t block on unresolved comments, so giving a -1 was the only good way to get attention for an issue. This is no longer the case, and I feel that we should go back to having -1 rights be one of the privileges given to contributors. * There’s no incident - We just don’t need to give -1 to every registered user anymore. This has been superseded by making people address all open patches. * Current status: * Registered users: -1 to +1 * Developers: -1 to +2 * Core developers: -2 to +2 * Proposed: * Registered users: 0 to +1 * Developers: -1 to +2 * Core developers: -2 to +2 * FelixS: If people can give +1, they should be allowed to give -1. * Martin: So should we give -2 privileges to everyone with +2 privileges as well? * FelixS: The -1 allows me to see attitudes about things without needing to read come * Martin: I feel like the -1 rights should go to people who have actually submitted patches - it’s not hard. * Max, David, Daniel: Agreed * FelixS: Disagree * Documentation needs to be updated. * We can change it back if there are issues. ### [Martin] Implementing fuzzing testing at coreboot. * First test at [https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/main/util…] * Any APIs & anything loaded out of SPI should be fuzzed when possible. * Add to ongoing projects. ### [Martin] Gtiles is currently down * FelixS added some firewallish rules to the web server to block some bots. Still not very efficient - each Bot needs to be blocked individually. * We don’t get IP addresses of requests. * Daniel: Search engines also index GitHub on which we have mirrored out repos, so when it’s about code visibility/discoverability, we can block crawlers completely to lower the impact on our own infra. People can use the GitHub viewer and Gitiles alike, giving just a different view on the same data. ### [FelixS] Revisit register naming for I2c device registers: * See (https://review.coreboot.org/c/coreboot/+/77098) - This only changes the *coreboot* structures, not device #defines and device specific structures. * After discussion about this patch, there’s more support for keeping internal naming consistent, even if it doesn’t match the names from the specs. * Werner: Keep the names consistent with the datasheets even if they don’t match the coreboot structures. Max: Agreed * Martin & FelixS would prefer to change. ### [Martin] Renaming SPI master/slave * There’s no specific SPI spec, but there are a number of major companies who have changed the names in their specifications. Most notably, Intel has changed the names in the eSPI specification to controller/target. \ Unfortunately, there’s no real agreement on what to change the names to: \ [https://en.wikipedia.org/wiki/Serial_Peripheral_Interface#Alternative_termi…] * Martin’s proposal would be to go with the eSPI names of controller/target as eSPI. \ * Matt and Werner agree. * Julius points out "main" and "sub" preserves MISO/MOSI and is currently used on Wikipedia. * Max likes this. David +1 * Nico: This seems a bit forced * SPI: main/sub and eSPI: controller/target (Devices use whatever their datasheet says) * FelixS: Let’s look at what the linux kernel does. ### [Martin] Designing a coreboot Poster & Brochure for conferences * We’d like to design a poster & brochure to have at conferences and other places where coreboot information is desired. * [https://docs.google.com/document/d/1l-dSWram1vpq6-fYYqecYmOXCpj_7YXSnBx-kaK…] * Please comment or contribute * Marvin has a flyer * Add a payload section - Most used payloads - add logos * Adding a bunch of qr codes pointing to the website for the vendors & consultants * Shortened links as well or instead * Make part of the domain instead - gsoc.coreboot.org instead of https://doc.coreboot.org/contributing/gsoc.html ### [Martin] Info only: The 24.02 release is complete and announced. * Next release will be Mid-May. ### [FelixS] Not applying to GSOC this year - deadline is passed. * Not many people interested in mentoring - This is a big time investment. # Next meeting * March 20, 2024. * [Meeting link](https://bbb.sfconservancy.org/b/mar-sfn-e22-axi). * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice * Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes [2024-03-06](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1… 1).

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