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About: "Free hardware"; Servers
by p db 09 Feb '25

09 Feb '25

Dear Coreboot, I am searching from different time, information about "Free hardware"; Servers, hardware that can be considerated "Ethic"; which supports 'Coreboot"; that has respect for the surrounding environment, which consumes little electricity and at the same time produces little Co2 " Carbon Dioxide", on which it is possible to install a Gnu/linux distribution, of those recognized as 100% Free Software by the Free Software Foundation, https://www.gnu.org/distros/free-distros.en.html as is possible dedicate space of the hard disk to the Gnu/Hurd operating system! Actually i know the "Silicon Mechanics", but i don't know, which models can support "coreboot", if anyone knows such other name, and that is "Ethic" and has support for "coreboot", is free to suggest the name and the model. Awaiting your reply, Best Regards, Paolo Del Bene [PdB71]

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looking for cheap fw box with coreboot support
by Eero Volotinen 09 Feb '25

09 Feb '25

Hi, Is there any cheap firewall box at aliexpress that can support coreboot? Eero

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Re: coreboot Digest, Vol 239, Issue 8
by Keith Hui 06 Feb '25

06 Feb '25

(I strongly suggest community members from US not respond for sanction concerns.) I am not too deep into the coreboot build system either, but I can tell you that what you changed is part of SeaBIOS payload, which the coreboot build brings in fresh every time you compile. This is not part of coreboot per se, and because it is brought in fresh each time, no wonder your changes are getting lost. You'll want to get the SeaBIOS sources yourself, make changes, build a binary, and insert it as a binary payload, instead of selecting SeaBIOS as your payload. I am a student from tehran university in iran and I am interested to > booting system's and I research in this field > I compiled compiled and build your project in the qemu and run > successfully but i have problem if i want to changing message that show in > the qemu. > > for this I changing some printf() function in file > /coreboot/payloads/external/Seabios/seabios/src/boot.c > and then commit this changing and use make to recompiling project but > nothing changing and then use "make clean " for deleting all the compiled > file and recompile all of the project again by "make" and after this i see > all of the my changing in the > /coreboot/payloads/external/Seabios/seabios/src/boot.c is deleted and even > my git commited is deleted . > > how build system work this happens? > > how to solve this problem and changing the massage in the qemu terminal? > > and please explain to me source for this subject (i search in coreboot > documentation but i can't find proper source) > > With respect and apologies for any English grammatical errors in the text. > Regards Keith >

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2025-02-05 - coreboot Leadership Meeting Minutes
by mina＠coreboot.org 06 Feb '25

06 Feb '25

# 2025-02-05 - coreboot Leadership Meeting ## Attendees Felix Held, Jay Talbott, Julius Werner, Andy Ebrahiem, Martin Roth, Maximilian Brune, Matt DeVillier, Christian Walter, Andre, Mina Asante, David Hendricks, Alicja Michalska, Jon Murphy, Jeremy Compostella, Elyes. ## Open Action Items * 2024-11-27 * Send out poll with regards to LLM usage (requested by SFC) * 2024-10-30 * Add clarification to docs, “do not use gerrit change-id or CB: format in reference to already-merged patches.” * 2024-10-16 * Matt: Set up a meeting to discuss board status alternatives and send out invites. * Decouple data collection with uploading * Require gerrit credentials or other auth to push * Json format? * https://github.com/chrultrabook/linux-tools/blob/main/debugging.sh * 2024-09-18 * Jon: Schedule a dedicated meeting to discuss the Coverity defects and action plan. * Werner: Send out an invite for the meeting. Sent out a poll to find a time slot: https://rallly.co/invite/1c8J3azXAcje * 2024-05-01 * Nick Van Der Harst volunteered for Dutch. "gogo gogo" would like to translate to Russian (?) * 2024-01-10 * Nico: (https://review.coreboot.org/q/topic:enforce_region_api) * Daniel: Look at how we want to localize (non console) strings for coreboot. Long term project. ## Minutes ### [Elyes] coreboot toolchain and/or Jenkins malfunction * There is something wrong with the coreboot toolchain and/or Jenkins. Here, (https://review.coreboot.org/c/coreboot/+/86100), I'm expecting the build to fail, at least getting this error: "error: initializer-string for array of 'char' is too long"! And here, (https://review.coreboot.org/c/coreboot/+/86012), it looks like Jenkins is mixing GCC versions! So, what is the plan? * I can understand adding support for a library that can be used by coreboot, as seen here(https://review.coreboot.org/c/coreboot/+/80737), but I'm having trouble understanding the purpose of adding LIBSTDCXX. Unless I'm mistaken, this library is not used in coreboot. What is the strategy of coreboot after this add and that of 'go' here (https://review.coreboot.org/c/coreboot/+/63639)? * To give some more background: * During the creation of the patch there was talk about the US government making SBOMs mandatory at some point (not sure what the current status is). * The go dependency was already there although to be fair it was only present in tooling (intel-sec-tools) as far as I know. We had multiple long talks (also in the leadership meeting) about adding go as a dependency into the coreboot build system. As far as I know we agreed on letting it into the coreboot build system because it was an optional dependency. * We worked with [https://fwupd.org/](https://fwupd.org/) together to facilitate SBOM as part of Firmware updates. More specifically you can see SBOM information on their web interface when you look at the Firmware updates. I haven’t looked at it for a while now, so I am not sure about the current status. * Isn’t that only an ABI for aarch64? According to the content of the patch it is removing the riscv abi (although the title mentions aarch64). * Rv32 is used by one of our emulation targets (src/mainboard/emulation/qemu-riscv) ### [Martin] Someone mentioned that GitHub isn't being synced anymore. * Felix S. already handled this? Need to double-check. ### [Alicja] Release notes status? ### [Martin] Adding IT support (reducing the "bus" factor) * Need someone knowledgeable in NixOS and our infra (Jenkins, Gerrit, Docker, etc) * Max has a potential candidate who can help. * We're happy to use some coreboot funds to do admin duties and document everything. * [Max] Toolchain is a significant maintenance burden. There are other projects out there, maybe we can utilize another project's toolchain (or merge?) so we don't shoulder the entire burden. * [Martin] For now the plan is to just split it into a separate module. We only update the toolchain 4x per year, and probably don't need to do it that often. * Splitting would allow us to test it separately from coreboot. We do toolchain builds but don't stress test the toolchain itself beyond "does it build?" * Splitting would make it easier to update - if people want more frequent updates, then that would be fine. * [Jon] This is also what ChromeOS does, for the above reasons. * [Max] Do we want all of our payloads to compile using coreboot's toolchain? * [Martin] We can try this out to see what's needed to support different payloads. * [David] It's nice, but not required. When we started LinuxBoot, we were using the coreboot toolchain since ARM64 was one of the early targets and doing the usual cross-toolchain setup was a pain outside of coreboot. * [Martin] Will look at adding build tests in Jenkins; can't promise to fix anything. * Having the latest working toolchain version is valuable info, even if the more recent toolchains fail. # Next Leadership Meeting * February 19, 2025. * [coreboot Calendar](https://coreboot.org/calendar.html). # Notice * Decisions shown here are not necessarily final, and are based on the current information available. If there are questions or comments about decisions made, or additional information to present, please put it on the leadership meeting agenda and show up if possible to discuss it. Of course, items may also be discussed on the mailing list, but as it's difficult to interpret tone over email, controversial topics frequently do not have good progress in those discussions. For particularly difficult issues, it may be best to try to schedule another meeting. # coreboot leadership meeting minutes https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgK…

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Help me understand more about coreboot
by sourabadi 05 Feb '25

05 Feb '25

Hello I am a student from tehran university in iran and I am interested to booting system's and I research in this field I compiled compiled and build your project in the qemu and run successfully but i have problem if i want to changing message that show in the qemu. for this I changing some printf() function in file /coreboot/payloads/external/Seabios/seabios/src/boot.c and then commit this changing and use make to recompiling project but nothing changing and then use "make clean " for deleting all the compiled file and recompile all of the project again by "make" and after this i see all of the my changing in the /coreboot/payloads/external/Seabios/seabios/src/boot.c is deleted and even my git commited is deleted . how build system work this happens? how to solve this problem and changing the massage in the qemu terminal? and please explain to me source for this subject (i search in coreboot documentation but i can't find proper source) With respect and apologies for any English grammatical errors in the text.

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 03 Feb '25

03 Feb '25

Dear coreboot Community, Please be reminded that we have an upcoming leadership meeting scheduled for Wednesday, February 5, 2025. [1] Kindly review the agenda and share your thoughts or suggest additional items you would like to discuss during the meeting. [2] Thank you. ## Current Agenda Items ### [Elyes] coreboot toolchain and/or Jenkins malfunction * There is something wrong with the coreboot toolchain and/or Jenkins. Here, (https://review.coreboot.org/c/coreboot/+/86100), I'm expecting the build to fail, at least getting this error: "error: initializer-string for array of 'char' is too long"! And here, (https://review.coreboot.org/c/coreboot/+/86012), it looks like Jenkins is mixing GCC versions! So, what is the plan? * I can understand adding support for a library that can be used by coreboot, as seen here(https://review.coreboot.org/c/coreboot/+/80737), but I'm having trouble understanding the purpose of adding LIBSTDCXX. Unless I'm mistaken, this library is not used in coreboot. What is the strategy of coreboot after this add and that of 'go' here? (https://review.coreboot.org/c/coreboot/+/63639) ? * GCC-15 deprecates support for ILP32 (-mabi=ilp32). If I'm not mistaken, RV32 is not used in coreboot tree. Should we remove it? (see (https://review.coreboot.org/c/coreboot/+/86053) ) [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 31 Jan '25

31 Jan '25

Dear coreboot Community, We are pleased to announce that our next leadership meeting is scheduled for February 5, 2025. [1] Please update the agenda with matters you wish to see addressed during the meeting. [2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Bug #576] (New) GPIO locking is broken on Kaby Lake and possibly other platforms
by Mate Kukri 30 Jan '25

30 Jan '25

Issue #576 has been reported by Mate Kukri. ---------------------------------------- Bug #576: GPIO locking is broken on Kaby Lake and possibly other platforms https://ticket.coreboot.org/issues/576 * Author: Mate Kukri * Status: New * Priority: Normal * Target version: none * Start date: 2025-01-30 ---------------------------------------- Many supported Kaby Lake boards (and possibly newer platforms as well) are vulnerable to [TPM GPIO reset attacks](https://mkukri.xyz/2024/06/01/tpm-gpio-fail.html). Trying to fix this by marking the affected GPIOs as locked in gpio.h and even also selecting `SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS` does not work. This was discovered last year and briefly discussed on #coreboot, but it came up again on the Heads matrix group in relation to supporting the TPM on the in-progress ThinkPad T480 port. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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Help me push coreboot's envelope on Asus P8Z77-V
by Keith Hui 29 Jan '25

29 Jan '25

Hello all, Doing some work with (Bill's) Asus P8Z77-V board and running into some issues and limits. See it unfold at https://review.coreboot.org/c/coreboot/+/85413 That said, I've run into a few issues and limits trying to bring feature parity to it. It will also help me with porting coreboot to two more boards in the family: P8Z77-V LE PLUS and Sabertooth Z77. A patch has been sent for Sabertooth and I have one on the way maybe early next month - it needs a cap replaced, maybe more. The other board is on hand and a patch is being prepared. I'll put in as much as I can get working before sending it in. #1. Bill has been testing this patch (thanks!) with PCH soft strap #9 configured to have all lanes as x1. Actual routing is controlled by 3 GPIO lines from the super I/O, and it has card presence lines wired to the PCH. I got both working, but Bill still couldn't get his card to work on one of the two x1 slots. I need more fresh eyes to help. #2. Changing flash descriptor from within coreboot. I've come to a point where I need to be able to change the PCH soft straps based on user selection. As you can see in 85413, and in consultation with Nicholas (that convo is also on this list), to make it fully work I need to be able to change the otherwise read-only soft strap #9 in the flash descriptor, and it appears Asus is doing it as well. I know about SPI console - I actually used it during early attempts of porting my P8Z77-M - but I have not dealt with writing to the SPI from within coreboot nor have I studied SPI console deep enough to be able to come up with code of my own. 7-series PCH supports hardware sequencing if the SPI flash chip meets certain requirements. Does it mean I can just write() to the memory area mapped for SPI flash, and it fires the SPI commands for me? Will it do sector erase on my behalf and preserve what's not being overwritten? Nicholas mentioned some Haswell boards also need this done. Would love to hear some progress there. #3. Dynamic device tree? There will be times when the devicetree needs to change based on user selection. Not necessarily nvram options, but also choices made in 'make menuconfig'. In my efforts they are respectively enabling/disabling PCIe root ports 2-4 (based on whether port 1 is set for x4) and enabling the SIO serial port on Sabertooth if the user enables the "hacked serial port" in Kconfig. Devicetrees are supposed to be static, I get this. Where are the runtime hooks where code can go in and say "nope, this device is off"? Many thanks Keith

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2025_01_29 coreboot Group Review Sesssion
by mina＠coreboot.org 27 Jan '25

27 Jan '25

Hello coreboot! Our upcoming biweekly group review meeting is scheduled for Wednesday, January 29. https://meet.google.com/kpu-yozw-gtt Please check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html As usual, we'll begin by reviewing a few patches together, then switch to individual reviews. However, everyone will still be available if you have questions about the patch you're reviewing. Here is the link to the list of patches to be reviewed this week: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…). Kindly add any specific patches you'd like the group to review to the top of the sheet. Thank you. Best regards, Mina.

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