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Could not find a bounce buffer... Payload not loaded. Intel 440BX/LX Board
by Christian Sühs 10 Sep '24

10 Sep '24

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2024-09-11 coreboot Group Review Session
by mina＠coreboot.org 09 Sep '24

09 Sep '24

Hello coreboot! We have an upcoming group review session on Wednesday: https://meet.google.com/kpu-yozw-gtt Please check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html As usual, we’ll begin by reviewing a few RFC patches together, then switch to review patches individually for a bit, but everyone will be available if you have questions about the patch you’re reviewing. Here’s the link to the list of patches to be reviewed: (https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY…) Kindly add any specific patches you'd like the group to review to the top of the sheet. Given the limited time for our review session, any reviews completed beforehand would be greatly appreciated. Thank you. Best regards, Mina.

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MrChromebox-2408 release is out
by Matt DeVillier 09 Sep '24

09 Sep '24

(2024.09.08) Now supporting nearly 300 x86_64 ChromeOS devices, this new release is based on the coreboot 24.08 tag (August 2024) and includes the following changes: * Rebased on coreboot tag 24.08 * New edk2 branch (uefipayload_2408), rebased on upstream edk2-stable202408 tag * Adjusted touchscreen init timing params for JINLON * Minor improvements to EC software sync code * Added automatic fan control for 7th/8th-gen Chromeboxes (FIZZ board) * Fixed fan control on 10th-gen Chromeboxes * Added ACPI driver attachment for SPI CR50 TPMs to use coolstar's Windows drivers * Added ability to configure (when compiling) UMA allocation for Intel Sandy/Ivybridge and AMD Stoneyridge and Picasso devices * Fixed display init on some boards (LASER14, MARASOV, OMNIGUL, KINOX) * AMD Picasso devices no longer use vboot https://mrchromebox.tech cheers, Matt

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[coreboot - Bug #527] Can't compile coreboot on Arch Linux
by Peter Daru 07 Sep '24

07 Sep '24

Issue #527 has been updated by Peter Daru. Sorry if this doesn't fit here. I thought this is similar if not same issue as op's one. I was following [doc tutorial](https://doc.coreboot.org/tutorial/part1.html) for qemu x64 and also couldn't compile. I run fully up to date installation (apart from kernel itself). Turns out doing `$ make clang CPUS=$(nproc)` and then `$ make` I was able to compile. This is what I got following tutor: ``` # # No change to /home/daru/Git/coreboot/payloads/coreinfo/.config # Makefile:358: warning: overriding recipe for target '/home/daru/Git/coreboot/payloads/coreinfo/libpayload/arch/x86/exec.libc.o' Makefile:358: warning: ignoring old recipe for target '/home/daru/Git/coreboot/payloads/coreinfo/libpayload/arch/x86/exec.libc.o' LPGCC coreinfo.bin /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: warning: exception_asm.libc.o: missing .note.GNU-stack section implies executable stack /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: NOTE: This behaviour is deprecated and will be removed in a future version of the linker /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: warning: build/coreinfo.bin has a LOAD segment with RWX permissions /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: build/cpuinfo_module.o: in function `cpuinfo_module_init': cpuinfo_module.c:(.text+0x474): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: build/timestamps_module.o: in function `timestamp_print_entry.constprop.0': timestamps_module.c:(.text+0x157): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: timestamps_module.c:(.text+0x194): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/coreinfo/libpayload/libpayload.a(time.libc.o): in function `update_clock': /home/daru/Git/coreboot/payloads/libpayload/libc/time.c:60:(.text.time+0xe8): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/libpayload/libc/time.c:65:(.text.time+0x11d): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/coreinfo/libpayload/libpayload.a(time.libc.o):/home/daru/Git/coreboot/payloads/libpayload/libc/time.c:68: more undefined references to `__udivdi3' follow /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/coreinfo/libpayload/libpayload.a(printf.libc.o): in function `print_number': /home/daru/Git/coreboot/payloads/libpayload/libc/printf.c:261:(.text.printf_core+0x5c0): undefined reference to `__udivmoddi4' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/coreinfo/libpayload/libpayload.a(gcd.libc.o): in function `gcd': /home/daru/Git/coreboot/src/commonlib/bsd/gcd.c:14:(.text.gcd+0x58): undefined reference to `__umoddi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/src/commonlib/bsd/gcd.c:19:(.text.gcd+0x76): undefined reference to `__umoddi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/coreinfo/libpayload/libpayload.a(timer.libc.o): in function `get_cpu_khz_xtal': /home/daru/Git/coreboot/payloads/libpayload/arch/x86/timer.c:121:(.text.get_cpu_speed+0x9f): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/libpayload/arch/x86/timer.c:121:(.text.get_cpu_speed+0xb0): undefined reference to `__udivdi3' /home/daru/Git/coreboot/util/crossgcc/xgcc/lib/gcc/x86_64-elf/14.2.0/../../../../x86_64-elf/bin/ld.bfd: /home/daru/Git/coreboot/payloads/coreinfo/libpayload/libpayload.a(timer.libc.o): in function `calibrate_pit': /home/daru/Git/coreboot/payloads/libpayload/arch/x86/timer.c:78:(.text.get_cpu_speed+0x17c): undefined reference to `__udivdi3' collect2: error: ld returned 1 exit status make[2]: *** [../libpayload/Makefile.payload:104: build/coreinfo.bin] Error 1 make[1]: *** [Makefile:64: defaultbuild] Error 2 make: *** [payloads/Makefile.mk:38: payloads/coreinfo/build/coreinfo.elf] Error 2 ``` ---------------------------------------- Bug #527: Can't compile coreboot on Arch Linux https://ticket.coreboot.org/issues/527#change-1918 * Author: naixin Lv * Status: New * Priority: Normal * Category: build system * Target version: master * Start date: 2024-02-23 * Affected versions: master * Needs backport to: none * Affected hardware: GIGABYTE GA-H61M-DS2 * Affected OS: none ---------------------------------------- I want to compile coreboot for my Gigabyte GA-H61M-DS2 mainboard, but I only found a short guide for this board at this site: https://www.iot-tech.dev/full.php?ar=166 After downloaded the coreboot git repository, It gave me this error: ``` shell /home/zhongli/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/console/vtxprintf.o: in function `number': /home/zhongli/coreboot/src/console/vtxprintf.c:63:(.text.number+0x12b): undefined reference to `__udivmoddi4' /home/zhongli/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/lib/gcc.o: in function `__wrap___divdi3': /home/zhongli/coreboot/src/lib/gcc.c:19:(.text.__wrap___divdi3+0x1): undefined reference to `__divdi3' /home/zhongli/coreboot/util/crossgcc/xgcc/bin/x86_64-elf-ld.bfd: build/romstage/lib/gcc.o: in function `__wrap___udivdi3': /home/zhongli/coreboot/src/lib/gcc.c:20:(.text.__wrap___udivdi3+0x1): undefined reference to `__udivdi3' make: *** [src/arch/x86/Makefile.mk:191: build/cbfs/fallback/romstage.debug] Error 1 ``` And I'll put my config file on here. Any help ? ---Files-------------------------------- defconfig (726 Bytes) ifd_shrinked.bin (4 KB) me_shrinked.bin (96 KB) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2024-09-04 - coreboot Leadership Meeting Canceled
by mina＠coreboot.org 02 Sep '24

02 Sep '24

Hello coreboot, Kindly be informed that the leadership meeting scheduled for Wednesday, September 4, has been canceled due to a time conflict with OSFC. [1] Thank you. [1](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK….

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[coreboot - Bug #552] (New) X201 not booting with edk2 payload
by Maya Matuszczyk 01 Sep '24

01 Sep '24

Issue #552 has been reported by Maya Matuszczyk. ---------------------------------------- Bug #552: X201 not booting with edk2 payload https://ticket.coreboot.org/issues/552 * Author: Maya Matuszczyk * Status: New * Priority: Normal * Category: board support * Target version: none * Start date: 2024-08-18 * Affected hardware: x201 ---------------------------------------- Hello, I tried to update my x201 with a new version of coreboot(I lost the working one). After building(using default config + set to x201 + bigger cbfs + linear high-res framebuffer) with latest release I couldn't get anything with edk2 to boot on it. I've tried changing `RESOURCE_ALLOCATION_TOP_DOWN` and using newer/older tags of MrChromebox's edk2 fork. -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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[coreboot - Bug #121] T520: Hangs in OS
by Ján Mlynek 01 Sep '24

01 Sep '24

Issue #121 has been updated by Ján Mlynek. I updated to main a week ago and after more than 100 hours of uptime, I didn't experience any hangs so far. This amount of time wasn't possible to achieve before. I will report again in a few weeks if no hangs occur but it looks promising. T420, i7-3632QM ---------------------------------------- Bug #121: T520: Hangs in OS https://ticket.coreboot.org/issues/121#change-1907 * Author: Firstname Lastname * Status: In Progress * Priority: Normal * Category: chipset configuration * Start date: 2017-06-09 * Affected hardware: SNB, IVY * Affected OS: - ---------------------------------------- I have been running coreboot since 2017.04.15 and have experienced hangs ever since then. It was suggested by folk on the IRC that I run memtest to check for incorrect raminit causing errors, however I have run memtest for 12 hours straight with no errors. Due to the ambiguous nature of the hangs (immediate freeze with no warning signs, audio gets stuck repeating the last 50ms or so of noise, not sure what this effect is called) I don't have much useful information other than the .config and dmesg. However one thing I can say with high confidence is that the hangs occur significantly more frequently in Linux (*buntu distros) than Windows 10. Within an hour of launching Linux a hang is likely, whereas Windows typically runs for many hours before a hang occurs. I considered this an insignificant anecdotal anomaly at first but over the course of the nearly 2 months I have been running coreboot it seems to be a solid trend. The hangs occur anywhere, typically during mere desktop usage or basic web browsing. Additionally there is another form of hang I experience where the screen goes black except for some sort of graphical corruption down the left side (http://i.imgur.com/4zWrlpX.jpg), whether this is related to the more common total freeze hangs I don't know but I figured I should include it nonetheless. These hangs only occur about 1:20 compared to the regular hangs. ---Files-------------------------------- config (20.7 KB) dmesg.txt (57.3 KB) cbmem-raminit.txt (62 KB) lspci.txt (29.6 KB) cpuinfo.txt (3.94 KB) defconfig (1023 Bytes) defconfig (699 Bytes) -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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coreboot Meetings Announcement And Agenda Call
by mina＠coreboot.org 30 Aug '24

30 Aug '24

Dear community, Please note that we have an upcoming coreboot leadership meeting scheduled for Wednesday, September 4, 2024.[1] Kindly take a moment to update the current agenda with matters you wish to see discussed during the meeting.[2] Thank you. Best regards, Mina Asante. [1](https://coreboot.org/calendar.html) [2](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkK…

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[coreboot - Bug #553] (New) M95M02 write failure
by Miklos Marton 30 Aug '24

30 Aug '24

Issue #553 has been reported by Miklos Marton. ---------------------------------------- Bug #553: M95M02 write failure https://ticket.coreboot.org/issues/553 * Author: Miklos Marton * Status: New * Priority: Normal * Target version: none * Start date: 2024-08-21 * Affected hardware: STLinkV3 * Affected OS: Linux ---------------------------------------- While trying to add support for EEPROM devices (which lacks the erase capability) I came across some issues with implementing it. The only device so far which lacks erase capability is the M95M02. When trying to write it via force I receieve a SIGSEV and the following output: ``` shell 08:17:18: Debugging /home/mm/Projektek/flashrom/flashrom -p stlinkv3_spi -c M95M02 -f -w /tmp/myfile ... could not find '.gnu_debugaltlink' file for /lib/x86_64-linux-gnu/libcap.so.2 flashrom 1.4.0-rc2 (git:v1.4.0-rc2-1-gbd3c5f31) on Linux 6.8.0-40-generic (x86_64) flashrom is free software, get the source code at https://flashrom.org Connected to STLink V3 with bridge FW version: 5 SCK frequency set to 750 kHz Assuming ST flash chip "M95M02" (256 kB, SPI) on stlinkv3_spi. === This flash part has status UNTESTED for operations: WP The test status of this chip may have been updated in the latest development version of flashrom. If you are running the latest development version, please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash chip. Please include the flashrom log file for all operations you tested (see the man page for details), and mention which mainboard or programmer you tested in the subject line. You can also try to follow the instructions here: https://www.flashrom.org/contrib_howtos/how_to_mark_chip_tested.html Thanks for your help! spi_get_opcode_from_erasefn: unknown erase function (0x1). Please report this at flashrom(a)flashrom.org ``` Backtrace: ``` >~"#0 0x000055555558f047 in check_block_eraser (flash=flash@entry=0x7fffffffd9d0, k=k@entry=0, log=log@entry=0) at flashrom.c:489\n" >~"#1 0x000055555558f0c7 in count_usable_erasers (flash=flash@entry=0x7fffffffd9d0) at flashrom.c:508\n" >~"#2 0x000055555558f15f in chip_safety_check (flash=flash@entry=0x7fffffffd9d0, force=1, read_it=read_it@entry=0, write_it=write_it@entry=1, erase_it=erase_it@entry=0, verify_it=verify_it@entry=1) at flashrom.c:2019\n" >~"#3 0x0000555555591426 in prepare_flash_access (flash=flash@entry=0x7fffffffd9d0, read_it=read_it@entry=false, write_it=write_it@entry=true, erase_it=erase_it@entry=false, verify_it=verify_it@entry=true) at flashrom.c:2121\n" >~"#4 0x0000555555591821 in flashrom_image_write (flashrom_flashctx=flashrom_flashctx@entry=0x7fffffffd9d0, buffer=buffer@entry=0x7ffff7ea5010, buffer_len=buffer_len@entry=262144, refbuffer=refbuffer@entry=0x0) at flashrom.c:2287\n" >~"#5 0x00005555555795d6 in do_write (flash=flash@entry=0x7fffffffd9d0, filename=0x55555565c2c0 \"/tmp/myfile\", referencefile=0x0) at cli_classic.c:535\n" >~"#6 0x000055555557a455 in main (argc=<optimized out>, argv=<optimized out>) at cli_classic.c:1255\n" ``` -- You have received this notification because you have either subscribed to it, or are involved in it. To change your notification preferences, please click here: https://ticket.coreboot.org/my/account

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2024-08-28 coreboot Group Review Session
by mina＠coreboot.org 26 Aug '24

26 Aug '24

Hello coreboot! We have an upcoming group review session on Wednesday: https://meet.google.com/kpu-yozw-gtt Check the coreboot calendar for the time in your timezone: https://coreboot.org/calendar.html As usual, we’ll begin by reviewing a few RFC patches together, then switch to review patches individually for a bit, but everyone will be available if you have questions about the patch you’re reviewing. Here’s the link to the list of patches to be reviewed: https://docs.google.com/spreadsheets/d/1io-tewVlkX3PAkhR9ttCKjJXiXR9Emy6qsY… 61#gid=1189723661 Please add any specific patches you'd like the group to review to the top of the sheet. Given the limited time for our review session, any reviews completed beforehand would be greatly appreciated. Thank you. Best regards, Mina.

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