Hello,

Thanks Angel. To clarify, the part of the chipset you're referring to would be the memory controller on the CPU, yes? Not somewhere on the southbridge?

Thanks,

-Matt

On Wed, Sep 8, 2021 at 11:33 AM Angel Pons <th3fanbus@gmail.com> wrote:

Hi Matt, list,

On Wed, Sep 8, 2021 at 3:29 PM Matt B <matthewwbradley6@gmail.com> wrote:
>
> Would an Ivybridge CPU even be expected to work with RDIMMs? Was this something anticipated when native raminit was written?

I don't think so. RDIMMs have higher latencies and very likely exceed
the maximum value that can be programmed into the chipset's timing
registers. Native raminit doesn't account for RDIMMs at all.

> -Matt

Best regards,
Angel