the ECC support on Sandy/Ivy Bridge should be fully working since Aug
2020, to be exact, commit b5fa9c8200423beb660403b6656fa8fd5d7edc31 .
By default it is automatically enabled if the hostbridge and all DIMMs
are ECC capable. It was tested on HP Z220 workstation PC.
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On Fri, Aug 13, 2021 at 9:46 PM Matt B <email@example.com> wrote:
> I gather that while native ram init is very far along and quite featureful, it doesn't support ECC. I'm interested to know if there have been past attempts at it, and what might be required for it to work.
> In the unofficial mapping  it looks like there's just one register to turn it on, plus some registers to inject faults for testing. (I imagine you would also need to clear the memory to avoid lots of errors from random initial contents, and make sure all the DIMMS are the same type first)
> It certainly "looks" simple (famous last words) so I'm wondering in part if the unofficial register documentation is just very incomplete? Is there any intel guidance on ECC out there?
> I suppose having ECC is attractive for servers, though I don't think people would still run ivybridge/sandybridge in production. I'm more interested in it for the Optiplex 9010 which appears to support ECC on the factory BIOS.  Would make a really nice NAS (external SAS disk shelf) if ECC worked under coreboot. Would also get bonus points as a daily-driver/home server from me.
>  https://doc.coreboot.org/northbridge/intel/sandybridge/nri_registers.html
> -Matthew Bradley
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