coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

Fwd: Unable to power up db800 with coreboot
by Phani Babu Giddi 01 Mar '08

01 Mar '08

Hi, I am trying to build coreboot for AMD DB800 and that the Linux Kernel is never started but I see a prompt on the serial terminal "grub" and when I issue the boot command it complains of "Unsupported boot format". Has any body seen this before. I have a HDD which has SLES 10 SP1 installed on it I have got four partitions one of them been a extended partition. /dev/hda1 --> boot (ext2) /dev/hda2 --> swap /dev/hda3 --> Root file system (resierfs) /dev/.... .... Based on this I have given the following options for FILO, do you think this is where the problem is.... MENULST_FILE = "hda1:/grub/menu.lst" AUTOBOOT_FILE = "hda1:/vmlinuz initrd hda1:/initrd root=/dev/hda3 vga=0x317 console=tty0 console=ttyS0,115200" Regards, Phani

2 2

Image format is unsupported while building QEMU
by malatesh kamatad 01 Mar '08

01 Mar '08

Hi...... We are building the QEMU, we followed the steps as given in the coreboot.org/QEMU_BUILD_Tutorial 1. building the FILO payload we downloaded FILO(0.5) then to create the filo.elf file we followed these steps $make $ vi Config $ make 2. Building coreboot for creating the coreboot image we followed this steps $ ./buildtarget emulation/qemu-x86 $ make 3. Building QEMU then we installed QUMU(0.9.0) 4. Creating a hard disk image for creating empty disk image we used $ qemu-img create -f raw disk.img 5G Then formated using $ mkfs.ext2 -F disk.img then we created mountpoint and mount the image # mkdir /mnt/rootfs # mount -o loop disk.img /mnt/rootfs then we created the boot directory and copied Linux kernel(vmlinuz) and initramfs (initrd) to it : # mkdir /mnt/rootfs/boot # cp vmlinuz /mnt/rootfs/boot/vmlinuz # cp initrd /mnt/rootfs/boot/initrd then we unmounted cd out of /mnt/rootfs # umount /mnt/rootfs # exit 5. Starting coreboot in QEMU Then executed QEMU using $ qemu -L ~ -hda disk.img -nographic At the end of this we got the ERROR like this [malatesh@turtle22 ~]$ qemu -L ~ -hda disk.img -nographic Could not configure '/dev/rtc' to have a 1024 Hz timer. This is not a fatal error, but for better emulation accuracy either use a 2.6 host Linux kernel or type 'echo 1024 > /proc/sys/dev/rtc/max-user-freq' as root. Could not open '/dev/kqemu' - QEMU acceleration layer not activated (qemu) coreboot-2.0.0-GRUB2 Fri Feb 22 15:42:36 IST 2008 starting... Copying coreboot to RAM. Jumping to coreboot. coreboot-2.0.0-GRUB2 Fri Feb 22 15:42:36 IST 2008 booting... Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] enabled PCI: 00:01.3 [8086/7113] enabled PCI: 00:02.0 [1013/00b8] enabled PCI: 00:03.0 [10ec/8029] enabled PCI: pci_scan_bus returning with max=000 done Allocating resources... Reading resources... Done reading resources. Setting resources... RAM size config registers are empty; defaulting to 64 MBytes I would set ram size to 0x10000 Kbytes PCI: 00:01.1 20 <- [0x0000001400 - 0x000000140f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe000000 - 0x00fe000fff] size 0x00001000 gran 0x0c mem PCI: 00:03.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io Done setting resources. Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 00/00 PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 subsystem <- 00/00 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 01 done. Initializing devices... Root Device init PCI: 00:00.0 init PCI: 00:01.0 init PCI: 00:01.1 init PCI: 00:01.3 init PCI: 00:02.0 init INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1013, did=b8 rom base, size: c0000 BAD SIGNATURE 0x0 0x0 biosint: INT# 0x10 biosint: eax 0x2 ebx 0x0 ecx 0x1 edx 0x0 biosint: ebp 0x11fac esp 0xffa edi 0x0 esi 0x12898 biosint: ip 0x8046 cs 0x0 flags 0x46 BIOSINT: Unsupport int #0x10 PCI: 00:03.0 init Devices initialized Copying IRQ routing tables to 0xf0000...done. Verifing copy of IRQ routing tables at 0xf0000...failed Moving GDT to 0x500...ok Adjust low_table_end from 0x00000530 to 0x00001000 Adjust rom_table_end from 0x000f0400 to 0x00100000 Wrote coreboot table at: 00000530 - 00000bec checksum 6eb8 Welcome to elfboot, the open sourced starter. January 2002, Eric Biederman. Version 1.3 rom_stream: 0xfffc0000 - 0xfffeffff Found ELF candidate at offset 0 header_offset is 0 Try to load at offset 0x0 Booting '' Unsupported image format with regards, malatesh.

3 2

[PATCH] v3: convert fake SPD to struct spd_entry
by Carl-Daniel Hailfinger 01 Mar '08

01 Mar '08

Convert all boards using fake SPD entries to struct spd_entry, thereby making sure we return 0xff for nonexisiting entries and shrinking the data structure by 85%. As a bonus, the various initram.c for boards with fake SPD are now almost identical. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Index: LinuxBIOSv3-spd/mainboard/artecgroup/dbe61/initram.c =================================================================== --- LinuxBIOSv3-spd/mainboard/artecgroup/dbe61/initram.c (Revision 621) +++ LinuxBIOSv3-spd/mainboard/artecgroup/dbe61/initram.c (Arbeitskopie) @@ -55,41 +55,59 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* SPD array */ -static const u8 spdbytes[] = { - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, - [SPD_BANK_DENSITY] = 0x40, - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, - [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ - [SPD_NUM_BANKS_PER_SDRAM] = 4, - [SPD_PRIMARY_SDRAM_WIDTH] = 8, - [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ - [SPD_NUM_COLUMNS] = 0xa, - [SPD_NUM_ROWS] = 3, - [SPD_REFRESH] = 0x3a, - [SPD_SDRAM_CYCLE_TIME_2ND] = 60, - [SPD_SDRAM_CYCLE_TIME_3RD] = 75, - [SPD_tRAS] = 40, - [SPD_tRCD] = 15, - [SPD_tRFC] = 70, - [SPD_tRP] = 15, - [SPD_tRRD] = 10, + +struct spd_entry { + u8 address; + u8 data; }; -u8 spd_read_byte(u16 device, u8 address) +/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spdbytes[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ +static u8 spd_read_byte(u16 device, u8 address) { + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - - if (device != (0x50 << 1)) { - printk(BIOS_DEBUG, " returns 0xff\n"); - return 0xff; + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + } + } } - printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); - - return spdbytes[address]; + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; } /** Index: LinuxBIOSv3-spd/mainboard/artecgroup/dbe62/initram.c =================================================================== --- LinuxBIOSv3-spd/mainboard/artecgroup/dbe62/initram.c (Revision 621) +++ LinuxBIOSv3-spd/mainboard/artecgroup/dbe62/initram.c (Arbeitskopie) @@ -45,36 +45,35 @@ * @ 200 ns, data-out window, 1.6; access, +- 70 ns; dqs-dq skew: .4ns * http://www.micron.com/products/partdetail?part=MT46V16M16P-5B */ + struct spd_entry { u8 address; u8 data; }; /* Save space by using a short list of SPD values used by Geode LX Memory init */ - static const struct spd_entry spdbytes[] = { - {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, - {SPD_BANK_DENSITY, 0x40}, - {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, - {SPD_MEMORY_TYPE, 7}, - {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10, /* A guess for the tRAC value */ - {SPD_MODULE_ATTRIBUTES, 0xff, /* FIXME later when we figure out. */ - {SPD_NUM_BANKS_PER_SDRAM, 4}, - {SPD_PRIMARY_SDRAM_WIDTH, 8}, - {SPD_NUM_DIMM_BANKS, 1}, - {SPD_NUM_COLUMNS, 0xa}, - {SPD_NUM_ROWS, 3}, - {SPD_REFRESH, 0x3a}, - {SPD_SDRAM_CYCLE_TIME_2ND, 60}, - {SPD_SDRAM_CYCLE_TIME_3RD, 75}, - {SPD_tRAS, 40}, - {SPD_tRCD, 15}, - {SPD_tRFC, 70}, - {SPD_tRP, 15}, - {SPD_tRRD, 10, + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, }; - /** * Given an SMBUS device, and an address in that device, return the value of SPD * for that device. In this mainboard, the only one that can return is DIMM0. @@ -89,9 +88,9 @@ u8 ret = 0xff; printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - if (device == DIMM0){ - for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){ - if (spd_table[i].address == address){ + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { ret = spd_table[i].data; } } Index: LinuxBIOSv3-spd/mainboard/pcengines/alix1c/initram.c =================================================================== --- LinuxBIOSv3-spd/mainboard/pcengines/alix1c/initram.c (Revision 621) +++ LinuxBIOSv3-spd/mainboard/pcengines/alix1c/initram.c (Arbeitskopie) @@ -55,41 +55,59 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* SPD array */ -static const u8 spdbytes[] = { - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, - [SPD_BANK_DENSITY] = 0x40, - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, - [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ - [SPD_NUM_BANKS_PER_SDRAM] = 4, - [SPD_PRIMARY_SDRAM_WIDTH] = 8, - [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ - [SPD_NUM_COLUMNS] = 0xa, - [SPD_NUM_ROWS] = 3, - [SPD_REFRESH] = 0x3a, - [SPD_SDRAM_CYCLE_TIME_2ND] = 60, - [SPD_SDRAM_CYCLE_TIME_3RD] = 75, - [SPD_tRAS] = 40, - [SPD_tRCD] = 15, - [SPD_tRFC] = 70, - [SPD_tRP] = 15, - [SPD_tRRD] = 10, + +struct spd_entry { + u8 address; + u8 data; }; -u8 spd_read_byte(u16 device, u8 address) +/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spdbytes[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ +static u8 spd_read_byte(u16 device, u8 address) { + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - - if (device != (0x50 << 1)) { - printk(BIOS_DEBUG, " returns 0xff\n"); - return 0xff; + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + } + } } - printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); - - return spdbytes[address]; + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; } /** -- http://www.hailfinger.org/

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Re: [coreboot] m57sli FAN control
by Ward Vandewege 29 Feb '08

29 Feb '08

Hi Ronald, On Thu, Feb 28, 2008 at 09:27:22PM +0100, Ronald Hoogenboom wrote: > On Wed, 2008-02-27 at 18:38 -0500, Ward Vandewege wrote: > > On Thu, Feb 28, 2008 at 12:13:13AM +0100, Ronald Hoogenboom wrote: > > > Why did you comment it out in r3118? Did you have some trouble after > > > all? > > > > It switches the cpu fan off on v1 of the board (PLCC) which is not ideal :/ > > I'm in the process of debugging that, which I hope to to finish on Friday > > when I'm back at the office. > > > Then you could have just turned off the 'HAVE_FANCTL' option for the V1 > boards... That should revert back to your fan-enable code. Two problems with that: 1) we don't make a distinction in the coreboot tree between v1 and v2 of the board (that's a good thing that I'd like to keep that way if we can) 2) I tried that, and the tree would not build anymore. I need to debug that too. > Can you use the --extra-dump option (with proprietary bios) for > superiotool and share the output with me? (just for curiousity) Certainly, attached. Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

1 0

r626 - coreboot-v3/mainboard/pcengines/alix1c
by svn＠coreboot.org 29 Feb '08

29 Feb '08

Author: rminnich Date: 2008-02-29 17:53:34 +0100 (Fri, 29 Feb 2008) New Revision: 626 Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile Log: Get rid of the conditional; this board always has PIRQ tables. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/pcengines/alix1c/Makefile =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-02-28 23:59:09 UTC (rev 625) +++ coreboot-v3/mainboard/pcengines/alix1c/Makefile 2008-02-29 16:53:34 UTC (rev 626) @@ -25,12 +25,8 @@ $(src)/northbridge/amd/geodelx/raminit.c \ $(src)/arch/x86/geodelx/geodelx.c -STAGE2_MAINBOARD_OBJ = +STAGE2_MAINBOARD_OBJ = irq_tables.o -ifeq ($(CONFIG_PIRQ_TABLE),y) -STAGE2_MAINBOARD_OBJ += irq_tables.o -endif - $(obj)/coreboot.vpd: $(Q)printf " BUILD DUMMY VPD\n" $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)

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dbe61 patch
by ron minnich 29 Feb '08

29 Feb '08

ron

3 3

Probe missing on W49F002U
by Jun Ma 29 Feb '08

29 Feb '08

Hi, all. I downloaded flashrom from http://www.openbios.org/viewvc/trunk/util/flashrom.tar.gz?view=tar, also it was built correctly, when I scp it to an SIS530/SIS5595 board with debian-4.0r2, it just can't recognize my Winbond W49G002U EEPROM, here comes the verbose log: Sis530:~# ./flashrom -c W49F002U Calibrating delay loop... OK. No coreboot table found. Found chipset "SIS5595", enabling flash write... OK. No EEPROM/flash device found. Sis530:~# ./flashrom -R flashrom r Sis530:~# ./flashrom --version flashrom r Sis530:~# ./flashrom -V -r Calibrating delay loop... 59M loops per second. OK. No coreboot table found. Found chipset "SIS5595", enabling flash write... OK. Probing for Am29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29LV040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for Am29F016D, 2048 KB probe_29f040b: id1 0xff, id2 0xff Probing for AE49F2008, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for At29C020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At49F002(N), 256 KB probe_jedec: id1 0xff, id2 0xff Probing for At49F002(N)T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for EN29F002(A)(N)T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for EN29F002(A)(N)B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for MBM29F400TC, 512 KB probe_m29f400bt: id1 0xff, id2 0xff Probing for MX29F002, 256 KB probe_29f002: id1 0xff, id2 0xff Probing for MX25L4005, 512 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L8005, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for MX25L3205, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for S25FL016A, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF040B, 512 KB generic_spi_command called, but no SPI chipset detected Probing for SST25VF016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for SST29EE020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST28SF040A, 512 KB probe_28sf040: id1 0xff, id2 0xff Probing for SST39SF010A, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39SF040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST39VF020, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF020A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF002A/B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF003A/B, 384 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004A/B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF008A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for SST49LF004C, 512 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF008C, 1024 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF016C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST49LF160C, 2048 KB probe_49lfxxxc: id1 0xff, id2 0xff Probing for Pm49FL002, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for Pm49FL004, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for Pm25LV512, 64 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV010, 128 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV020, 256 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV040, 512 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV080B, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for Pm25LV016B, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for W29C011, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C040P, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W29C020C, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W29EE011, 128 KB probe_w29ee011: id1 0xff, id2 0xff Probing for W49F002U, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W49V002A, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W49V002FA, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040FA, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for W39V080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for W25x10, 128 KB generic_spi_command called, but no SPI chipset detected Probing for W25x20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for W25x40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for W25x80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M29F002B, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW040, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F002T/NT, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F400BT, 512 KB probe_m29f400bt: id1 0xff, id2 0xff Probing for M50FLW040A, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW040B, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080A, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FLW080B, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW080, 1024 KB probe_jedec: id1 0xff, id2 0xff Probing for M50FW016, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M50LPW116, 2048 KB probe_jedec: id1 0xff, id2 0xff Probing for M29W010B, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for M29F040B, 512 KB probe_29f040b: id1 0xff, id2 0xff Probing for M25P05-A, 64 KB generic_spi_command called, but no SPI chipset detected Probing for M25P10-A, 128 KB generic_spi_command called, but no SPI chipset detected Probing for M25P20, 256 KB generic_spi_command called, but no SPI chipset detected Probing for M25P40, 512 KB generic_spi_command called, but no SPI chipset detected Probing for M25P80, 1024 KB generic_spi_command called, but no SPI chipset detected Probing for M25P16, 2048 KB generic_spi_command called, but no SPI chipset detected Probing for M25P32, 4096 KB generic_spi_command called, but no SPI chipset detected Probing for M25P64, 8192 KB generic_spi_command called, but no SPI chipset detected Probing for M25P128, 16384 KB generic_spi_command called, but no SPI chipset detected Probing for 82802ab, 512 KB probe_82802ab: id1 0xff, id2 0xff Probing for 82802ac, 1024 KB probe_82802ab: id1 0xff, id2 0xff Probing for F49B002UA, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for LHF00L04, 1024 KB probe_lhf00l04: id1 0xff, id2 0xff Probing for S29C51001T, 128 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51002T, 256 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C51004T, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for S29C31004T, 512 KB probe_jedec: id1 0xff, id2 0xff Probing for EON unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for MX unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for PMC unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for SST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected Probing for ST unknown SPI chip, 0 KB WARNING: size: 0 -> 4096 (page size) generic_spi_command called, but no SPI chipset detected No EEPROM/flash device found. Sis530:~# After quick reading of your source code, I saw this probing function: int probe_jedec(struct flashchip *flash) { volatile uint8_t *bios = flash->virtual_memory; uint8_t id1, id2; uint32_t largeid1, largeid2; /* Issue JEDEC Product ID Entry command */ *(volatile uint8_t *)(bios + 0x5555) = 0xAA; myusec_delay(10); *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0x90; /* Older chips may need up to 100 us to respond. The ATMEL 29C020 * needs 10 ms according to the data sheet, but it has been tested * to work reliably with 20 us. Allow a factor of 2 safety margin. */ myusec_delay(40); /* Read product ID */ id1 = *(volatile uint8_t *)bios; id2 = *(volatile uint8_t *)(bios + 0x01); largeid1 = id1; largeid2 = id2; /* Check if it is a continuation ID, this should be a while loop. */ if (id1 == 0x7F) { largeid1 <<= 8; id1 = *(volatile uint8_t *)(bios + 0x100); largeid1 |= id1; } if (id2 == 0x7F) { largeid2 <<= 8; id2 = *(volatile uint8_t *)(bios + 0x101); largeid2 |= id2; } /* Issue JEDEC Product ID Exit command */ *(volatile uint8_t *)(bios + 0x5555) = 0xAA; myusec_delay(10); *(volatile uint8_t *)(bios + 0x2AAA) = 0x55; myusec_delay(10); *(volatile uint8_t *)(bios + 0x5555) = 0xF0; myusec_delay(40); printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, largeid1, largeid2); if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) return 1; return 0; } Seems flashrom routing got 0xff, 0xff on largeid1, largeid2. Has anybody tested this routing on SIS530? Thanks. Jun.

1 0

r3119 build service
by coreboot information 29 Feb '08

29 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "duwe" checked in revision 3119 to the coreboot source repository and caused the following changes: Change Log: In pci_device.c, the class for VGA was not tested properly, leading to no VGA output from coreboot, even after the boot-rom was executed properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the class field of struct device is '3 bytes: (base,sub,prog-if)'. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Torsten Duwe <duwe(a)lst.de> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3119&device=serengeti_chee… If something broke during this checkin please be a pain in duwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r625 - coreboot-v3/mainboard/artecgroup/dbe62
by svn＠coreboot.org 29 Feb '08

29 Feb '08

Author: rminnich Date: 2008-02-29 00:59:09 +0100 (Fri, 29 Feb 2008) New Revision: 625 Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c Log: per a good suggestion, use the common struct. Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/mainboard/artecgroup/dbe62/stage1.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-02-28 23:13:01 UTC (rev 624) +++ coreboot-v3/mainboard/artecgroup/dbe62/stage1.c 2008-02-28 23:59:09 UTC (rev 625) @@ -30,22 +30,20 @@ #include <amd_geodelx.h> #include <southbridge/amd/cs5536/cs5536.h> #include <northbridge/amd/geodelx/raminit.h> +#include <arch/x86/msr.h> -static const struct wmsr { - u32 reg; - struct msr msr; -} dbe62_msr[] = { - {.reg = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}}, - {.reg = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}}, - {.reg = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}}, - {.reg = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}}, +static const struct msrinit dbe62_msr[] = { + {.msrnum = 0x10000020, {.lo = 0x00fff80, .hi = 0x20000000}}, + {.msrnum = 0x10000021, {.lo = 0x80fffe0, .hi = 0x20000000}}, + {.msrnum = 0x40000020, {.lo = 0x00fff80, .hi = 0x20000000}}, + {.msrnum = 0x40000021, {.lo = 0x80fffe0, .hi = 0x20000000}}, }; static void dbe62_msr_init(void) { int i; for (i = 0; i < ARRAY_SIZE(dbe62_msr); i++) - wrmsr(dbe62_msr[i].reg, dbe62_msr[i].msr); + wrmsr(dbe62_msr[i].msrnum, dbe62_msr[i].msr); } void hardware_stage1(void)

1 0

[patch] PCI class test for VGA
by Ronald Hoogenboom 29 Feb '08

29 Feb '08

Hi, In pci_device.c, the class for VGA was not tested properly, leading to no VGA output from coreboot, even after the boot-rom was executed properly (CONFIG_PCI_ROM_RUN) or no boot-rom execution with CONFIG_VGA_ROM_RUN at all. According to the header file device.h, the class field of struct device is '3 bytes: (base,sub,prog-if)'. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl>

3 4

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coreboot February 2008