coreboot February 2008

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Some work on the cn700 ram init
by Corey Osgood 27 Feb '08

27 Feb '08

It isn't quite complete, but there's a couple fairly important bits in there. I'm trying to reconstruct a lot of the work I've done in the last few months from memory, so bear with me ;)

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r622 - in coreboot-v3/mainboard: artecgroup/dbe61 artecgroup/dbe62 pcengines/alix1c
by svn＠coreboot.org 27 Feb '08

27 Feb '08

Author: rminnich Date: 2008-02-27 06:27:51 +0100 (Wed, 27 Feb 2008) New Revision: 622 Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c coreboot-v3/mainboard/artecgroup/dbe62/initram.c coreboot-v3/mainboard/pcengines/alix1c/initram.c Log: Convert all boards using fake SPD entries to struct spd_entry, thereby making sure we return 0xff for nonexisiting entries and shrinking the data structure by 85%. As a bonus, the various initram.c for boards with fake SPD are now almost identical. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Tested on Alix1c, with minor mods to get it to compile. Full boot to Linux, with graphics. Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/artecgroup/dbe61/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-02-25 22:56:08 UTC (rev 621) +++ coreboot-v3/mainboard/artecgroup/dbe61/initram.c 2008-02-27 05:27:51 UTC (rev 622) @@ -55,41 +55,59 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* SPD array */ -static const u8 spdbytes[] = { - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, - [SPD_BANK_DENSITY] = 0x40, - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, - [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ - [SPD_NUM_BANKS_PER_SDRAM] = 4, - [SPD_PRIMARY_SDRAM_WIDTH] = 8, - [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ - [SPD_NUM_COLUMNS] = 0xa, - [SPD_NUM_ROWS] = 3, - [SPD_REFRESH] = 0x3a, - [SPD_SDRAM_CYCLE_TIME_2ND] = 60, - [SPD_SDRAM_CYCLE_TIME_3RD] = 75, - [SPD_tRAS] = 40, - [SPD_tRCD] = 15, - [SPD_tRFC] = 70, - [SPD_tRP] = 15, - [SPD_tRRD] = 10, + +struct spd_entry { + u8 address; + u8 data; }; +/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ u8 spd_read_byte(u16 device, u8 address) { + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - - if (device != (0x50 << 1)) { - printk(BIOS_DEBUG, " returns 0xff\n"); - return 0xff; + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + } + } } - printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); - - return spdbytes[address]; + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; } /** Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c =================================================================== --- coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-02-25 22:56:08 UTC (rev 621) +++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c 2008-02-27 05:27:51 UTC (rev 622) @@ -45,36 +45,35 @@ * @ 200 ns, data-out window, 1.6; access, +- 70 ns; dqs-dq skew: .4ns * http://www.micron.com/products/partdetail?part=MT46V16M16P-5B */ + struct spd_entry { u8 address; u8 data; }; /* Save space by using a short list of SPD values used by Geode LX Memory init */ - -static const struct spd_entry spdbytes[] = { - {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, - {SPD_BANK_DENSITY, 0x40}, - {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, - {SPD_MEMORY_TYPE, 7}, - {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10, /* A guess for the tRAC value */ - {SPD_MODULE_ATTRIBUTES, 0xff, /* FIXME later when we figure out. */ - {SPD_NUM_BANKS_PER_SDRAM, 4}, - {SPD_PRIMARY_SDRAM_WIDTH, 8}, - {SPD_NUM_DIMM_BANKS, 1}, - {SPD_NUM_COLUMNS, 0xa}, - {SPD_NUM_ROWS, 3}, - {SPD_REFRESH, 0x3a}, - {SPD_SDRAM_CYCLE_TIME_2ND, 60}, - {SPD_SDRAM_CYCLE_TIME_3RD, 75}, - {SPD_tRAS, 40}, - {SPD_tRCD, 15}, - {SPD_tRFC, 70}, - {SPD_tRP, 15}, - {SPD_tRRD, 10, +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, }; - /** * Given an SMBUS device, and an address in that device, return the value of SPD * for that device. In this mainboard, the only one that can return is DIMM0. @@ -82,16 +81,16 @@ * @param address The address in SPD rom to return the value of * @returns The value */ -static u8 spd_read_byte(u16 device, u8 address) +u8 spd_read_byte(u16 device, u8 address) { int i; /* returns 0xFF on any failures */ u8 ret = 0xff; printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - if (device == DIMM0){ - for (i=0; i < (sizeof spd_table/sizeof spd_table[0]); i++){ - if (spd_table[i].address == address){ + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { ret = spd_table[i].data; } } Modified: coreboot-v3/mainboard/pcengines/alix1c/initram.c =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-02-25 22:56:08 UTC (rev 621) +++ coreboot-v3/mainboard/pcengines/alix1c/initram.c 2008-02-27 05:27:51 UTC (rev 622) @@ -55,41 +55,59 @@ * Lead Free (P) * DDR400 3-3-3 (D43) */ -/* SPD array */ -static const u8 spdbytes[] = { - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x10, - [SPD_BANK_DENSITY] = 0x40, - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0xff, - [SPD_MEMORY_TYPE] = 7, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 10, /* A guess for the tRAC value */ - [SPD_MODULE_ATTRIBUTES] = 0xff, /* FIXME later when we figure out. */ - [SPD_NUM_BANKS_PER_SDRAM] = 4, - [SPD_PRIMARY_SDRAM_WIDTH] = 8, - [SPD_NUM_DIMM_BANKS] = 1, /* ALIX1.C is 1 bank. */ - [SPD_NUM_COLUMNS] = 0xa, - [SPD_NUM_ROWS] = 3, - [SPD_REFRESH] = 0x3a, - [SPD_SDRAM_CYCLE_TIME_2ND] = 60, - [SPD_SDRAM_CYCLE_TIME_3RD] = 75, - [SPD_tRAS] = 40, - [SPD_tRCD] = 15, - [SPD_tRFC] = 70, - [SPD_tRP] = 15, - [SPD_tRRD] = 10, + +struct spd_entry { + u8 address; + u8 data; }; +/* Save space by using a short list of SPD values used by Geode LX Memory init */ +static const struct spd_entry spd_table[] = { + {SPD_ACCEPTABLE_CAS_LATENCIES, 0x10}, + {SPD_BANK_DENSITY, 0x40}, + {SPD_DEVICE_ATTRIBUTES_GENERAL, 0xff}, + {SPD_MEMORY_TYPE, 7}, + {SPD_MIN_CYCLE_TIME_AT_CAS_MAX, 10}, /* A guess for the tRAC value */ + {SPD_MODULE_ATTRIBUTES, 0xff}, /* FIXME later when we figure out. */ + {SPD_NUM_BANKS_PER_SDRAM, 4}, + {SPD_PRIMARY_SDRAM_WIDTH, 8}, + {SPD_NUM_DIMM_BANKS, 1}, /* ALIX1.C is 1 bank. */ + {SPD_NUM_COLUMNS, 0xa}, + {SPD_NUM_ROWS, 3}, + {SPD_REFRESH, 0x3a}, + {SPD_SDRAM_CYCLE_TIME_2ND, 60}, + {SPD_SDRAM_CYCLE_TIME_3RD, 75}, + {SPD_tRAS, 40}, + {SPD_tRCD, 15}, + {SPD_tRFC, 70}, + {SPD_tRP, 15}, + {SPD_tRRD, 10}, +}; + +/** + * Given an SMBUS device, and an address in that device, return the value of SPD + * for that device. In this mainboard, the only one that can return is DIMM0. + * @param device The device number + * @param address The address in SPD rom to return the value of + * @returns The value + */ u8 spd_read_byte(u16 device, u8 address) { + int i; + /* returns 0xFF on any failures */ + u8 ret = 0xff; + printk(BIOS_DEBUG, "spd_read_byte dev %04x\n", device); - - if (device != (0x50 << 1)) { - printk(BIOS_DEBUG, " returns 0xff\n"); - return 0xff; + if (device == DIMM0) { + for (i = 0; i < ARRAY_SIZE(spd_table); i++) { + if (spd_table[i].address == address) { + ret = spd_table[i].data; + } + } } - printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, spdbytes[address]); - - return spdbytes[address]; + printk(BIOS_DEBUG, " addr %02x returns %02x\n", address, ret); + return ret; } /**

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Fwd: Unable to power up db800 with coreboot
by Phani Babu Giddi 27 Feb '08

27 Feb '08

---------- Forwarded message ---------- From: Phani Babu Giddi <phanig(a)gmail.com> Date: Tue, Feb 26, 2008 at 4:55 PM Subject: Re: [coreboot] Unable to power up db800 with coreboot To: Marc Jones <marc.jones(a)amd.com> Hi Marc, Not sure if that is the case because after programming the chip I verify the contents and they are same. Btw the flash chip that I am using is Intel's N82802AB which is of the same size as the flash part that the board was shipped with SST49LF004B. One more thing, I have built coreboot manually instead of using buildrom after which i have patched vsa. Regards, Phani On Tue, Feb 26, 2008 at 2:54 PM, Marc Jones <marc.jones(a)amd.com> wrote: > > > > Phani Babu Giddi wrote: > > Hi Marc, > > > > I was able to build coreboot for db800 board using the latest codebase > > 3118 on SLES. Fedora still doesnt work for me. So I have build coreboot > > image with FILO as the payload. When I powerup the system the Linux > > image doesnt boot. On the IDE disk I have installed SLES with /boot in a > > different partition. /boot is ext2 and / is reiserfs. The system does > > nothing for a long time and after wards USB LED's on the board come up. > > > > I was expecting some messages on the serial console and the montior but > > I dont see any. Any idea whats going on. The FILO config file is as > > shown below, i hope I am not passing incorrect parameters here.... > > > > Regards, > > Phani > > Phani, > > This seems like the ROM didn't get programmed correctly. You should get > something on the serial port. Note I think that there is a errata on > some db800s where the serial doesn't work on a reset (should work from > power off). Information should be available from Logic. > > Marc > > -- > Marc Jones > Senior Firmware Engineer > (970) 226-9684 Office > mailto:Marc.Jones@amd.com > http://www.amd.com/embeddedprocessors > > >

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new K8/K10 rev guides!
by Rudolf Marek 27 Feb '08

27 Feb '08

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, Just FYI: Revision Guide for AMD Athlon™ 64 and AMD Opteron™ Processors http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/257… Revision Guide for AMD NPT Family 0Fh Processors http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/336… Revision Guide for AMD Family 10h Processors http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/413… Especially for family 0xf really nice - the old was TWO years old. Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHxKKk3J9wPJqZRNURAhRXAKDirYnl30/1dpE6muQpLlP63B9wkACgtdPW u6xBHDeg/Cic5HrvDY3rnTY= =bvqO -----END PGP SIGNATURE-----

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Unable to power up db800 with coreboot
by Phani Babu Giddi 26 Feb '08

26 Feb '08

Hi Marc, I was able to build coreboot for db800 board using the latest codebase 3118 on SLES. Fedora still doesnt work for me. So I have build coreboot image with FILO as the payload. When I powerup the system the Linux image doesnt boot. On the IDE disk I have installed SLES with /boot in a different partition. /boot is ext2 and / is reiserfs. The system does nothing for a long time and after wards USB LED's on the board come up. I was expecting some messages on the serial console and the montior but I dont see any. Any idea whats going on. The FILO config file is as shown below, i hope I am not passing incorrect parameters here.... Regards, Phani 1. amd/db800/db800/Config.lb target db800 mainboard amd/db800 # HACK to get the right TSC support. option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0 # Leave 36k for VSA. #option ROM_SIZE=1024*1024-36*1024 option ROM_SIZE=512*1024-36*1024 # option ROM_SIZE=256*1024-36*1024 option FALLBACK_SIZE=ROM_SIZE option DEFAULT_CONSOLE_LOGLEVEL = 11 option MAXIMUM_CONSOLE_LOGLEVEL = 11 # option DEFAULT_CONSOLE_LOGLEVEL = 4 # option MAXIMUM_CONSOLE_LOGLEVEL = 4 romimage "fallback" option USE_FALLBACK_IMAGE=1 option ROM_IMAGE_SIZE=64*1024 option COREBOOT_EXTRA_VERSION=".0Fallback" payload ../payload.elf end buildrom ./coreboot.rom ROM_SIZE "fallback" 2. # !!! NOTE !!! # Do NOT add spaces or comments at the end of option lines. # It confuses some versions of make. # Use grub instead of autoboot? USE_GRUB = 1 # Grub menu.lst path MENULST_FILE = "hda1:/grub/menu.lst" # Via Epia-MII CF boot: #MENULST_FILE = "hde1:/boot/filo/menu.lst" # time before default menu.lst is chosen. Set to 0 to ignore MENULST_TIMEOUT = 10 # Image filename for automatic boot and optional command line parameter AUTOBOOT_FILE = "hda1:/vmlinuz root=/dev/hda3 vga=0x317 resume=/dev/hda2 splash=silent showopts initrd /initrd console=tty0 console=ttyS0,115200" #AUTOBOOT_FILE = "mem@0xfff80000" #AUTOBOOT_FILE = "hde1@0" #AUTOBOOT_FILE = "uda1:/vmlinuz.elf" # Time in second before booting AUTOBOOT_FILE AUTOBOOT_DELAY = 5 # Driver for hard disk, CompactFlash, and CD-ROM on IDE bus IDE_DISK = 1 # Add a short delay when polling status registers # (required on some broken SATA controllers) # NOTE: Slows down access significantly, so disable # whenever possible. #IDE_DISK_POLL_DELAY = 1 # Use PCMCIA compact flash on Via Epia MII10000 and MII6000E # This device is referred to as hde. #PCMCIA_CF = 1 # Driver for USB Storage USB_DISK = 1 # VGA text console VGA_CONSOLE = 1 PC_KEYBOARD = 1 # Serial console SERIAL_CONSOLE = 1 SERIAL_IOBASE = 0x3f8 # if SERIAL_SPEED is commented out, the speed will not be changed. SERIAL_SPEED = 115200 # Filesystems FSYS_EXT2FS = 1 FSYS_FAT = 1 #FSYS_JFS = 1 #FSYS_MINIX = 1 FSYS_REISERFS = 1 #FSYS_XFS = 1 FSYS_ISO9660 = 1 #FSYS_CRAMFS = 1 #FSYS_SQUASHFS = 1 # Support for boot disk image in bootable CD-ROM (El Torito) ELTORITO = 1 # PCI support SUPPORT_PCI = 1 # Enable this to scan PCI busses above bus 0 # AMD64 based boards do need this. PCI_BRUTE_SCAN = 1 # Sound support (needs SUPPORT_PCI) #SUPPORT_SOUND = 1 # Sound drivers #VIA_SOUND = 1 # Debugging DEBUG_ALL = 1 #DEBUG_ELFBOOT = 1 #DEBUG_ELFNOTE = 1 #DEBUG_LINUXBIOS = 1 #DEBUG_MALLOC = 1 #DEBUG_MULTIBOOT = 1 #DEBUG_SEGMENT = 1 #DEBUG_SYS_INFO = 1 #DEBUG_TIMER = 1 #DEBUG_BLOCKDEV = 1 #DEBUG_PCI = 1 #DEBUG_VIA_SOUND = 1 #DEBUG_LINUXLOAD = 1 #DEBUG_IDE = 1 #DEBUG_USB = 1 #DEBUG_ELTORITO = 1 # i386 options # Loader for standard Linux kernel image, a.k.a. /vmlinuz LINUX_LOADER = 1 # Boot FILO from Multiboot loader (eg. GRUB) #MULTIBOOT_IMAGE = 1

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EFI strategy
by Carl-Daniel Hailfinger 26 Feb '08

26 Feb '08

Hi, when promoting LinuxBIOS over the last few months I almost invariably got the response: "Why would anyone want to create a new BIOS? EFI is the future." EFI marketing seems to have successfully convinced many people by simple repetition of their "EFI is the future" campaign. Back when we had the dreaded "BIOS" in the project name it was almost impossible to get the message across that we had the most modern concept and codebase. Now is the time for change. CHANGE! Let's use EFI marketing for our own advantage and add some new marketing in EFI style to our public image. Suggestions: - "The EFI proponents are right. BIOS is a thing of the past." - "EFI has been superseded by Coreboot. Of course Coreboot has a backwards compatible EFI emulation for systems stuck with a solution from the 90s." - "Coreboot is able to run legacy code like EFI and BIOS, but who would want that?" To be fair to EFI, it was a good idea back in 1995, but we live in 2008 and have to be realistic about the "future" of EFI. Regards, Carl-Daniel -- http://www.hailfinger.org/

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Fan settings testing procedure
by Carl-Daniel Hailfinger 26 Feb '08

26 Feb '08

Hi, On 26.02.2008 05:36, svn(a)coreboot.org wrote: > Author: ward > New Revision: 3118 > > Log: > Temporarily disable the fan control patch from this morning; it turns out to > stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than > desirable. I did not notice before because my board ran fine for about 15 > minutes before the CPU overheated. > The disaster mentioned above shall never repeat. We need a testing procedure which ensures that a board does not overheat. Mprime (Linux variant of Prime95) should be a nice CPU head generator. Together with reading out the K8 internal temperature every 20 seconds, running Mprime for half an hour should definitely detect CPU overheating problems. Regards, Carl-Daniel -- http://www.hailfinger.org/

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patch: add zero fill command option to lar
by ron minnich 26 Feb '08

26 Feb '08

You can now say: lar z build/bios.bin and get a zero-filled lar entry. The "zeros" are actually 0xff, which is flash-friendly and makes flashrom fast. Parts of stream.c could use the new functions, in particular hlen, but that patch is for later. This change dramatically speeds up booting on the alix 1c. ron

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r3118 build service
by coreboot information 26 Feb '08

26 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ward" checked in revision 3118 to the coreboot source repository and caused the following changes: Change Log: Temporarily disable the fan control patch from this morning; it turns out to stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than desirable. I did not notice before because my board ran fine for about 15 minutes before the CPU overheated. Thankfully the board has a good failsafe mode - it just switches off when the CPU gets too hot, without permanent damage. I'm debugging this and plan to commit a proper fix later in the week. This is not really trivial, but the tree is dangerous in the current state so I'm self-acking. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3118&device=serengeti_chee… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r134 - buildrom-devel/config/platforms
by svn＠coreboot.org 26 Feb '08

26 Feb '08

Author: ward Date: 2008-02-26 05:38:29 +0100 (Tue, 26 Feb 2008) New Revision: 134 Modified: buildrom-devel/config/platforms/m57sli.conf Log: Bump up version to go back to the old fan control code for m57sli until we fix the code for the PLCC version of the board, too. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/m57sli.conf =================================================================== --- buildrom-devel/config/platforms/m57sli.conf 2008-02-25 20:13:09 UTC (rev 133) +++ buildrom-devel/config/platforms/m57sli.conf 2008-02-26 04:38:29 UTC (rev 134) @@ -41,7 +41,7 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf CBV2_TDIR=m57sli -CBV2_TAG=3116 +CBV2_TAG=3118 # FILO configuration

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coreboot February 2008