coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

r3118 - trunk/coreboot-v2/src/superio/ite/it8716f
by svn＠coreboot.org 26 Feb '08

26 Feb '08

Author: ward Date: 2008-02-26 05:36:52 +0100 (Tue, 26 Feb 2008) New Revision: 3118 Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c Log: Temporarily disable the fan control patch from this morning; it turns out to stop the CPU fan on the m57sli v1.1 (PLCC) entirely, which is less than desirable. I did not notice before because my board ran fine for about 15 minutes before the CPU overheated. Thankfully the board has a good failsafe mode - it just switches off when the CPU gets too hot, without permanent damage. I'm debugging this and plan to commit a proper fix later in the week. This is not really trivial, but the tree is dangerous in the current state so I'm self-acking. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-02-25 22:32:41 UTC (rev 3117) +++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-02-26 04:36:52 UTC (rev 3118) @@ -62,9 +62,9 @@ return inb(port_base + 1); } -#ifdef HAVE_FANCTL +/* #ifdef HAVE_FANCTL extern void init_ec(uint16_t base); -#else +#else */ static void init_ec(uint16_t base) { uint8_t value; @@ -80,7 +80,7 @@ printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", base + 0x14, value | 0x87); } -#endif +//#endif static void it8716f_init(device_t dev) {

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Re: [coreboot] amd/db800 build failure on Fedora 8
by Phani Babu Giddi 26 Feb '08

26 Feb '08

Hi Marc, In the last mail I forgot to CC it to coreboot. ldscript.ld for fallback is attached. Regards, Phani On Thu, Feb 21, 2008 at 5:06 PM, Phani Babu Giddi <phanig(a)gmail.com> wrote: > Hi Marc, > > Here is a log of messages. I tried using buildrom and was seeing the same > error. In this case I have build filo and core boot separately. > > make[1]: Entering directory > `/home/dev1/fabric/coreboot-v2/targets/amd/db800/db800/fallback' > gcc -m32 -x assembler-with-cpp -DASSEMBLY -E ... crt0.S > crt0.s > gcc -m32 -x assembler-with-cpp -DASSEMBLY -E > -I/home/dev1/fabric/coreboot-v2/src/include > -I/home/dev1/fabric/coreboot-v2/src/arch/i386/include > -I/usr/lib/gcc/i386-redhat-linux/4.1.2/include -DARCH='i386' > -DHAVE_MOVNTI='0' -DCROSS_COMPILE -DCC='gcc -m32' -DHOSTCC='gcc' > -DOBJCOPY='objcopy --gap-fill 0xff' -DCOREBOOT_VERSION='"2.0.0"' > -DCOREBOOT_BUILD='"Thu Feb 21 17:02:02 PST 2008"' > -DCOREBOOT_COMPILE_TIME='"17:02:02"' -DCOREBOOT_COMPILE_BY='"dev1"' > -DCOREBOOT_COMPILE_HOST='"localhost.localdomain"' > -DCOREBOOT_COMPILE_DOMAIN='"localdomain"' -DCOREBOOT_COMPILER='"gcc version > 4.1.2 20070925 (Red Hat 4.1.2-33)"' -DCOREBOOT_LINKER='"the GNU General > Public License version 3 or (at your option) a later version."' > -DCOREBOOT_ASSEMBLER='"GNU assembler version 2.18.50.0.3(i386-redhat-linux) using BFD version version > 2.18.50.0.3-1 20071102"' -DCONFIG_USE_INIT='0' -DHAVE_FALLBACK_BOOT='1' > -DHAVE_FAILOVER_BOOT='0' -DROM_IMAGE_SIZE='0x10000' -DPAYLOAD_SIZE='0x67000' > -D_ROMBASE='0xffff0000' -D_RESET='0xffff0000' > -D_EXCEPTION_VECTORS='0xffff0100' -DSTACK_SIZE='0x2000' -DHEAP_SIZE='0x4000' > -D_RAMBASE='0x4000' -DUSE_DCACHE_RAM='1' -DCAR_FAM10='0' > -DDCACHE_RAM_BASE='0xc8000' -DDCACHE_RAM_SIZE='0x8000' > -DDCACHE_RAM_GLOBAL_VAR_SIZE='0x0' -DCONFIG_AP_CODE_IN_CAR='0' > -DMEM_TRAIN_SEQ='0' -DWAIT_BEFORE_CPUS_INIT='0' -DCONFIG_COMPRESS='1' > -DCONFIG_UNCOMPRESSED='0' -DCONFIG_LB_MEM_TOPK='2048' > -DHAVE_OPTION_TABLE='0' -DUSE_OPTION_TABLE='0' -DLB_CKS_RANGE_START='49' > -DLB_CKS_RANGE_END='125' -DLB_CKS_LOC='126' > -DCRT0='/home/dev1/fabric/coreboot-v2/src/arch/i386/init/crt0.S.lb' > -DDEBUG='1' -DCONFIG_CONSOLE_VGA='0' -DCONFIG_CONSOLE_VGA_MULTI='0' > -DCONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST='0' -DCONFIG_CONSOLE_BTEXT='0' > -DCONFIG_CONSOLE_LOGBUF='0' -DCONFIG_CONSOLE_SROM='0' > -DCONFIG_CONSOLE_SERIAL8250='1' -DCONFIG_USBDEBUG_DIRECT='0' > -DDEFAULT_CONSOLE_LOGLEVEL='11' -DMAXIMUM_CONSOLE_LOGLEVEL='11' > -DCONFIG_SERIAL_POST='0' -DTTYS0_BASE='0x3f8' -DTTYS0_BAUD='115200' > -DTTYS0_LCS='0x3' -DCONFIG_USE_PRINTK_IN_CAR='0' > -DMAINBOARD='/home/dev1/fabric/coreboot-v2/src/mainboard/amd/db800' > -DMAINBOARD_PART_NUMBER='"db800"' -DMAINBOARD_VENDOR='"amd"' > -DMAINBOARD_PCI_SUBSYSTEM_VENDOR_ID='0' > -DMAINBOARD_PCI_SUBSYSTEM_DEVICE_ID='0x0' -DCONFIG_MAX_PCI_BUSES='255' > -DCONFIG_SMP='0' -DCONFIG_MAX_CPUS='1' -DCONFIG_MAX_PHYSICAL_CPUS='1' > -DCONFIG_LOGICAL_CPUS='0' -DSERIAL_CPU_INIT='1' -DAPIC_ID_OFFSET='0' > -DENABLE_APIC_EXT_ID='0' -DLIFT_BSP_APIC_ID='0' -DCONFIG_IDE_PAYLOAD='0' > -DCONFIG_ROM_PAYLOAD='1' -DCONFIG_ROM_PAYLOAD_START='0xfff89000' > -DCONFIG_COMPRESSED_PAYLOAD_NRV2B='0' -DCONFIG_COMPRESSED_PAYLOAD_LZMA='0' > -DCONFIG_PRECOMPRESSED_PAYLOAD='0' -DCONFIG_SERIAL_PAYLOAD='0' > -DCONFIG_FS_PAYLOAD='0' -DCONFIG_FS_EXT2='0' -DCONFIG_FS_ISO9660='0' > -DCONFIG_FS_FAT='0' -DAUTOBOOT_DELAY='2' -DAUTOBOOT_CMDLINE='"hdc1:/vmlinuz > root=/dev/hdc3 console=tty0 console=ttyS0,115200"' > -DUSE_WATCHDOG_ON_BOOT='0' -DCONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT='1' > -DCONFIG_AGP_PLUGIN_SUPPORT='1' -DCONFIG_CARDBUS_PLUGIN_SUPPORT='1' > -DCONFIG_PCIX_PLUGIN_SUPPORT='1' -DCONFIG_PCIEXP_PLUGIN_SUPPORT='1' > -DCONFIG_IDE='0' -DIDE_BOOT_DRIVE='0' -DIDE_OFFSET='0' -DPCI_IO_CFG_EXT='0' > -DCONFIG_CHIP_NAME='0' -DHAVE_INIT_TIMER='1' -DMAX_REBOOT_CNT='3' > -DFAKE_SPDROM='0' -DHAVE_ACPI_TABLES='0' -DACPI_SSDTX_NUM='0' > -DHT_CHAIN_UNITID_BASE='1' -DHT_CHAIN_END_UNITID_BASE='32' > -DSB_HT_CHAIN_UNITID_OFFSET_ONLY='1' -DSB_HT_CHAIN_ON_BUS0='0' > -DPCI_BUS_SEGN_BITS='0' -DMMCONF_SUPPORT='0' -DMMCONF_SUPPORT_DEFAULT='0' > -DHW_MEM_HOLE_SIZEK='0' -DHW_MEM_HOLE_SIZE_AUTO_INC='0' > -DCONFIG_VAR_MTRR_HOLE='1' -DK8_HT_FREQ_1G_SUPPORT='0' > -DK8_REV_F_SUPPORT='0' -DCBB='0' -DCDB='24' -DHT3_SUPPORT='0' > -DEXT_RT_TBL_SUPPORT='0' -DEXT_CONF_SUPPORT='0' -DDIMM_SUPPORT='0x108' > -DCPU_SOCKET_TYPE='16' -DCPU_ADDR_BITS='36' -DCONFIG_VGA_ROM_RUN='0' > -DCONFIG_PCI_ROM_RUN='0' -DCONFIG_PCI_64BIT_PREF_MEM='0' -DCONFIG_AMDMCT='0' > -DHAVE_MP_TABLE='0' -DHAVE_PIRQ_TABLE='1' -DUSE_FALLBACK_IMAGE='1' > -DHAVE_HARD_RESET='0' -DIRQ_SLOT_COUNT='4' > -DCOREBOOT_EXTRA_VERSION='".0Fallback"' -DFALLBACK_SIZE='0x77000' > -DROM_SIZE='0x77000' -DROM_SECTION_SIZE='0x77000' -DROM_SECTION_OFFSET='0x0' > -DXIP_ROM_SIZE='0x10000' -DXIP_ROM_BASE='0xffff0000' -DCONFIG_UDELAY_TSC='1' > -DCONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2='1' -DCONFIG_VIDEO_MB='8' > -DCONFIG_UDELAY_IO='0' -DUSE_FAILOVER_IMAGE='0' -I. > -I/home/dev1/fabric/coreboot-v2/src crt0.S > crt0.s.new && mv crt0.s.new > crt0.s > gcc -m32 ... -o crt0.o crt0.s > gcc -m32 -c -fno-stack-protector > -I/home/dev1/fabric/coreboot-v2/src/include > -I/home/dev1/fabric/coreboot-v2/src/arch/i386/include > -I/usr/lib/gcc/i386-redhat-linux/4.1.2/include -DARCH='i386' > -DHAVE_MOVNTI='0' -DCROSS_COMPILE -DCC='gcc -m32' -DHOSTCC='gcc' > -DOBJCOPY='objcopy --gap-fill 0xff' -DCOREBOOT_VERSION='"2.0.0"' > -DCOREBOOT_BUILD='"Thu Feb 21 17:02:02 PST 2008"' > -DCOREBOOT_COMPILE_TIME='"17:02:02"' -DCOREBOOT_COMPILE_BY='"dev1"' > -DCOREBOOT_COMPILE_HOST='"localhost.localdomain"' > -DCOREBOOT_COMPILE_DOMAIN='"localdomain"' -DCOREBOOT_COMPILER='"gcc version > 4.1.2 20070925 (Red Hat 4.1.2-33)"' -DCOREBOOT_LINKER='"the GNU General > Public License version 3 or (at your option) a later version."' > -DCOREBOOT_ASSEMBLER='"GNU assembler version 2.18.50.0.3(i386-redhat-linux) using BFD version version > 2.18.50.0.3-1 20071102"' -DCONFIG_USE_INIT='0' -DHAVE_FALLBACK_BOOT='1' > -DHAVE_FAILOVER_BOOT='0' -DROM_IMAGE_SIZE='0x10000' -DPAYLOAD_SIZE='0x67000' > -D_ROMBASE='0xffff0000' -D_RESET='0xffff0000' > -D_EXCEPTION_VECTORS='0xffff0100' -DSTACK_SIZE='0x2000' -DHEAP_SIZE='0x4000' > -D_RAMBASE='0x4000' -DUSE_DCACHE_RAM='1' -DCAR_FAM10='0' > -DDCACHE_RAM_BASE='0xc8000' -DDCACHE_RAM_SIZE='0x8000' > -DDCACHE_RAM_GLOBAL_VAR_SIZE='0x0' -DCONFIG_AP_CODE_IN_CAR='0' > -DMEM_TRAIN_SEQ='0' -DWAIT_BEFORE_CPUS_INIT='0' -DCONFIG_COMPRESS='1' > -DCONFIG_UNCOMPRESSED='0' -DCONFIG_LB_MEM_TOPK='2048' > -DHAVE_OPTION_TABLE='0' -DUSE_OPTION_TABLE='0' -DLB_CKS_RANGE_START='49' > -DLB_CKS_RANGE_END='125' -DLB_CKS_LOC='126' > -DCRT0='/home/dev1/fabric/coreboot-v2/src/arch/i386/init/crt0.S.lb' > -DDEBUG='1' -DCONFIG_CONSOLE_VGA='0' -DCONFIG_CONSOLE_VGA_MULTI='0' > -DCONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST='0' -DCONFIG_CONSOLE_BTEXT='0' > -DCONFIG_CONSOLE_LOGBUF='0' -DCONFIG_CONSOLE_SROM='0' > -DCONFIG_CONSOLE_SERIAL8250='1' -DCONFIG_USBDEBUG_DIRECT='0' > -DDEFAULT_CONSOLE_LOGLEVEL='11' -DMAXIMUM_CONSOLE_LOGLEVEL='11' > -DCONFIG_SERIAL_POST='0' -DTTYS0_BASE='0x3f8' -DTTYS0_BAUD='115200' > -DTTYS0_LCS='0x3' -DCONFIG_USE_PRINTK_IN_CAR='0' > -DMAINBOARD='/home/dev1/fabric/coreboot-v2/src/mainboard/amd/db800' > -DMAINBOARD_PART_NUMBER='"db800"' -DMAINBOARD_VENDOR='"amd"' > -DMAINBOARD_PCI_SUBSYSTEM_VENDOR_ID='0' > -DMAINBOARD_PCI_SUBSYSTEM_DEVICE_ID='0x0' -DCONFIG_MAX_PCI_BUSES='255' > -DCONFIG_SMP='0' -DCONFIG_MAX_CPUS='1' -DCONFIG_MAX_PHYSICAL_CPUS='1' > -DCONFIG_LOGICAL_CPUS='0' -DSERIAL_CPU_INIT='1' -DAPIC_ID_OFFSET='0' > -DENABLE_APIC_EXT_ID='0' -DLIFT_BSP_APIC_ID='0' -DCONFIG_IDE_PAYLOAD='0' > -DCONFIG_ROM_PAYLOAD='1' -DCONFIG_ROM_PAYLOAD_START='0xfff89000' > -DCONFIG_COMPRESSED_PAYLOAD_NRV2B='0' -DCONFIG_COMPRESSED_PAYLOAD_LZMA='0' > -DCONFIG_PRECOMPRESSED_PAYLOAD='0' -DCONFIG_SERIAL_PAYLOAD='0' > -DCONFIG_FS_PAYLOAD='0' -DCONFIG_FS_EXT2='0' -DCONFIG_FS_ISO9660='0' > -DCONFIG_FS_FAT='0' -DAUTOBOOT_DELAY='2' -DAUTOBOOT_CMDLINE='"hdc1:/vmlinuz > root=/dev/hdc3 console=tty0 console=ttyS0,115200"' > -DUSE_WATCHDOG_ON_BOOT='0' -DCONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT='1' > -DCONFIG_AGP_PLUGIN_SUPPORT='1' -DCONFIG_CARDBUS_PLUGIN_SUPPORT='1' > -DCONFIG_PCIX_PLUGIN_SUPPORT='1' -DCONFIG_PCIEXP_PLUGIN_SUPPORT='1' > -DCONFIG_IDE='0' -DIDE_BOOT_DRIVE='0' -DIDE_OFFSET='0' -DPCI_IO_CFG_EXT='0' > -DCONFIG_CHIP_NAME='0' -DHAVE_INIT_TIMER='1' -DMAX_REBOOT_CNT='3' > -DFAKE_SPDROM='0' -DHAVE_ACPI_TABLES='0' -DACPI_SSDTX_NUM='0' > -DHT_CHAIN_UNITID_BASE='1' -DHT_CHAIN_END_UNITID_BASE='32' > -DSB_HT_CHAIN_UNITID_OFFSET_ONLY='1' -DSB_HT_CHAIN_ON_BUS0='0' > -DPCI_BUS_SEGN_BITS='0' -DMMCONF_SUPPORT='0' -DMMCONF_SUPPORT_DEFAULT='0' > -DHW_MEM_HOLE_SIZEK='0' -DHW_MEM_HOLE_SIZE_AUTO_INC='0' > -DCONFIG_VAR_MTRR_HOLE='1' -DK8_HT_FREQ_1G_SUPPORT='0' > -DK8_REV_F_SUPPORT='0' -DCBB='0' -DCDB='24' -DHT3_SUPPORT='0' > -DEXT_RT_TBL_SUPPORT='0' -DEXT_CONF_SUPPORT='0' -DDIMM_SUPPORT='0x108' > -DCPU_SOCKET_TYPE='16' -DCPU_ADDR_BITS='36' -DCONFIG_VGA_ROM_RUN='0' > -DCONFIG_PCI_ROM_RUN='0' -DCONFIG_PCI_64BIT_PREF_MEM='0' -DCONFIG_AMDMCT='0' > -DHAVE_MP_TABLE='0' -DHAVE_PIRQ_TABLE='1' -DUSE_FALLBACK_IMAGE='1' > -DHAVE_HARD_RESET='0' -DIRQ_SLOT_COUNT='4' > -DCOREBOOT_EXTRA_VERSION='".0Fallback"' -DFALLBACK_SIZE='0x77000' > -DROM_SIZE='0x77000' -DROM_SECTION_SIZE='0x77000' -DROM_SECTION_OFFSET='0x0' > -DXIP_ROM_SIZE='0x10000' -DXIP_ROM_BASE='0xffff0000' -DCONFIG_UDELAY_TSC='1' > -DCONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2='1' -DCONFIG_VIDEO_MB='8' > -DCONFIG_UDELAY_IO='0' -DUSE_FAILOVER_IMAGE='0' -Os -nostdinc -nostdlib > -fno-builtin -Wall -o version.o/home/dev1/fabric/coreboot-v2/src/lib/version.c > rm -f coreboot.a > ar cr coreboot.a malloc.o cache.o pci_ops.o smbus_ops.o memset.opci_ops_auto.o > superio.o northbridgeinit.o fallback_boot.o pciexp_device.o cpubug.o > keyboard.o pnp_device.o printk.o irq_tables.o pcix_device.o vsmsetup.o > i8259.o pci_device.o console.o delay_tsc.o elfboot.o hardwaremain.o boot.o > exception.o delay.o version.o pci_ops_mmconf.o memcmp.o secondary.o > isa-dma.o lapic_cpu_init.o hypertransport.o vtxprintf.o tables.o > grphinit.o root_device.o cardbus_device.o uart8250.o device_util.o > compute_ip_checksum.o device.o northbridge.o memcpy.o agp_device.o clog2.opirq_routing.o > memmove.o pci_ops_conf2.o pci_ops_conf1.o mc146818rtc.o coreboot_table.o > rom_stream.o c_start.o lapic.o vsprintf.o cpu.o static.o > gcc -m32 -Wl,--build-id=none -nostdlib -r -o coreboot_ram.o c_start.o > mainboard.o cs5536_ide.o uart8250_console.o cs5536.o model_lx_init.o > coreboot.a /usr/lib/gcc/i386-redhat-linux/4.1.2/libgcc.a > gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o > coreboot_ram -T /home/dev1/fabric/coreboot-v2/src/config/coreboot_ram.ld > coreboot_ram.o > nm -n coreboot_ram | sort > coreboot_ram.map > objcopy --gap-fill 0xff -O binary coreboot_ram coreboot_ram.bin > ./nrv2b e coreboot_ram.bin coreboot_ram.nrv2b > input/output = 77868/29566 = 2.634 > cp coreboot_ram.nrv2b coreboot_ram.rom > gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -static -o coreboot > -T ldscript.ld crt0.o > /usr/bin/..//bin/ld: coreboot: section `.id' can't be allocated in segment > 1 > LOAD: .id .reset > /usr/bin/..//bin/ld: final link failed: Bad value > collect2: ld returned 1 exit status > make[1]: *** [coreboot] Error 1 > make[1]: Leaving directory > `/home/dev1/fabric/coreboot-v2/targets/amd/db800/db800/fallback' > make: *** [fallback/coreboot.rom] Error 1 > > > Regards, > Phani > > > On Thu, Feb 21, 2008 at 5:01 PM, Marc Jones <Marc.Jones(a)amd.com> wrote: > > > Phani Babu Giddi wrote: > > > Hello All, > > > > > > I am trying to build coreboot for amd/db800 target with filo as the > > > payload. I am compiling this on Fedora 8 and I see that ld is > > > reporting a error ".id can't be allocated in segment 1. I have > > > installed the latest version of binutils ( three packages) and I am > > > using the latest code base so I have all the patches that were > > > submitted to fix this issue. The ld version is 2.18.50.0.3-1. > > > > > > Any idea whats going on ? > > > > > > Regards, > > > Phani > > > > Hi Phani, > > > > Can you send more output? There might be some hints to what is going on > > in the target/.../fallback/ldscript.ld file. Are you building with > > buildrom? > > > > Thanks, > > Marc > > > > > > -- > > Marc Jones > > Senior Firmware Engineer > > (970) 226-9684 Office > > mailto:Marc.Jones@amd.com > > http://www.amd.com/embeddedprocessors > > > > > > >

4 4

r3117 build service
by coreboot information 26 Feb '08

26 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "hailfinger" checked in revision 3117 to the coreboot source repository and caused the following changes: Change Log: This patch adds support to dump other registers than the primary pnp-style configuration registers, using the new option -e/--extra-dump. This patch only adds dumping of the Environmental Controller configuration registers for the IT8716f chip. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> I (Carl-Daniel) checked the data sheets of the whole IT87[012] series and although the environment controller is sometimes called fan controller, the location of the register is the same for all models. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3117&device=serengeti_chee… If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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r621 - in coreboot-v3: . arch/x86
by svn＠coreboot.org 25 Feb '08

25 Feb '08

Author: myles Date: 2008-02-25 23:56:08 +0100 (Mon, 25 Feb 2008) New Revision: 621 Modified: coreboot-v3/Kconfig coreboot-v3/arch/x86/Makefile Log: This patch adds a config option for zero-filling coreboot.rom after adding a payload. It depends on having a payload so that you can't end up with a file with no payload and no possiblility to add one. The default is no zero-filling. I also added a message "ZEROING lar -z ./coreboot.rom" Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: coreboot-v3/Kconfig =================================================================== --- coreboot-v3/Kconfig 2008-02-25 18:32:23 UTC (rev 620) +++ coreboot-v3/Kconfig 2008-02-25 22:56:08 UTC (rev 621) @@ -148,5 +148,13 @@ payload in, coreboot can not parse it. We hope to remove ELF entirely in the future. +config ZERO_AFTER_PAYLOAD + bool "Zero fill lar after adding the payload" + depends PAYLOAD_ELF + default n + help + This option speeds booting but makes it so that no further files may + be added to the lar. + endmenu Modified: coreboot-v3/arch/x86/Makefile =================================================================== --- coreboot-v3/arch/x86/Makefile 2008-02-25 18:32:23 UTC (rev 620) +++ coreboot-v3/arch/x86/Makefile 2008-02-25 22:56:08 UTC (rev 621) @@ -87,6 +87,10 @@ ../util/lar/lar $(PARSEELF) $(COMPRESSFLAG) -a \ ../coreboot.rom normal/payload; endif +ifeq ($(CONFIG_ZERO_AFTER_PAYLOAD),y) + $(Q)printf " ZEROING lar -z ./coreboot.rom\n" + $(Q)cd $(obj) && ./util/lar/lar -z ./coreboot.rom +endif $(Q)# QEMU wants bios.bin: $(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero". $(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/bios.bin)\n"

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[patch] superiotool dumps environmental controller registers too
by Ronald Hoogenboom 25 Feb '08

25 Feb '08

Hi, I've extended the ite.c part to include dumping the environmental controller register contents too. It's amazingly easy to add such things. Only IT8716f (that's the only datasheet I have at the moment). Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl>

7 16

r3117 - trunk/util/superiotool
by svn＠coreboot.org 25 Feb '08

25 Feb '08

Author: hailfinger Date: 2008-02-25 23:32:41 +0100 (Mon, 25 Feb 2008) New Revision: 3117 Modified: trunk/util/superiotool/README trunk/util/superiotool/ite.c trunk/util/superiotool/superiotool.8 trunk/util/superiotool/superiotool.c trunk/util/superiotool/superiotool.h Log: This patch adds support to dump other registers than the primary pnp-style configuration registers, using the new option -e/--extra-dump. This patch only adds dumping of the Environmental Controller configuration registers for the IT8716f chip. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> I (Carl-Daniel) checked the data sheets of the whole IT87[012] series and although the environment controller is sometimes called fan controller, the location of the register is the same for all models. Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006(a)gmx.net> Modified: trunk/util/superiotool/README =================================================================== --- trunk/util/superiotool/README 2008-02-25 19:36:20 UTC (rev 3116) +++ trunk/util/superiotool/README 2008-02-25 22:32:41 UTC (rev 3117) @@ -33,6 +33,7 @@ $ superiotool [-d] [-l] [-V] [-v] [-h] -d | --dump Dump Super I/O register contents + -e | --extra-dump Dump Secondary registers too (like EC registers etc.) -l | --list-supported Show the list of supported Super I/O chips -V | --verbose Verbose mode -v | --version Show the superiotool version @@ -95,9 +96,9 @@ Idwer Vollering <idwer_v(a)hotmail.com> Rasmus Wiman <rasmus(a)wiman.org> Robinson P. Tryon <bishop.robinson(a)gmail.com> +Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Ronald Minnich <rminnich(a)gmail.com> Stefan Reinauer <stepan(a)coresystems.de> Ulf Jordan <jordan(a)chalmers.se> Uwe Hermann <uwe(a)hermann-uwe.de> Ward Vandewege <ward(a)gnu.org> - Modified: trunk/util/superiotool/ite.c =================================================================== --- trunk/util/superiotool/ite.c 2008-02-25 19:36:20 UTC (rev 3116) +++ trunk/util/superiotool/ite.c 2008-02-25 22:32:41 UTC (rev 3117) @@ -324,6 +324,36 @@ {EOT} }; +static const struct superio_registers ec_table[] = { + {0x8716, "IT8716F", { + {NOLDN, NULL, + {0x00,0x04,0x05,0x06,0x07,0x08,0x09,0x0b,0x0c,0x10, + 0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x1b,0x1c,0x1d, + 0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39, + 0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,0x40,0x41,0x42,0x43, + 0x44,0x45,0x48,0x50,0x51,0x52,0x53,0x54,0x56,0x57, + 0x59,0x5c,EOT}, + {0x18,0x00,0x00,0x00,0x00,0x00,0x80,0x09,0x00,NANA, + NANA,NANA,0x07,0x50,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,RSVD,0x00,0x00,0x7f,0x7f,0x7f,0x00,0x00, + 0x00,0x00,EOT}}, + {NOLDN, NULL, + {0x5d,0x5e,0x5f,0x60,0x61,0x62,0x63,0x64,0x65,0x68, + 0x69,0x6a,0x6b,0x6c,0x6d,0x70,0x71,0x72,0x73,0x74, + 0x75,0x84,0x85,0x86,0x87,0x88,0x89,0x8c,0x8d,0x8e, + 0x8f,0x90,0x91,0x92,0x93,0x94,0x95,0x98,0x99,0x9a, + 0x9b,0x9c,0x9d,EOT}, + {0x00,0x00,0x00,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x7f, + 0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f,0x00,0x00, + 0x7f,NANA,NANA,NANA,NANA,0x00,0x00,0x02,0x00,0x99, + 0x99,0x7f,0x7f,0x7f,0x00,0x00,0x7f,0x7f,0x7f,0x7f, + 0x00,0x00,0x7f,EOT}}, + {EOT}}}, + {EOT} +}; + /** * IT871[01]F and IT8708F use 0x87, 0x87 * IT8761F uses 0x87, 0x61, 0x55, 0x55/0xaa @@ -368,6 +398,17 @@ chip_found = 1; dump_superio("ITE", reg_table, port, id); + + if (extra_dump) { + uint16_t ecport; + regwrite(port, 0x07, 0x04); /*EC LDN*/ + ecport = regval(port, 0x60) << 8; + ecport |= regval(port, 0x61); + ecport += 5; + + printf("Environment Controller (0x%04x)\n",ecport); + dump_superio("ITE-EC", ec_table, ecport, id); + } } void probe_idregs_ite(uint16_t port) Modified: trunk/util/superiotool/superiotool.8 =================================================================== --- trunk/util/superiotool/superiotool.8 2008-02-25 19:36:20 UTC (rev 3116) +++ trunk/util/superiotool/superiotool.8 2008-02-25 22:32:41 UTC (rev 3117) @@ -2,7 +2,7 @@ .SH NAME superiotool \- Super I/O detection tool .SH SYNOPSIS -.B superiotool \fR[\fB\-dlVvh\fR] +.B superiotool \fR[\fB\-delVvh\fR] .SH DESCRIPTION .B superiotool is a GPL'd user-space utility which can @@ -73,6 +73,16 @@ detailed information about the .BR MM " fields." .TP +.B "\-e, \-\-extra-dump" +Dump extra secondary register contents too, if available. Only in combination +with the +.B --dump +option. This option will, for instance, dump the Environmental Controller +configuration registers for the ITE IT8716f chip. The format is similar to +the output of the +.B --dump +option. +.TP .B "\-l, \-\-list-supported" List all Super I/O chips recognized by .BR superiotool ". The phrase" Modified: trunk/util/superiotool/superiotool.c =================================================================== --- trunk/util/superiotool/superiotool.c 2008-02-25 19:36:20 UTC (rev 3116) +++ trunk/util/superiotool/superiotool.c 2008-02-25 22:32:41 UTC (rev 3117) @@ -24,7 +24,7 @@ #include "superiotool.h" /* Command line options. */ -int dump = 0, verbose = 0; +int dump = 0, verbose = 0, extra_dump = 0; /* Global flag which indicates whether a chip was detected at all. */ int chip_found = 0; @@ -208,6 +208,7 @@ static const struct option long_options[] = { {"dump", no_argument, NULL, 'd'}, + {"extra-dump", no_argument, NULL, 'e'}, {"list-supported", no_argument, NULL, 'l'}, {"verbose", no_argument, NULL, 'V'}, {"version", no_argument, NULL, 'v'}, @@ -215,12 +216,15 @@ {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "dlVvh", + while ((opt = getopt_long(argc, argv, "delVvh", long_options, &option_index)) != EOF) { switch (opt) { case 'd': dump = 1; break; + case 'e': + extra_dump = 1; + break; case 'l': print_list_of_supported_chips(); exit(0); Modified: trunk/util/superiotool/superiotool.h =================================================================== --- trunk/util/superiotool/superiotool.h 2008-02-25 19:36:20 UTC (rev 3116) +++ trunk/util/superiotool/superiotool.h 2008-02-25 22:32:41 UTC (rev 3117) @@ -32,6 +32,7 @@ #define USAGE "Usage: superiotool [-d] [-l] [-V] [-v] [-h]\n\n\ -d | --dump Dump Super I/O register contents\n\ + -e | --extra-dump Dump Secondary registers too (like EC registers etc.)\n\ -l | --list-supported Show the list of supported Super I/O chips\n\ -V | --verbose Verbose mode\n\ -v | --version Show the superiotool version\n\ @@ -56,7 +57,7 @@ #define MAXNUMPORTS (6 + 1) /* Maximum number of Super I/O ports */ /* Command line parameters. */ -extern int dump, verbose; +extern int dump, verbose, extra_dump; extern int chip_found;

1 0

r3116 build service
by coreboot information 25 Feb '08

25 Feb '08

Dear coreboot readers! This is the automated build check service of coreboot. The developer "ward" checked in revision 3116 to the coreboot source repository and caused the following changes: Change Log: This patch adds automatic fan control for the CPU fan on the m57sli board. This is done via the ec_init routine in a source file in the mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been added to notify superio.c to get the ec_init externally. I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board. It works. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Ward Vandewege <ward(a)gnu.org> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3116&device=serengeti_chee… If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

r133 - buildrom-devel/config/platforms
by svn＠coreboot.org 25 Feb '08

25 Feb '08

Author: ward Date: 2008-02-25 21:13:09 +0100 (Mon, 25 Feb 2008) New Revision: 133 Modified: buildrom-devel/config/platforms/m57sli.conf Log: Bump up m57sli CBV2 version to r3116 to take advantage of the corrected fan control code. Tested on real hardware. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/config/platforms/m57sli.conf =================================================================== --- buildrom-devel/config/platforms/m57sli.conf 2008-02-24 17:03:57 UTC (rev 132) +++ buildrom-devel/config/platforms/m57sli.conf 2008-02-25 20:13:09 UTC (rev 133) @@ -41,7 +41,7 @@ CBV2_CONFIG=Config.lb CBV2_PAYLOAD_FILE_EXT=elf CBV2_TDIR=m57sli -CBV2_TAG=3096 +CBV2_TAG=3116 # FILO configuration

1 0

r3116 - in trunk/coreboot-v2/src: config mainboard/gigabyte/m57sli superio/ite/it8716f
by svn＠coreboot.org 25 Feb '08

25 Feb '08

Author: ward Date: 2008-02-25 20:36:20 +0100 (Mon, 25 Feb 2008) New Revision: 3116 Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c Modified: trunk/coreboot-v2/src/config/Options.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb trunk/coreboot-v2/src/superio/ite/it8716f/superio.c Log: This patch adds automatic fan control for the CPU fan on the m57sli board. This is done via the ec_init routine in a source file in the mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been added to notify superio.c to get the ec_init externally. I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board. It works. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: trunk/coreboot-v2/src/config/Options.lb =================================================================== --- trunk/coreboot-v2/src/config/Options.lb 2008-02-25 10:15:10 UTC (rev 3115) +++ trunk/coreboot-v2/src/config/Options.lb 2008-02-25 19:36:20 UTC (rev 3116) @@ -861,6 +861,11 @@ # Misc device options ############################################### +define HAVE_FANCTL + default 0 + export used + comment "Include board specific FAN control initialization" +end define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 default 0 export used Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2008-02-25 10:15:10 UTC (rev 3115) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb 2008-02-25 19:36:20 UTC (rev 3116) @@ -206,6 +206,10 @@ end end +if HAVE_FANCTL + object fanctl.o +end + ## ## Setup RAM ## Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2008-02-25 10:15:10 UTC (rev 3115) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb 2008-02-25 19:36:20 UTC (rev 3116) @@ -115,6 +115,7 @@ uses CONFIG_USE_PRINTK_IN_CAR +uses HAVE_FANCTL ### ### Build options ### @@ -140,6 +141,11 @@ default CONFIG_LB_MEM_TOPK=2048 ## +## Set-up automatic fan control +## +default HAVE_FANCTL=1 + +## ## Build code for the fallback boot ## default HAVE_FALLBACK_BOOT=1 Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c =================================================================== --- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c (rev 0) +++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/fanctl.c 2008-02-25 19:36:20 UTC (rev 3116) @@ -0,0 +1,57 @@ +#include <arch/io.h> + +static void write_index(uint16_t port_base, uint8_t reg, uint8_t value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static const struct { + uint8_t index, value; +} sequence[]= { + /* Set FAN_CTL control register (0x14) polarity to high, and + activate fans 1, 2 and 3. */ + { 0x14, 0x87}, + /* set the correct sensor types 1,2 thermistor; 3 diode */ + { 0x51, 0x1c}, + /* set the 'zero' voltage for diode type sensor */ + { 0x5c, 0x80}, +// { 0x56, 0xe5}, +// { 0x57, 0xe5}, + { 0x59, 0xe5}, + { 0x5c, 0x00}, + /* fan1 (controlled by temp3) control parameters */ + /* fan off limit */ + { 0x60, 0xff}, + /* fan start limit */ + { 0x61, 0x14}, + /* ???? */ +// { 0x62, 0x00}, + /* start PWM */ + { 0x63, 0x27}, + /* smooth and slope PWM */ + { 0x64, 0x90}, + /* direct-down and interval */ + { 0x65, 0x03}, + /* fan1 auto controlled by temp3 */ + { 0x15, 0x82}, + /* fan2 soft controlled, max speed */ + { 0x16, 0x7f}, + /* fan3 soft controlled, 75% speed */ + { 0x17, 0x60}, + /* all fans enable, fan1 ctl smart */ + { 0x13, 0x71} +}; + +#define ARRAYSIZE(x) sizeof x/sizeof *x + +/* + * Called from superio.c + */ +void init_ec(uint16_t base) +{ + int i; + for (i=0; i<ARRAYSIZE(sequence); i++) { + write_index(base, sequence[i].index, sequence[i].value); + } +} Modified: trunk/coreboot-v2/src/superio/ite/it8716f/superio.c =================================================================== --- trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-02-25 10:15:10 UTC (rev 3115) +++ trunk/coreboot-v2/src/superio/ite/it8716f/superio.c 2008-02-25 19:36:20 UTC (rev 3116) @@ -62,6 +62,9 @@ return inb(port_base + 1); } +#ifdef HAVE_FANCTL +extern void init_ec(uint16_t base); +#else static void init_ec(uint16_t base) { uint8_t value; @@ -77,6 +80,7 @@ printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n", base + 0x14, value | 0x87); } +#endif static void it8716f_init(device_t dev) {

1 0

v3 config patch and lar patch
by Myles Watson 25 Feb '08

25 Feb '08

This patch makes PAYLOAD_PREPARSE_ELF only apply to the payload. It also separates the lar steps for adding the payload to make this happen. Because of that, I also separated the nocompress files so that there is no need for that style of flag. I removed it in lar as well. I rearranged Kconfig a little so that PAYLOAD_PREPARSE_ELF is an option if you've selected to have an ELF payload. I made the Makefile print PAYLOAD payload.elf -C lzma when the payload is compressed and PAYLOAD payload.elf when it isn't. Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com>

3 12

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coreboot February 2008