coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

r3115 - trunk/coreboot-v2/src/southbridge/nvidia/mcp55
by svn＠coreboot.org 25 Feb '08

25 Feb '08

Author: duwe Date: 2008-02-25 11:15:10 +0100 (Mon, 25 Feb 2008) New Revision: 3115 Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c Log: This trivial patch removes an unused local variable, thus getting rid of a compiler warning. Signed-off-by: Ronald Hoogenboom <hoogenboom30(a)zonnet.nl> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c =================================================================== --- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2008-02-21 21:00:19 UTC (rev 3114) +++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c 2008-02-25 10:15:10 UTC (rev 3115) @@ -248,7 +248,6 @@ static void mcp55_lpc_read_resources(device_t dev) { struct resource *res; - unsigned long index; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP

1 0

etherboot and filo issue
by joe＠smittys.pointclark.net 25 Feb '08

25 Feb '08

Hello, I think I figured out what the problem stated on the wiki is wrong with the etherboot payload. etherboot does not have filo in it's src directory. If you try ROM-o-matic and check off the box "CONFIG_FILO Enable FILO support. It will make main call pci_init." it gives you an ": undefined reference to `pci_init'" error. This comes from filo correct? So I browsed the etherboot src directory and filo is not there?? Should I download both, and copy filo into the etherboot src directory and try to build it? If I try this, should I build filo first, or does etherboot build both? Thanks - Joe

3 3

r132 - buildrom-devel/packages/utils
by svn＠coreboot.org 24 Feb '08

24 Feb '08

Author: ward Date: 2008-02-24 18:03:57 +0100 (Sun, 24 Feb 2008) New Revision: 132 Modified: buildrom-devel/packages/utils/nrv2b.mk Log: Make nrv2b.mk quiet, and make nrv2b-distclean not ask for confirmation when deleting it's directory under work/. This is a trivial patch. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Ward Vandewege <ward(a)gnu.org> Modified: buildrom-devel/packages/utils/nrv2b.mk =================================================================== --- buildrom-devel/packages/utils/nrv2b.mk 2008-02-24 14:47:53 UTC (rev 131) +++ buildrom-devel/packages/utils/nrv2b.mk 2008-02-24 17:03:57 UTC (rev 132) @@ -30,8 +30,8 @@ > $(NRV2B_BUILD_LOG) 2>&1) $(STAGING_DIR)/bin/nrv2b: $(NRV2B_SRC_DIR)/nrv2b - mkdir -p $(STAGING_DIR)/bin - cp $< $@ + @ mkdir -p $(STAGING_DIR)/bin + @ cp $< $@ $(NRV2B_STAMP_DIR) $(NRV2B_LOG_DIR): @ mkdir -p $@ @@ -43,5 +43,5 @@ @ $(MAKE) -C $(NRV2B_SRC_DIR) clean > /dev/null 2>&1 nrv2b-distclean: - @ rm -r $(NRV2B_DIR) + @ rm -rf $(NRV2B_DIR)

1 0

r131 - in buildrom-devel/packages: . utils
by svn＠coreboot.org 24 Feb '08

24 Feb '08

Author: ward Date: 2008-02-24 15:47:53 +0100 (Sun, 24 Feb 2008) New Revision: 131 Added: buildrom-devel/packages/utils/ buildrom-devel/packages/utils/nrv2b.mk Log: This is a part of r128 that was accidentally forgotten in the checkin. Signed-off-by: Jordan Crouse <jordan.crouse(a)amd.com> Acked-by: Ward Vandewege <ward(a)gnu.org> Added: buildrom-devel/packages/utils/nrv2b.mk =================================================================== --- buildrom-devel/packages/utils/nrv2b.mk (rev 0) +++ buildrom-devel/packages/utils/nrv2b.mk 2008-02-24 14:47:53 UTC (rev 131) @@ -0,0 +1,47 @@ +NRV2B_URL=svn://coreboot.org/repos/trunk/coreboot-v2/util/nrv2b +NRV2B_TAG=3086 + +NRV2B_DIR=$(BUILD_DIR)/nrv2b +NRV2B_SRC_DIR=$(NRV2B_DIR)/svn +NRV2B_STAMP_DIR=$(NRV2B_DIR)/stamps +NRV2B_LOG_DIR=$(NRV2B_DIR)/logs +NRV2B_TARBALL=nrv2b-svn-$(NRV2B_TAG).tar.gz + +ifeq ($(CONFIG_VERBOSE),y) +NRV2B_BUILD_LOG=/dev/stdout +NRV2B_FETCH_LOG=/dev/stdout +else +NRV2B_BUILD_LOG=$(NRV2B_LOG_DIR)/build.log +NRV2B_FETCH_LOG=$(NRV2B_LOG_DIR)/fetch.log +endif + +$(SOURCE_DIR)/$(NRV2B_TARBALL): + mkdir -p $(SOURCE_DIR)/nrv2b + @ $(BIN_DIR)/fetchsvn.sh $(NRV2B_URL) $(SOURCE_DIR)/nrv2b \ + $(NRV2B_TAG) $@ > $(NRV2B_FETCH_LOG) 2>&1 + +$(NRV2B_STAMP_DIR)/.unpacked: $(SOURCE_DIR)/$(NRV2B_TARBALL) + @ tar -C $(NRV2B_DIR) -zxf $(SOURCE_DIR)/$(NRV2B_TARBALL) + @ touch $@ + +$(NRV2B_SRC_DIR)/nrv2b: $(NRV2B_STAMP_DIR)/.unpacked + @ (unset CFLAGS; unset LDFLAGS; \ + $(MAKE) -C $(NRV2B_SRC_DIR) \ + > $(NRV2B_BUILD_LOG) 2>&1) + +$(STAGING_DIR)/bin/nrv2b: $(NRV2B_SRC_DIR)/nrv2b + mkdir -p $(STAGING_DIR)/bin + cp $< $@ + +$(NRV2B_STAMP_DIR) $(NRV2B_LOG_DIR): + @ mkdir -p $@ + +nrv2b: $(NRV2B_STAMP_DIR) $(NRV2B_LOG_DIR) $(STAGING_DIR)/bin/nrv2b + +nrv2b-clean: + @ echo "Cleaning nrv2b..." + @ $(MAKE) -C $(NRV2B_SRC_DIR) clean > /dev/null 2>&1 + +nrv2b-distclean: + @ rm -r $(NRV2B_DIR) +

1 0

Checking support for Anaheim2A motherboard
by Ken Chiang 23 Feb '08

23 Feb '08

Hello, I new to the list and would like to contribute to this project if possible. To get things started, I am wondering if the motherboard specified below is currently supported? Thanks! ================specs================== CPU: Intel Celeron 533Mhz northbridge: Intel 82810 southbridge: Intel 82801AA mainboard: Anaheim2A BIOs chip: ANA 2A (EM) v.1.03 lspci output: 00:00.0 Host bridge: Intel Corporation 82810 GMCH [Graphics Memory Controller Hub] (rev 03) 00:01.0 VGA compatible controller: Intel Corporation 82810 CGC [Chipset Graphics Controller] (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801AA PCI Bridge (rev 02) 00:1f.0 ISA bridge: Intel Corporation 82801AA ISA Bridge (LPC) (rev 02) 00:1f.1 IDE interface: Intel Corporation 82801AA IDE (rev 02) 00:1f.2 USB Controller: Intel Corporation 82801AA USB (rev 02) 00:1f.3 SMBus: Intel Corporation 82801AA SMBus (rev 02) 01:09.0 Multimedia audio controller: Cirrus Logic Crystal CS4281 PCI Audio (rev 01) 01:0b.0 Ethernet controller: D-Link System Inc RTL8139 Ethernet (rev 10) 01:0d.0 USB Controller: NEC Corporation USB (rev 41) 01:0d.1 USB Controller: NEC Corporation USB (rev 41) 01:0d.2 USB Controller: NEC Corporation USB 2.0 (rev 02) 01:0e.0 Communication controller: Conexant HSF 56k Data/Fax Modem (rev 01) superio chip: model number on actual chip ITE IT8702F-A superiotool output: superiotool r Found ITE IT8702F (id=0x8702, rev=0x3) at 0x2e No dump available for this Super I/O Type of BIOS device: soldered PLCC ____________________________________________________________________________________ Looking for last minute shopping deals? Find them fast with Yahoo! Search. http://tools.search.yahoo.com/newsearch/category.php?category=shopping

2 1

[patch] v3 geode graphics fixup
by Marc Jones 23 Feb '08

23 Feb '08

This should fix the Geode graphics init. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Fix Geode graphics init. The functions to enable graphics were misplaced in the pci dtc instead of the correct location in the domain. Also fixed up some warnings on the const gliutable. Signed-off-by:Marc Jones <marc.jones(a)amd.com> Index: coreboot-v3/northbridge/amd/geodelx/domain =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/domain 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/domain 2008-02-22 18:04:50.000000000 -0700 @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,5 +21,8 @@ { device_operations = "geodelx_north_domain"; + + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "0"; }; Index: coreboot-v3/northbridge/amd/geodelx/pci =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/pci 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/pci 2008-02-22 18:04:50.000000000 -0700 @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +20,5 @@ { device_operations = "geodelx_north_pci"; - - /* Video RAM has to be in 2MB chunks. */ - geode_video_mb = "0"; }; Index: coreboot-v3/northbridge/amd/geodelx/geodelink.h =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelink.h 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-02-22 18:04:50.000000000 -0700 @@ -73,6 +73,6 @@ {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, }; -static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; +static const struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; #endif /* GEODELINK_H */ Index: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelx.c 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-22 18:04:50.000000000 -0700 @@ -31,7 +31,7 @@ /* Function prototypes */ extern void chipsetinit(void); extern void northbridge_init_early(void); -extern void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci); +extern void graphics_init(u8 video_mb); extern u64 sizeram(void); /** @@ -49,9 +49,9 @@ * * @return TODO. */ -u64 get_systop(struct northbridge_amd_geodelx_pci_config *nb_pci) +u64 get_systop(struct northbridge_amd_geodelx_domain_config *nb_dm) { - struct gliutable *gl = NULL; + const struct gliutable *gl = NULL; u64 systop; struct msr msr; int i; @@ -68,7 +68,7 @@ systop += 4 * 1024; /* 4K */ } else { systop = - (((sizeram() - nb_pci->geode_video_mb) * 1024) - SMM_SIZE) * 1024; + (((sizeram() - nb_dm->geode_video_mb) * 1024) - SMM_SIZE) * 1024; } return systop; @@ -149,8 +149,8 @@ { int idx; struct device *mc_dev; - struct northbridge_amd_geodelx_pci_config *nb_pci = - (struct northbridge_amd_geodelx_pci_config *)dev->device_configuration; + struct northbridge_amd_geodelx_domain_config *nb_dm = + (struct northbridge_amd_geodelx_domain_config *)dev->device_configuration; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); @@ -162,7 +162,7 @@ ram_resource(dev, idx++, 0, 640); /* 1 MB .. (Systop - 1 MB) (in KB) */ ram_resource(dev, idx++, 1024, - (get_systop(nb_pci)/1024) - 1024); + (get_systop(nb_dm)/1024) - 1024); } phase4_assign_resources(&dev->link[0]); @@ -182,8 +182,8 @@ */ static void geodelx_pci_domain_phase2(struct device *dev) { - struct northbridge_amd_geodelx_pci_config *nb_pci = - (struct northbridge_amd_geodelx_pci_config *)dev->device_configuration; + struct northbridge_amd_geodelx_domain_config *nb_dm = + (struct northbridge_amd_geodelx_domain_config *)dev->device_configuration; void do_vsmbios(void); @@ -198,8 +198,8 @@ do_vsmbios(); printk(BIOS_SPEW, "After VSA:\n"); /* print_conf(); */ - - graphics_init(nb_pci); +printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", nb_dm->geode_video_mb); + graphics_init((u8)nb_dm->geode_video_mb); pci_set_method(dev); } Index: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelxinit.c 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-22 18:04:50.000000000 -0700 @@ -59,7 +59,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void writeglmsr(struct gliutable *gl) +static void writeglmsr(const struct gliutable *gl) { struct msr msr; @@ -76,7 +76,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void ShadowInit(struct gliutable *gl) +static void ShadowInit(const struct gliutable *gl) { struct msr msr; @@ -134,7 +134,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void sysmem_init(struct gliutable *gl) +static void sysmem_init(const struct gliutable *gl) { struct msr msr; int sizembytes, sizebytes; @@ -170,7 +170,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void SMMGL0Init(struct gliutable *gl) +static void SMMGL0Init(const struct gliutable *gl) { struct msr msr; int sizebytes = sizeram() << 20; @@ -201,7 +201,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void SMMGL1Init(struct gliutable *gl) +static void SMMGL1Init(const struct gliutable *gl) { struct msr msr; printk(BIOS_DEBUG, "%s:\n", __FUNCTION__); @@ -225,7 +225,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void GLIUInit(struct gliutable *gl) +static void GLIUInit(const struct gliutable *gl) { while (gl->desc_type != GL_END) { switch (gl->desc_type) { @@ -259,7 +259,7 @@ */ static void GLPCI_init(void) { - struct gliutable *gl = NULL; + const struct gliutable *gl = NULL; struct msr msr; int i, enable_preempt, enable_cpu_override; int nic_grants_control, enable_bus_parking; @@ -545,7 +545,7 @@ { int i; struct msr msr; - struct gliutable *pTable; + const struct gliutable *pTable; u32 shadowLo, shadowHi; shadowLo = (u32) shadowSettings; @@ -612,7 +612,7 @@ static void enable_L1_cache(void) { int i; - struct gliutable *gl = NULL; + const struct gliutable *gl = NULL; struct msr msr; u8 SysMemCacheProp; Index: coreboot-v3/northbridge/amd/geodelx/grphinit.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/grphinit.c 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-02-22 18:04:50.000000000 -0700 @@ -26,7 +26,7 @@ /* * This function mirrors the Graphics_Init routine in GeodeROM. */ -void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci) +void graphics_init(u8 video_mb) { u16 wClassIndex, wData, res; @@ -54,7 +54,7 @@ */ wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | - VG_CFG_DSCRT | (nb_pci->geode_video_mb & VG_MEM_MASK); + VG_CFG_DSCRT | (video_mb & VG_MEM_MASK); vr_write(wClassIndex, wData); res = vr_read(wClassIndex); Index: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3.orig/mainboard/pcengines/alix1c/dts 2008-02-22 18:04:03.000000000 -0700 +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-22 18:05:15.000000000 -0700 @@ -27,10 +27,10 @@ }; domain@0 { /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; pci@1,0 { /config/("northbridge/amd/geodelx/pci"); - /* Video RAM has to be in 2MB chunks. */ - geode_video_mb = "8"; }; pci@15,0 { /config/("southbridge/amd/cs5536/dts");

2 3

r617 - in coreboot-v3: mainboard/pcengines/alix1c northbridge/amd/geodelx
by svn＠coreboot.org 23 Feb '08

23 Feb '08

Author: rminnich Date: 2008-02-23 17:31:50 +0100 (Sat, 23 Feb 2008) New Revision: 617 Modified: coreboot-v3/mainboard/pcengines/alix1c/dts coreboot-v3/northbridge/amd/geodelx/domain coreboot-v3/northbridge/amd/geodelx/geodelink.h coreboot-v3/northbridge/amd/geodelx/geodelx.c coreboot-v3/northbridge/amd/geodelx/geodelxinit.c coreboot-v3/northbridge/amd/geodelx/grphinit.c coreboot-v3/northbridge/amd/geodelx/pci Log: Fix Geode graphics init. The functions to enable graphics were misplaced in the pci dtc instead of the correct location in the domain. Also fixed up some warnings on the const gliutable. Tested on alix1c and boots to Linux, ethernet works. Still trying to light up the display :-) Signed-off-by: Marc Jones <marc.jones(a)amd.com> Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-23 16:31:50 UTC (rev 617) @@ -27,10 +27,10 @@ }; domain@0 { /config/("northbridge/amd/geodelx/domain"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; pci@1,0 { /config/("northbridge/amd/geodelx/pci"); - /* Video RAM has to be in 2MB chunks. */ - geode_video_mb = "8"; }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); Modified: coreboot-v3/northbridge/amd/geodelx/domain =================================================================== --- coreboot-v3/northbridge/amd/geodelx/domain 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/northbridge/amd/geodelx/domain 2008-02-23 16:31:50 UTC (rev 617) @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,5 +21,8 @@ { device_operations = "geodelx_north_domain"; + + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "0"; }; Modified: coreboot-v3/northbridge/amd/geodelx/geodelink.h =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-02-23 16:31:50 UTC (rev 617) @@ -73,6 +73,6 @@ {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, }; -static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; +static const struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; #endif /* GEODELINK_H */ Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-23 16:31:50 UTC (rev 617) @@ -31,7 +31,7 @@ /* Function prototypes */ extern void chipsetinit(void); extern void northbridge_init_early(void); -extern void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci); +extern void graphics_init(u8 video_mb); extern u64 sizeram(void); /** @@ -49,9 +49,9 @@ * * @return TODO. */ -u64 get_systop(struct northbridge_amd_geodelx_pci_config *nb_pci) +u64 get_systop(struct northbridge_amd_geodelx_domain_config *nb_dm) { - struct gliutable *gl = NULL; + const struct gliutable *gl = NULL; u64 systop; struct msr msr; int i; @@ -68,7 +68,7 @@ systop += 4 * 1024; /* 4K */ } else { systop = - (((sizeram() - nb_pci->geode_video_mb) * 1024) - SMM_SIZE) * 1024; + (((sizeram() - nb_dm->geode_video_mb) * 1024) - SMM_SIZE) * 1024; } return systop; @@ -149,8 +149,8 @@ { int idx; struct device *mc_dev; - struct northbridge_amd_geodelx_pci_config *nb_pci = - (struct northbridge_amd_geodelx_pci_config *)dev->device_configuration; + struct northbridge_amd_geodelx_domain_config *nb_dm = + (struct northbridge_amd_geodelx_domain_config *)dev->device_configuration; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); @@ -162,7 +162,7 @@ ram_resource(dev, idx++, 0, 640); /* 1 MB .. (Systop - 1 MB) (in KB) */ ram_resource(dev, idx++, 1024, - (get_systop(nb_pci)/1024) - 1024); + (get_systop(nb_dm)/1024) - 1024); } phase4_assign_resources(&dev->link[0]); @@ -182,8 +182,8 @@ */ static void geodelx_pci_domain_phase2(struct device *dev) { - struct northbridge_amd_geodelx_pci_config *nb_pci = - (struct northbridge_amd_geodelx_pci_config *)dev->device_configuration; + struct northbridge_amd_geodelx_domain_config *nb_dm = + (struct northbridge_amd_geodelx_domain_config *)dev->device_configuration; void do_vsmbios(void); @@ -198,8 +198,8 @@ do_vsmbios(); printk(BIOS_SPEW, "After VSA:\n"); /* print_conf(); */ - - graphics_init(nb_pci); +printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", nb_dm->geode_video_mb); + graphics_init((u8)nb_dm->geode_video_mb); pci_set_method(dev); } Modified: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-23 16:31:50 UTC (rev 617) @@ -59,7 +59,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void writeglmsr(struct gliutable *gl) +static void writeglmsr(const struct gliutable *gl) { struct msr msr; @@ -76,7 +76,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void ShadowInit(struct gliutable *gl) +static void ShadowInit(const struct gliutable *gl) { struct msr msr; @@ -134,7 +134,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void sysmem_init(struct gliutable *gl) +static void sysmem_init(const struct gliutable *gl) { struct msr msr; int sizembytes, sizebytes; @@ -170,7 +170,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void SMMGL0Init(struct gliutable *gl) +static void SMMGL0Init(const struct gliutable *gl) { struct msr msr; int sizebytes = sizeram() << 20; @@ -201,7 +201,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void SMMGL1Init(struct gliutable *gl) +static void SMMGL1Init(const struct gliutable *gl) { struct msr msr; printk(BIOS_DEBUG, "%s:\n", __FUNCTION__); @@ -225,7 +225,7 @@ * * @param gl A GeodeLink table descriptor. */ -static void GLIUInit(struct gliutable *gl) +static void GLIUInit(const struct gliutable *gl) { while (gl->desc_type != GL_END) { switch (gl->desc_type) { @@ -259,7 +259,7 @@ */ static void GLPCI_init(void) { - struct gliutable *gl = NULL; + const struct gliutable *gl = NULL; struct msr msr; int i, enable_preempt, enable_cpu_override; int nic_grants_control, enable_bus_parking; @@ -545,7 +545,7 @@ { int i; struct msr msr; - struct gliutable *pTable; + const struct gliutable *pTable; u32 shadowLo, shadowHi; shadowLo = (u32) shadowSettings; @@ -612,7 +612,7 @@ static void enable_L1_cache(void) { int i; - struct gliutable *gl = NULL; + const struct gliutable *gl = NULL; struct msr msr; u8 SysMemCacheProp; Modified: coreboot-v3/northbridge/amd/geodelx/grphinit.c =================================================================== --- coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-02-23 16:31:50 UTC (rev 617) @@ -26,7 +26,7 @@ /* * This function mirrors the Graphics_Init routine in GeodeROM. */ -void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci) +void graphics_init(u8 video_mb) { u16 wClassIndex, wData, res; @@ -54,7 +54,7 @@ */ wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | - VG_CFG_DSCRT | (nb_pci->geode_video_mb & VG_MEM_MASK); + VG_CFG_DSCRT | (video_mb & VG_MEM_MASK); vr_write(wClassIndex, wData); res = vr_read(wClassIndex); Modified: coreboot-v3/northbridge/amd/geodelx/pci =================================================================== --- coreboot-v3/northbridge/amd/geodelx/pci 2008-02-22 01:58:09 UTC (rev 616) +++ coreboot-v3/northbridge/amd/geodelx/pci 2008-02-23 16:31:50 UTC (rev 617) @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +20,5 @@ { device_operations = "geodelx_north_pci"; - - /* Video RAM has to be in 2MB chunks. */ - geode_video_mb = "0"; };

1 0

v3 smbus device structure
by Marc Jones 23 Feb '08

23 Feb '08

We need to discuss v3 smbus operations. Someone has done a lot of work to make smbus_ops.c and smbus.h. The code treats smbus as a bus, like the pci bus, with a device structure and all. This approach seems nice and maybe the right way to do it, but it is somewhat overkill. I think that the complexity is one reason why the structure is in place in v2 but never used. Instead, simpler chipset/mainboard specific functions are used. The other reason is that the smbus is accessed in ROMCC/CAR code and not in the main coreboot bus enumeration code. My observation is that the SPD is the only device on smbus used by most mainboards in coreboot. So, what do we want to do for v3? If we go with the bus/device structure every mainboard in v2 will need to have the smbus functions ported. Also, someone will have to figure out how to describe the smbus devices in the dts and the entire thing might need to use a simpler bus/device structure. Or, we can do as was done in v2 and leave it to the chipset/mainboard code. Thoughts? Volunteers? Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

4 6

SST49LF008A on amd/db800
by Phani Babu Giddi 23 Feb '08

23 Feb '08

Hello All, I am planning to use the BIOS chip SST49LF008A instead of SST49LF004B on AMD's Geode LX 800 development board DB800. Do you think this will work without changing any optiong in Config.lb for this board. 49LF004B is based on LPC while 49LF008A is based on FWH. I had to change the part because LPC interface based chip by SST has been EOLed. The best way for me would have been to test it and find it out myself but currently coreboot build is failing on Fedora 8 based system even after applying the rececent patches and updates to LD. I am just curious does CS5536 has to be initalized in a differently to be able to boot from FWH ? Any idea ? Regards, Phani

2 2

v3 build process and lar flags
by Myles Watson 23 Feb '08

23 Feb '08

It seems like the build would be cleaner if we had two lists of files to add to the lar and added them in two steps. lar -c coreboot.rom $(NOCOMPRESS_FILES) -s $(ROM_SIZE) ... lar -a coreboot.rom $(COMPRESS_FLAG) $(COMPRESSIBLE_FILES) The unfortunate thing with the nocompress:file:lar_path style is that it makes it difficult to add support for other flags, unless you specify a flag ordering. For example imagine if you wanted to add a flag specifying to add the file as close to the end as possible, etc. The reason I was interested is I still think the cleanest way is to allow repacking of lar files (i.e., no intermediate format), but I don't see a good way to add that option with the current usage model for lar. Myles

3 8

← Newer
1
...
6
7
8
9
10
11
12
...
43
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2008