coreboot February 2008

coreboot@coreboot.org

77 participants
422 discussions

r126 - buildrom-devel/config/platforms
by svn＠coreboot.org 22 Feb '08

22 Feb '08

Author: myles Date: 2008-02-22 21:39:55 +0100 (Fri, 22 Feb 2008) New Revision: 126 Modified: buildrom-devel/config/platforms/qemu.conf buildrom-devel/config/platforms/serengeti_cheetah.conf Log: This bumps uclibc for two targets that got missed with rev 117, so that they still build. I deem it trivial. Myles Signed-off-by: Myles Watson <mylesgw(a)gmail.com Acked by: Myles Watson <mylesgw(a)gmail.com Modified: buildrom-devel/config/platforms/qemu.conf =================================================================== --- buildrom-devel/config/platforms/qemu.conf 2008-02-22 18:58:33 UTC (rev 125) +++ buildrom-devel/config/platforms/qemu.conf 2008-02-22 20:39:55 UTC (rev 126) @@ -18,7 +18,7 @@ KERNEL_VERSION=2.6.22.2 KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-qemu -UCLIBC_VER=0.9.28 +UCLIBC_VER=0.9.29 # Etherboot configuration ETHERBOOT_ARCH=i386 Modified: buildrom-devel/config/platforms/serengeti_cheetah.conf =================================================================== --- buildrom-devel/config/platforms/serengeti_cheetah.conf 2008-02-22 18:58:33 UTC (rev 125) +++ buildrom-devel/config/platforms/serengeti_cheetah.conf 2008-02-22 20:39:55 UTC (rev 126) @@ -32,7 +32,7 @@ else KERNEL_VERSION=2.6.20.2 KERNEL_CONFIG=$(PACKAGE_DIR)/kernel/conf/defconfig-serengeti_cheetah -UCLIBC_VER=0.9.28 +UCLIBC_VER=0.9.29 endif #UCLIBC_ARCH=$(TARGET_ARCH)

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[PATCH] [buildrom] add optional 'press enter to start the busybox shell' pause to LAB
by Ward Vandewege 22 Feb '08

22 Feb '08

-- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior System Administrator

2 2

r125 - in buildrom-devel: config/payloads packages/busybox/conf scripts skeleton
by svn＠coreboot.org 22 Feb '08

22 Feb '08

Author: ward Date: 2008-02-22 19:58:33 +0100 (Fri, 22 Feb 2008) New Revision: 125 Modified: buildrom-devel/config/payloads/Config.in buildrom-devel/packages/busybox/conf/defconfig buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 buildrom-devel/scripts/Makefile.lab buildrom-devel/skeleton/linuxrc Log: This patch adds an optional delay before the LAB environment kexecs the on-disk kernel. This allows entering the busybox shell, which can be useful for maintenance and debugging. The delay is configurable from kconfig, and defaults to 5 seconds. The patch enables CONFIG_ASH_READ_TIMEOUT in the uclibc configuration because the 'read' command in the ash shell does not support the '-t' timeout parameter otherwise. It also changes the default for including a statically compiled copy of kexec into the LAB payload to no, because this makes the payload too large for 1MB rom chips. Tested on real hardware. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Jordan Crouse <jordan.crouse(a)amd.com> Modified: buildrom-devel/config/payloads/Config.in =================================================================== --- buildrom-devel/config/payloads/Config.in 2008-02-21 21:51:05 UTC (rev 124) +++ buildrom-devel/config/payloads/Config.in 2008-02-22 18:58:33 UTC (rev 125) @@ -95,12 +95,20 @@ config KBL bool "Reduced size kexec-tools" - default y + default n select KBL_KEXEC_ONLY help Say 'Y' here to include the the Kexec Bootloader as a cheep substitute for kexec-tools +config LAB_PAUSE + int "Seconds to pause before booting, to allow access to the busybox environment" + default 5 + help + Set the number of seconds you'd like to pause before booting the kexec'ed + kernel here. During this pause, you can press enter to gain access to the + busybox environment. + config BUSYBOX bool "Busybox" default y Modified: buildrom-devel/packages/busybox/conf/defconfig =================================================================== --- buildrom-devel/packages/busybox/conf/defconfig 2008-02-21 21:51:05 UTC (rev 124) +++ buildrom-devel/packages/busybox/conf/defconfig 2008-02-22 18:58:33 UTC (rev 125) @@ -556,7 +556,7 @@ # # CONFIG_ASH_JOB_CONTROL is not set # CONFIG_ASH_READ_NCHARS is not set -# CONFIG_ASH_READ_TIMEOUT is not set +CONFIG_ASH_READ_TIMEOUT=y CONFIG_ASH_ALIAS=y CONFIG_ASH_MATH_SUPPORT=y # CONFIG_ASH_MATH_SUPPORT_64 is not set Modified: buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 =================================================================== --- buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 2008-02-21 21:51:05 UTC (rev 124) +++ buildrom-devel/packages/busybox/conf/defconfig-serengeti_cheetah-x86_64 2008-02-22 18:58:33 UTC (rev 125) @@ -556,7 +556,7 @@ # # CONFIG_ASH_JOB_CONTROL is not set # CONFIG_ASH_READ_NCHARS is not set -# CONFIG_ASH_READ_TIMEOUT is not set +CONFIG_ASH_READ_TIMEOUT=y CONFIG_ASH_ALIAS=y CONFIG_ASH_MATH_SUPPORT=y # CONFIG_ASH_MATH_SUPPORT_64 is not set Modified: buildrom-devel/scripts/Makefile.lab =================================================================== --- buildrom-devel/scripts/Makefile.lab 2008-02-21 21:51:05 UTC (rev 124) +++ buildrom-devel/scripts/Makefile.lab 2008-02-22 18:58:33 UTC (rev 125) @@ -3,6 +3,7 @@ $(OUTPUT_DIR)/initrd.uncompressed: $(PAYLOAD-y) @ cp -af $(SKELETON_DIR)/* $(INITRD_DIR) @ chmod 0755 $(INITRD_DIR)/linuxrc + @ sed -i 's/%%LAB_PAUSE%%/$(CONFIG_LAB_PAUSE)/' $(INITRD_DIR)/linuxrc @ echo "Cleaning up shared libraries..." Modified: buildrom-devel/skeleton/linuxrc =================================================================== --- buildrom-devel/skeleton/linuxrc 2008-02-21 21:51:05 UTC (rev 124) +++ buildrom-devel/skeleton/linuxrc 2008-02-22 18:58:33 UTC (rev 125) @@ -17,11 +17,24 @@ # Show the version cat /buildrom-version > /dev/tty$VT -message "Trying to boot from hdd." -cd /bin -./boot-hdd +message "Press enter to start the busybox shell (pausing %%LAB_PAUSE%% seconds)." +read -t %%LAB_PAUSE%% UNUSED RET=$? -cd / +if [ "$RET" == '0' ]; then + message "NOTICE: Starting the shell..." + message "" + message "To boot your system as normal, type:" + message " cd /bin; ./boot-hdd" + message "" + openvt $VT /bin/ash + exec /bin/ash +else + message "Trying to boot from hdd." + cd /bin + ./boot-hdd + RET=$? + cd / +fi message "NOTICE: Starting the shell..." openvt $VT /bin/ash

1 0

v3 geode interrupt routing?
by Marc Jones 22 Feb '08

22 Feb '08

Ron, Can you post what you did for interrupt routing? Thanks, Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors

2 2

Mainboard config.lb question
by Nate 22 Feb '08

22 Feb '08

What exactly is happening when I set a device "pci x.x off" in config.lb. Does coreboot just not set a BAR and irq for this device or is more happening to actively disable or turn this device off? Thanks, Nate --------------------------------- Never miss a thing. Make Yahoo your homepage.

2 1

(no subject)
by Mikhail Savchenko 22 Feb '08

22 Feb '08

Getting the next output, help me to localize the problem coreboot-2.0.0_blast_Fallback Fri Feb 22 15:57:45 MSK 2008 starting... bsp_apicid=00 (0,1) link=01 (1,0) link=01 02 nodes initialized. core0 started: 01 01 02 03SBLink=00 NC node|link=00 while waiting for BSP signal to STOP, timeout in ap 01 while waiting for BSP signal to STOP, timeout in ap 02 while waiting for BSP signal to STOP, timeout in ap 03

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[ patch] v3 Geode graphics init.
by Marc Jones 22 Feb '08

22 Feb '08

This patch assumes the vsa/idt patch is in place. Marc -- Marc Jones Senior Firmware Engineer (970) 226-9684 Office mailto:Marc.Jones@amd.com http://www.amd.com/embeddedprocessors Removed CONFIG_VIDE0_MB in Kconfig and set the Geode graphics memory size through the Geode northbridge pci dts. This is a better way to handle a cpu/mainboard specific value. Signed-off-by: Marc Jones <marc.jones(a)amd.com> Index: coreboot-v3/northbridge/amd/geodelx/geodelx.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelx.c 2008-02-20 10:07:27.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-20 12:12:07.000000000 -0700 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,12 +25,14 @@ #include <device/pci_ids.h> #include <msr.h> #include <amd_geodelx.h> +#include <statictree.h> +#include "geodelink.h" /* Function prototypes */ extern void chipsetinit(void); -extern u32 get_systop(void); extern void northbridge_init_early(void); - +extern void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci); +extern int sizeram(void); /** * Currently not set up. @@ -41,6 +43,37 @@ { } + +/** + * TODO. + * + * @return TODO. + */ +u32 get_systop(struct northbridge_amd_geodelx_pci_config *nb_pci) +{ + struct gliutable *gl = NULL; + u32 systop; + struct msr msr; + int i; + + for (i = 0; gliu0table[i].desc_name != GL_END; i++) { + if (gliu0table[i].desc_type == R_SYSMEM) { + gl = &gliu0table[i]; + break; + } + } + if (gl) { + msr = rdmsr(gl->desc_name); + systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); + systop += 4 * 1024; /* 4K */ + } else { + systop = + ((sizeram() - nb_pci->geode_video_mb) * 1024) - SMM_SIZE - 1024; + } + + return systop; +} + /** * Initialize the northbridge PCI device. * Right now this a no op. We leave it here as a hook for later use. @@ -116,6 +149,8 @@ { int idx; struct device *mc_dev; + struct northbridge_amd_geodelx_pci_config *nb_pci = + (struct northbridge_amd_geodelx_pci_config *)dev->device_configuration; printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); @@ -127,7 +162,7 @@ ram_resource(dev, idx++, 0, 640); /* 1 MB .. (Systop - 1 MB) (converted to KB) */ ram_resource(dev, idx++, 1024, - (get_systop() - (1 * 1024 * 1024)) / 1024); + (get_systop(nb_pci) - (1 * 1024 * 1024)) / 1024); } phase4_assign_resources(&dev->link[0]); @@ -147,6 +182,9 @@ */ static void geodelx_pci_domain_phase2(struct device *dev) { + struct northbridge_amd_geodelx_pci_config *nb_pci = + (struct northbridge_amd_geodelx_pci_config *)dev->device_configuration; + void do_vsmbios(void); printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__); @@ -161,8 +199,7 @@ printk(BIOS_SPEW, "After VSA:\n"); /* print_conf(); */ -#warning graphics_init is disabled. - /* graphics_init(); */ + graphics_init(nb_pci); pci_set_method(dev); } Index: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/geodelxinit.c 2008-02-19 10:46:51.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c 2008-02-20 10:59:05.000000000 -0700 @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,63 +23,8 @@ #include <msr.h> #include <cpu.h> #include <amd_geodelx.h> +#include "geodelink.h" -/* Function prototypes */ - -struct gliutable { - unsigned long desc_name; - unsigned short desc_type; - unsigned long hi, lo; -}; - -static struct gliutable gliu0table[] = { - /* 0-7FFFF to MC */ - {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0, - .lo = 0x0FFF80}, - /* 80000-9FFFF to MC */ - {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0, - .lo = (0x80 << 20) + 0x0FFFE0}, - /* C0000-FFFFF split to MC and PCI (sub decode) A0000-BFFFF - * handled by SoftVideo. - */ - {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW, - .hi = MSR_MC + 0x0,.lo = 0x03}, - /* Catch and fix dynamically. */ - {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM, - .hi = MSR_MC,.lo = 0x0}, - /* Catch and fix dynamically. */ - {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM, - .hi = MSR_MC,.lo = 0x0}, - {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER, - .hi = 0x0,.lo = GL0_CPU}, - {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, -}; - -static struct gliutable gliu1table[] = { - /* 0-7FFFF to MC */ - {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0, - .lo = 0x0FFF80}, - /* 80000-9FFFF to MC */ - {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0, - .lo = (0x80 << 20) + 0x0FFFE0}, - /* C0000-Fffff split to MC and PCI (sub decode) */ - {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW, - .hi = MSR_GL0 + 0x0,.lo = 0x03}, - /* Catch and fix dynamically. */ - {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM, - .hi = MSR_GL0,.lo = 0x0}, - /* Catch and fix dynamically. */ - {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM, - .hi = MSR_GL0,.lo = 0x0}, - {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER, - .hi = 0x0,.lo = GL1_GLIU0}, - /* FooGlue FPU 0xF0 */ - {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO, - .hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, - {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, -}; - -static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; static struct msrinit clock_gating_default[] = { {GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}}, @@ -763,10 +708,6 @@ printk(BIOS_DEBUG, "L2 cache enabled\n"); } -#ifndef CONFIG_VIDEO_MB -#warning "CONFIG_VIDEO_MB was not defined" -#define CONFIG_VIDEO_MB 8 -#endif /** * Set up all LX cache registers, L1, L2, and x86. @@ -790,36 +731,6 @@ } /** - * TODO. - * - * @return TODO. - */ -u32 get_systop(void) -{ - struct gliutable *gl = NULL; - u32 systop; - struct msr msr; - int i; - - for (i = 0; gliu0table[i].desc_name != GL_END; i++) { - if (gliu0table[i].desc_type == R_SYSMEM) { - gl = &gliu0table[i]; - break; - } - } - if (gl) { - msr = rdmsr(gl->desc_name); - systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8); - systop += 4 * 1024; /* 4K */ - } else { - systop = - ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024; - } - - return systop; -} - -/** * Do all the Nasty Bits that have to happen. * * These can be done once memory is up, but before much else is done. Index: coreboot-v3/northbridge/amd/geodelx/grphinit.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ coreboot-v3/northbridge/amd/geodelx/grphinit.c 2008-02-20 10:59:05.000000000 -0700 @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <io.h> +#include <amd_geodelx.h> +#include <console.h> +#include <statictree.h> + + /* + * This function mirrors the Graphics_Init routine in GeodeROM. + */ +void graphics_init(struct northbridge_amd_geodelx_pci_config *nb_pci) +{ + u16 wClassIndex, wData, res; + + /* SoftVG initialization */ + printk(BIOS_DEBUG, "Graphics init...\n"); + + /* Call SoftVG with the main configuration parameters. */ + /* NOTE: SoftVG expects the memory size to be given in 2MB blocks */ + + wClassIndex = (VRC_VG << 8) + VG_CONFIG; + + /* + * Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP) + * External Monochrome Card Support(12) 0, NO + * Controller Priority Select(11) 1, Primary + * Display Select(10:8) 0x0, CRT + * Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1, + * defined in mainboard/../dts + * PLL Reference Clock Bypass(0) 0, Default + */ + + /* Video RAM has to be given in 2MB chunks + * the value is read @ 7:1 (value in 7:0 looks like /2) + * so we can add the real value in megabytes. + */ + + wData = VG_CFG_DRIVER | VG_CFG_PRIORITY | + VG_CFG_DSCRT | (nb_pci->geode_video_mb & VG_MEM_MASK); + vr_write(wClassIndex, wData); + + res = vr_read(wClassIndex); + printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res); +} Index: coreboot-v3/northbridge/amd/geodelx/geodelink.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ coreboot-v3/northbridge/amd/geodelx/geodelink.h 2008-02-20 10:59:05.000000000 -0700 @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef GEODELINK_H +#define GEODELINK_H + +struct gliutable { + unsigned long desc_name; + unsigned short desc_type; + unsigned long hi, lo; +}; + +static struct gliutable gliu0table[] = { + /* 0-7FFFF to MC */ + {.desc_name = MSR_GLIU0_BASE1,.desc_type = BM,.hi = MSR_MC + 0x0, + .lo = 0x0FFF80}, + /* 80000-9FFFF to MC */ + {.desc_name = MSR_GLIU0_BASE2,.desc_type = BM,.hi = MSR_MC + 0x0, + .lo = (0x80 << 20) + 0x0FFFE0}, + /* C0000-FFFFF split to MC and PCI (sub decode) A0000-BFFFF + * handled by SoftVideo. + */ + {.desc_name = MSR_GLIU0_SHADOW,.desc_type = SC_SHADOW, + .hi = MSR_MC + 0x0,.lo = 0x03}, + /* Catch and fix dynamically. */ + {.desc_name = MSR_GLIU0_SYSMEM,.desc_type = R_SYSMEM, + .hi = MSR_MC,.lo = 0x0}, + /* Catch and fix dynamically. */ + {.desc_name = MSR_GLIU0_SMM,.desc_type = BMO_SMM, + .hi = MSR_MC,.lo = 0x0}, + {.desc_name = GLIU0_GLD_MSR_COH,.desc_type = OTHER, + .hi = 0x0,.lo = GL0_CPU}, + {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, +}; + +static struct gliutable gliu1table[] = { + /* 0-7FFFF to MC */ + {.desc_name = MSR_GLIU1_BASE1,.desc_type = BM,.hi = MSR_GL0 + 0x0, + .lo = 0x0FFF80}, + /* 80000-9FFFF to MC */ + {.desc_name = MSR_GLIU1_BASE2,.desc_type = BM,.hi = MSR_GL0 + 0x0, + .lo = (0x80 << 20) + 0x0FFFE0}, + /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name = MSR_GLIU1_SHADOW,.desc_type = SC_SHADOW, + .hi = MSR_GL0 + 0x0,.lo = 0x03}, + /* Catch and fix dynamically. */ + {.desc_name = MSR_GLIU1_SYSMEM,.desc_type = R_SYSMEM, + .hi = MSR_GL0,.lo = 0x0}, + /* Catch and fix dynamically. */ + {.desc_name = MSR_GLIU1_SMM,.desc_type = BM_SMM, + .hi = MSR_GL0,.lo = 0x0}, + {.desc_name = GLIU1_GLD_MSR_COH,.desc_type = OTHER, + .hi = 0x0,.lo = GL1_GLIU0}, + /* FooGlue FPU 0xF0 */ + {.desc_name = MSR_GLIU1_FPU_TRAP,.desc_type = SCIO, + .hi = (GL1_GLCP << 29) + 0x0,.lo = 0x033000F0}, + {.desc_name = GL_END,.desc_type = GL_END,.hi = 0x0,.lo = 0x0}, +}; + +static struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 }; + +#endif /* GEODELINK_H */ Index: coreboot-v3/include/arch/x86/amd_geodelx.h =================================================================== --- coreboot-v3.orig/include/arch/x86/amd_geodelx.h 2008-02-19 10:46:52.000000000 -0700 +++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-02-20 10:59:05.000000000 -0700 @@ -1254,7 +1254,7 @@ * @param class_index The register index * @return the 16-bit word of data */ -static inline u16 vr_ead(u16 class_index) +static inline u16 vr_read(u16 class_index) { u16 data; outl(((u32) VR_UNLOCK << 16) | class_index, VRC_INDEX); Index: coreboot-v3/mainboard/pcengines/alix1c/dts =================================================================== --- coreboot-v3.orig/mainboard/pcengines/alix1c/dts 2008-02-19 10:46:52.000000000 -0700 +++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-20 10:59:05.000000000 -0700 @@ -29,6 +29,8 @@ /config/("northbridge/amd/geodelx/domain"); pci@1,0 { /config/("northbridge/amd/geodelx/pci"); + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "8"; }; pci@15,0 { /config/("southbridge/amd/cs5536/dts"); Index: coreboot-v3/northbridge/amd/geodelx/pci =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/pci 2008-02-19 10:46:52.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/pci 2008-02-20 10:59:05.000000000 -0700 @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2008 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2008 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,5 +21,8 @@ { device_operations = "geodelx_north_pci"; + + /* Video RAM has to be in 2MB chunks. */ + geode_video_mb = "0"; }; Index: coreboot-v3/northbridge/amd/geodelx/Makefile =================================================================== --- coreboot-v3.orig/northbridge/amd/geodelx/Makefile 2008-02-20 11:34:34.000000000 -0700 +++ coreboot-v3/northbridge/amd/geodelx/Makefile 2008-02-20 11:35:28.000000000 -0700 @@ -23,6 +23,7 @@ STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \ $(obj)/northbridge/amd/geodelx/vsmsetup.o \ - $(obj)/util/x86emu/vm86_gdt.o + $(obj)/util/x86emu/vm86_gdt.o \ + $(obj)/northbridge/amd/geodelx/grphinit.o endif

6 24

flashrom: Handling of mainboard selection
by Mart Raudsepp 22 Feb '08

22 Feb '08

Hello, I am working on adding board_enable code for Artec Group DBE61 and DBE62 boards to utils/flashrom to set up everything fully for flash writing to work in all circumstances, but I've hit a problem in the infrastructure code for mainboard selection handling that I'd like to discuss on how to approach. These boards are based on the AMD Geode line, so the PCI devices that exist for the outside are whatever the VSA exposes, which is typically the very same set of PCI devices that a big number of other Geode based products get exposed (save maybe network adapter and a few other things that can easily overlap with other boards). Therefore, it is undesirable to have the board PCI ID based auto-detection consider a board with Geode PCI devices a DBE61 without the user having said so specifically via -m artecgroup:dbe61 in scenarios when the ROM flash is empty or contains something else than a coreboot image with an appropriate name that would get auto-detected first. However, the current infrastructure in board_enable.c doesn't allow this scenario, due to the combination of the following in the current code: a) for a user specified board to be accepted, at least one set of IDs has to match to something that's on board (reasonable safeguard by itself); b) auto-detection is ran whenever a mainboard is not specified - the first board that has all non-NULL IDs existent is deemed the correct board even if the check would succeed for other boards in the list as well So, as soon as I add a board entry to board_pciid_enables[] that describes one or two Geode VSA exposed PCI devices, I suspect all other Geode products will start getting auto-detected as the board I add, unless they happen to have a coreboot image with a name that is in the struct as well (lb_vendor/lb_name). As I'm not sure how it's desired to handle this, I'm going to list the various approaches that I can think of, and will wait for comments and suggestions on the matter: * Allow all NULL PCI IDs, making the board auto-detection skip such entries, and use it only when the coreboot name match succeeds or the user has specified the board with -m (--mainboard) argument. Pros: can leave such hardly identifiable (by PCI devices) out of the auto-detection logic Cons: No safeguarding at all * Add a field to the struct (either treated as boolean, or a flag), that tells the logic if this entry should be considered in the auto-detection logic or skipped Pros: * can skip boards from PCI based auto-detection logic, requiring user specifying it; * has safeguards still in place (in this specific case will allow to claim it's a DBE61 only on Geode based products) Potential cons: extra struct field * Make the PCI id based auto-detection logic run over all the struct entries, instead of going with the first that meets all checks. If multiple are found, report ambiguity and require a board name to be specified by the user. This can be considered independently of the above options. Pros: * Doesn't automatically pick the first suitable entry when there is an ambiguity, whereas the pick is made purely on internal struct entry order * Takes care of the possible wrong choice auto-detection in this specific case, as two boards (DBE61 and DBE62) would get added, triggering the ambiguity check. But doesn't help for future cases where two boards with the same IDs don't get introduced at once; also a user friendly ambiguity report would report only the listed entries with the matched IDs, while it could be a completely different board that just isn't listed yet The patch I would like to see in SVN after this issue is taken care of is attached for reference. Without prior improvements to the general code in board_enable.c, applying this patch would make all Geode based products (that don't expose a separate PCI subsystem) be auto-detected as DBE61 (first in list) - if their ROM doesn't already have a coreboot image with a name that is listed in the struct. If this isn't a problem for the time being, then here's an addition to the commit log: Signed-off-by: Mart Raudsepp <mart.raudsepp(a)artecdesign.ee> Awaiting for comments and suggestions, Mart Raudsepp, Software Engineer, Artec Design LLC

6 14

Dump GPIO I/O Registers
by joe＠smittys.pointclark.net 22 Feb '08

22 Feb '08

Hello, How do I dump the GPIO I/O Registers in linux. I need to dump the GPIO's from the southbridge. Anyone? Thanks - Joe

11 31

Need a motherboard with PLCC 32 socket which supports the flashing rom
by Kiran Patil 22 Feb '08

22 Feb '08

Hello All, We have been learning coreboot since two months, we are unable to flash the rom (PMC004) either in Asrock or MSI borads. We have MSI 7260 and MSI 7250 and both are unable to flash as said in the Coreboot Documentation. Here in India we are unable to get the motherboards which are specified in the Documentation and we could get only MSI (7250/7260). Will any of you help us in sending the mother board with Bios Saviour kit ? We will be very thankful and looking forword to contribute. -Kiran Kiran Patil Technology Director Turtle Linux Labs. Value Your Freedom

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coreboot February 2008