coreboot February 2021

coreboot@coreboot.org

42 participants
35 discussions

Start a nNew thread

https://acpica.org/ Down for multiple hours
by selma.bensaid＠intel.com 17 Feb '21

17 Feb '21

Hi, Are you facing the same issue, does any one know how we can get this fixed? Thanks, Selma.

1 0

Mailing list issues, update
by Patrick Georgi 15 Feb '21

15 Feb '21

Hi everybody, There have been some issues with the mailing lists hosted at coreboot.org (spanning multiple projects: coreboot, flashrom, seabios and openbios) related to configuration changes in response to our precious little spammer. As a result some people have seen mailing list delivery to them disabled due to bounces. I reversed that change for the affected users so everybody's back in. To avoid this type of issue going forward, the server manual has been revised to point out some pitfalls in the mail server configuration and how to avoid them. Again thank you for your patience, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

1 0

Integrating (temporarily) proprietary tooling into our build system (was Re: Intel CBnT tooling and dealing with NDA)
by Nico Huber 14 Feb '21

14 Feb '21

Hi Arthur, I appreciate that you took the matter to the mailing list. This gives us the chance to really discuss it before we create yet another prece- dent. I urge all of us to not demand or make any hasty decision. Please understand that integration of any new proprietary component naturally wakes heavy feelings. It doesn't seem like there is a gua- rantee that Intel will allow you to release the source code of your tool. So for now it's proprietary software. Putting the whole story together, what you are asking for is the integration of a proprietary tool to configure proprietary firmware parts around a proprietary version* of what used to be a free-software project. (*existing coreboot port is only usable with an NDA) I don't say that's impossible. I just want you to understand what thoughts you have to expect. Actually, I believe it is possible and we should carefully assess a compromise as you suggested. However, it seems possible that the effort required by this discussion will outweigh the convenience you would buy yourself (and/or your customer) with such a compromise. Also, the question `how` might be even more delicate than `if` we should do this. Especially with a statically linked binary, there is a lot more code involved compared to what we'd pull in as source code. On 09.02.21 11:02, Arthur Heymans wrote: > My question to the community is if it would be ok to allow for the build system > integration code for KM and BPM generation to be integrated into the > master branch > before the code to the tooling is made public. > CBnT is an optional feature on Intel hardware and is implemented as an > optional feature in > coreboot. The tool is standalone and coreboot can still be built fine > without it. > > At the moment coreboot has code for xeon_sp in the master > branch without a public FSP too, with the promise that it will be > publicly released later > on by Intel. Compared to that the situation would be a little better: I can't agree to any such comparison. The situation is completely different. The risk of compromising the integrity of the whole build environment can't be compared to the risk of compromising single firmware builds. One might say it's the lesser insult, though. > we propose to add a binary tool (it's written in go so it's > automatically build as a static binary) to the blobs repo under a > licence similar to the one used for Intel FSP and MCU (allows > redistribution). We hope to remove it ASAP from there and build it > from source from 3rdparty/intel-sec-tools. > > We'd like to develop as close as possible to the coreboot master > branch, so we hope that this is an acceptable solution to the > community. > > So TL;DR: > - Is (temporarily) adding a tool to the blobs repo ok? I would say yes. But prefer a separate repository. > - Is integrating an (optional) not yet open tool into the build system ok? I don't think so. That's just my opinion. However, in case we proceed, I think there should be rules about it. Some things from the top of my mind (alas, I don't have the time to provide a comprehensive list of my thoughts): It should be *optional* (don't know why you put it in parentheses). There should be warnings about it in Kconfig at least. Probably even something like a "Press enter to proceed" during the build. Rationale: People need to know! Some people still care about security; others might have to, or even risk there status if they fail to. For instance at secunet, we build our software in a highly restricted environment. If we proceed here, secunet would likely stop mirroring the blobs repo just to be sure (it seems possible because we don't depend on it anymore). All components used to produce the binary and the environment in which it took place should be documented, also all further processing and checking, e.g. which antivirus software was run. Rationale: (ask somebody who used PCs in the '90s) > Let me know what you think. One more thought: Get a lawyer. Be 100% sure about the license. Make sure Intel agrees to it. FWIW, some people interpret the BSD license when used for binaries as a free pass to reverse-engineering and modifications (what I humbly presume Intel would not want for their binaries). Nico

2 1

Mailing list moderation
by Patrick Georgi 12 Feb '21

12 Feb '21

Hi everybody, As we're encountering a spam campaign right now by a sufficiently motivated actor to get through our filters I put the mailing list on moderation until this silliness subsides. For this reason delivery of mails sent to this list may be delayed. Thanks for your patience, Patrick -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

1 0

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 09 Feb '21

09 Feb '21

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 122 new defect(s) introduced to coreboot found with Coverity Scan. 11 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 20 of 122 defect(s) ** CID 1446367: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/usb_pd_policy.c: 422 in is_usb4_vdo() ________________________________________________________________________________________________________ *** CID 1446367: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/usb_pd_policy.c: 422 in is_usb4_vdo() 416 if (IS_PD_IDH_UFP_PTYPE(ptype)) { 417 /* 418 * Ref: USB Type-C Cable and Connector Specification 419 * Figure 5-1 USB4 Discovery and Entry Flow Model 420 * Device USB4 VDO detection. 421 */ >>> CID 1446367: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && is_vdo_present(cnt, 4)" is always false regardless of the values of its operands. This occurs as the logical first operand of "&&". 422 return IS_ENABLED(CONFIG_USB_PD_USB4) && 423 is_vdo_present(cnt, VDO_INDEX_PTYPE_UFP1_VDO) && 424 PD_PRODUCT_IS_USB4(payload[VDO_INDEX_PTYPE_UFP1_VDO]); 425 } 426 return false; 427 } ** CID 1446366: Parse warnings (PARSE_ERROR) /3rdparty/chromeec/common/motion_lid.c: 104 in () ________________________________________________________________________________________________________ *** CID 1446366: Parse warnings (PARSE_ERROR) /3rdparty/chromeec/common/motion_lid.c: 104 in () 98 static const struct motion_sensor_t * const accel_base = 99 &motion_sensors[CONFIG_LID_ANGLE_SENSOR_BASE]; 100 static const struct motion_sensor_t * const accel_lid = 101 &motion_sensors[CONFIG_LID_ANGLE_SENSOR_LID]; 102 103 STATIC_IF(CONFIG_TABLET_MODE) void motion_lid_set_tablet_mode(int reliable); >>> CID 1446366: Parse warnings (PARSE_ERROR) >>> expression must be an integral constant expression 104 STATIC_IF(CONFIG_TABLET_MODE) int lid_angle_set_tablet_mode_threshold( 105 int angle, int hys); 106 107 STATIC_IF(CONFIG_TABLET_MODE) fp_t tablet_zone_lid_angle; 108 STATIC_IF(CONFIG_TABLET_MODE) fp_t laptop_zone_lid_angle; 109 STATIC_IF(CONFIG_TABLET_MODE) int tablet_mode_lid_angle; ** CID 1446365: (DEADCODE) /3rdparty/chromeec/driver/charger/isl923x.c: 512 in isl923x_init() /3rdparty/chromeec/driver/charger/isl923x.c: 608 in isl923x_init() /3rdparty/chromeec/driver/charger/isl923x.c: 473 in isl923x_init() /3rdparty/chromeec/driver/charger/isl923x.c: 577 in isl923x_init() /3rdparty/chromeec/driver/charger/isl923x.c: 591 in isl923x_init() ________________________________________________________________________________________________________ *** CID 1446365: (DEADCODE) /3rdparty/chromeec/driver/charger/isl923x.c: 512 in isl923x_init() 506 reg | 507 ISL9237_C1_SWITCH_FREQ_599K)) 508 goto init_fail; 509 } 510 511 if (IS_ENABLED(CONFIG_TRICKLE_CHARGING)) >>> CID 1446365: (DEADCODE) >>> Execution cannot reach this statement: "if (raw_write16(chgnum, 62,...". 512 if (raw_write16(chgnum, ISL923X_REG_SYS_VOLTAGE_MIN, 513 precharge_voltage)) 514 goto init_fail; 515 516 /* 517 * [10:9]: Prochot# Debounce time /3rdparty/chromeec/driver/charger/isl923x.c: 608 in isl923x_init() 602 if (IS_ENABLED(CHARGER_ISL9238X) || 603 IS_ENABLED(CONFIG_CHARGER_RAA489000)) { 604 /* 605 * Don't reread the prog pin and don't reload the ILIM on ACIN. 606 * For the RAA489000, just don't reload ACLIM. 607 */ >>> CID 1446365: (DEADCODE) >>> Execution cannot reach this statement: "if (raw_read16(chgnum, 76, ...". 608 if (raw_read16(chgnum, ISL9238_REG_CONTROL3, &reg)) 609 goto init_fail; 610 reg |= ISL9238_C3_NO_RELOAD_ACLIM_ON_ACIN; 611 if (!IS_ENABLED(CONFIG_CHARGER_RAA489000)) 612 reg |= ISL9238_C3_NO_REREAD_PROG_PIN; 613 /3rdparty/chromeec/driver/charger/isl923x.c: 473 in isl923x_init() 467 int reg; 468 const struct battery_info *bi = battery_get_info(); 469 int precharge_voltage = bi->precharge_voltage ? 470 bi->precharge_voltage : bi->voltage_min; 471 472 if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) { >>> CID 1446365: (DEADCODE) >>> Execution cannot reach this statement: "if (0) { if (raw_read16(c...". 473 if (CONFIG_CHARGER_SENSE_RESISTOR == 474 CONFIG_CHARGER_SENSE_RESISTOR_AC) { 475 /* 476 * A 1:1 ratio for Rs1:Rs2 is allowed, but Control4 477 * register Bit<11> must be set. 478 */ /3rdparty/chromeec/driver/charger/isl923x.c: 577 in isl923x_init() 571 if (raw_write16(chgnum, ISL923X_REG_CONTROL0, reg)) 572 goto init_fail; 573 } 574 575 if (IS_ENABLED(CONFIG_CHARGER_ISL9238C)) { 576 /* b/155366741: enable slew rate control */ >>> CID 1446365: (DEADCODE) >>> Execution cannot reach this statement: "if (raw_read16(chgnum, 55, ...". 577 if (raw_read16(chgnum, ISL9238C_REG_CONTROL6, &reg)) 578 goto init_fail; 579 580 reg |= ISL9238C_C6_SLEW_RATE_CONTROL; 581 582 if (raw_write16(chgnum, ISL9238C_REG_CONTROL6, reg)) /3rdparty/chromeec/driver/charger/isl923x.c: 591 in isl923x_init() 585 586 if (IS_ENABLED(CONFIG_CHARGER_RAA489000)) { 587 /* 588 * Return the BFET to normal operation as it may have been 589 * turned off when entering hibernate. 590 */ >>> CID 1446365: (DEADCODE) >>> Execution cannot reach this statement: "if (raw_read16(chgnum, 60, ...". 591 if (raw_read16(chgnum, ISL923X_REG_CONTROL1, &reg)) 592 goto init_fail; 593 reg &= ~RAA489000_C1_BGATE_FORCE_OFF; 594 if (raw_write16(chgnum, ISL923X_REG_CONTROL1, reg)) 595 goto init_fail; 596 } ** CID 1446364: Control flow issues (DEADCODE) /3rdparty/chromeec/common/keyboard_8042.c: 882 in i8042_handle_from_host() ________________________________________________________________________________________________________ *** CID 1446364: Control flow issues (DEADCODE) /3rdparty/chromeec/common/keyboard_8042.c: 882 in i8042_handle_from_host() 876 if (h.type == HOST_COMMAND) { 877 ret_len = handle_keyboard_command(h.byte, output); 878 } else { 879 CPRINTS5("KB recv data: 0x%02x", h.byte); 880 kblog_put('d', h.byte); 881 >>> CID 1446364: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "handle_mouse_data(h.byte, output, &ret_len)" inside this statement: "if (({ int __undefined = ...". 882 if (IS_ENABLED(CONFIG_8042_AUX) && 883 handle_mouse_data(h.byte, output, &ret_len)) 884 chan = CHAN_AUX; 885 else 886 ret_len = handle_keyboard_data(h.byte, output); 887 } ** CID 1446363: Control flow issues (DEADCODE) /3rdparty/chromeec/common/throttle_ap.c: 93 in prochot_input_deferred() ________________________________________________________________________________________________________ *** CID 1446363: Control flow issues (DEADCODE) /3rdparty/chromeec/common/throttle_ap.c: 93 in prochot_input_deferred() 87 */ 88 ASSERT(signal_is_gpio(gpio_prochot_in)); 89 90 prochot_in = gpio_get_level(gpio_prochot_in); 91 92 if (IS_ENABLED(CONFIG_CPU_PROCHOT_ACTIVE_LOW)) >>> CID 1446363: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "prochot_in" inside this statement: "prochot_in = !prochot_in;". 93 prochot_in = !prochot_in; 94 95 if (prochot_in == debounced_prochot_in) 96 return; 97 98 debounced_prochot_in = prochot_in; ** CID 1446362: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/motion_sense.c: 1415 in host_cmd_motion_sense() ________________________________________________________________________________________________________ *** CID 1446362: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/motion_sense.c: 1415 in host_cmd_motion_sense() 1409 #endif /* defined(CONFIG_GESTURE_HOST_DETECTION) */ 1410 1411 #ifdef CONFIG_ACCEL_SPOOF_MODE 1412 case MOTIONSENSE_CMD_SPOOF: { 1413 /* spoof activity if it is activity sensor */ 1414 if (IS_ENABLED(CONFIG_GESTURE_HOST_DETECTION) && >>> CID 1446362: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "(*in).spoof.sensor_id == -1" is always false regardless of the values of its operands. This occurs as the logical second operand of "&&". 1415 in->spoof.sensor_id == MOTION_SENSE_ACTIVITY_SENSOR_ID) { 1416 switch (in->spoof.activity_num) { 1417 #ifdef CONFIG_BODY_DETECTION 1418 case MOTIONSENSE_ACTIVITY_BODY_DETECTION: 1419 switch (in->spoof.spoof_enable) { 1420 case MOTIONSENSE_SPOOF_MODE_DISABLE: ** CID 1446361: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_policy.c: 321 in is_cable_ready_to_enter_usb4() ________________________________________________________________________________________________________ *** CID 1446361: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_policy.c: 321 in is_cable_ready_to_enter_usb4() 315 * 316 */ 317 static bool is_cable_ready_to_enter_usb4(int port, int cnt) 318 { 319 /* TODO: USB4 enter mode for Active cables */ 320 struct pd_discovery *disc = &discovery[port][TCPC_TX_SOP_PRIME]; >>> CID 1446361: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE" inside this statement: "if (({ int __undefined = ...". 321 if (IS_ENABLED(CONFIG_USB_PD_USB4) && 322 (get_usb_pd_cable_type(port) == IDH_PTYPE_PCABLE) && 323 is_vdo_present(cnt, VDO_INDEX_PTYPE_CABLE1)) { 324 switch (cable[port].rev) { 325 case PD_REV30: 326 switch (disc->identity.product_t1.p_rev30.ss) { ** CID 1446360: Control flow issues (DEADCODE) /3rdparty/chromeec/common/motion_sense.c: 435 in motion_sense_switch_sensor_rate() ________________________________________________________________________________________________________ *** CID 1446360: Control flow issues (DEADCODE) /3rdparty/chromeec/common/motion_sense.c: 435 in motion_sense_switch_sensor_rate() 429 if (IS_ENABLED(CONFIG_GESTURE_DETECTION) && 430 (sensor_active == SENSOR_ACTIVE_S5)) { 431 uint32_t enabled = 0, disabled, mask; 432 433 mask = CONFIG_GESTURE_DETECTION_MASK; 434 while (mask) { >>> CID 1446360: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "i = get_next_bit(&mask);". 435 i = get_next_bit(&mask); 436 sensor = &motion_sensors[i]; 437 if (sensor->state != SENSOR_INITIALIZED) 438 continue; 439 sensor->drv->list_activities(sensor, 440 &enabled, &disabled); ** CID 1446359: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/i2c_controller.c: 545 in i2c_field_update8() ________________________________________________________________________________________________________ *** CID 1446359: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/i2c_controller.c: 545 in i2c_field_update8() 539 rv = i2c_read8(port, slave_addr_flags, offset, &read_val); 540 if (rv) 541 return rv; 542 543 write_val = (read_val & (~field_mask)) | set_value; 544 >>> CID 1446359: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && write_val == read_val" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 545 if (IS_ENABLED(CONFIG_I2C_UPDATE_IF_CHANGED) && write_val == read_val) 546 return EC_SUCCESS; 547 548 return i2c_write8(port, slave_addr_flags, offset, write_val); 549 } 550 ** CID 1446358: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/main.c: 205 in main() ________________________________________________________________________________________________________ *** CID 1446358: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/main.c: 205 in main() 199 #endif 200 #if defined(CONFIG_DEDICATED_RECOVERY_BUTTON) || defined(CONFIG_VOLUME_BUTTONS) 201 button_init(); 202 #endif /* defined(CONFIG_DEDICATED_RECOVERY_BUTTON | CONFIG_VOLUME_BUTTONS) */ 203 204 /* Make sure recovery boot won't be paused. */ >>> CID 1446358: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && system_is_manual_recovery()" is always false regardless of the values of its operands. This occurs as the logical first operand of "&&". 205 if (IS_ENABLED(CONFIG_POWER_BUTTON_INIT_IDLE) 206 && system_is_manual_recovery() 207 && (system_get_reset_flags() & EC_RESET_FLAG_AP_IDLE)) { 208 CPRINTS("Clear AP_IDLE for recovery mode"); 209 system_clear_reset_flags(EC_RESET_FLAG_AP_IDLE); 210 } ** CID 1446357: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_host_cmd.c: 509 in hc_get_pd_port_caps() ________________________________________________________________________________________________________ *** CID 1446357: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_host_cmd.c: 509 in hc_get_pd_port_caps() 503 r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_SOURCE; 504 else 505 r->pd_try_power_role_cap = EC_PD_TRY_POWER_ROLE_NONE; 506 507 if (IS_ENABLED(CONFIG_USB_VPD) || 508 IS_ENABLED(CONFIG_USB_CTVPD)) >>> CID 1446357: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "r->pd_data_role_cap = EC_PD...". 509 r->pd_data_role_cap = EC_PD_DATA_ROLE_UFP; 510 else 511 r->pd_data_role_cap = EC_PD_DATA_ROLE_DUAL; 512 513 /* Allow boards to override the locations from UNKNOWN if desired */ 514 r->pd_port_location = board_get_pd_port_location(p->port); ** CID 1446356: (DEADCODE) /3rdparty/chromeec/util/genvif.c: 3165 in init_vif_component_usb_data_ufp_fields() /3rdparty/chromeec/util/genvif.c: 3170 in init_vif_component_usb_data_ufp_fields() /3rdparty/chromeec/util/genvif.c: 3150 in init_vif_component_usb_data_ufp_fields() /3rdparty/chromeec/util/genvif.c: 3160 in init_vif_component_usb_data_ufp_fields() ________________________________________________________________________________________________________ *** CID 1446356: (DEADCODE) /3rdparty/chromeec/util/genvif.c: 3165 in init_vif_component_usb_data_ufp_fields() 3159 break; 3160 case USB_GEN21: 3161 set_vif_field_itss(&vif_fields[Device_Speed], 3162 vif_component_name[Device_Speed], 3163 USB_GEN21, "USB 3.2 GEN 2x1"); 3164 break; >>> CID 1446356: (DEADCODE) >>> Execution cannot reach this statement: "case USB_GEN12:". 3165 case USB_GEN12: 3166 set_vif_field_itss(&vif_fields[Device_Speed], 3167 vif_component_name[Device_Speed], 3168 USB_GEN12, "USB 3.2 GEN 1x2"); 3169 break; 3170 case USB_GEN22: /3rdparty/chromeec/util/genvif.c: 3170 in init_vif_component_usb_data_ufp_fields() 3164 break; 3165 case USB_GEN12: 3166 set_vif_field_itss(&vif_fields[Device_Speed], 3167 vif_component_name[Device_Speed], 3168 USB_GEN12, "USB 3.2 GEN 1x2"); 3169 break; >>> CID 1446356: (DEADCODE) >>> Execution cannot reach this statement: "case USB_GEN22:". 3170 case USB_GEN22: 3171 set_vif_field_itss(&vif_fields[Device_Speed], 3172 vif_component_name[Device_Speed], 3173 USB_GEN22, "USB 3.2 GEN 2x2"); 3174 break; 3175 } /3rdparty/chromeec/util/genvif.c: 3150 in init_vif_component_usb_data_ufp_fields() 3144 &vif_fields[Device_Supports_USB_Data], 3145 &supports_usb_data)) 3146 supports_usb_data = false; 3147 3148 if (supports_usb_data) { 3149 switch (ds) { >>> CID 1446356: (DEADCODE) >>> Execution cannot reach this statement: "case USB_2:". 3150 case USB_2: 3151 set_vif_field_itss(&vif_fields[Device_Speed], 3152 vif_component_name[Device_Speed], 3153 USB_2, "USB 2"); 3154 break; 3155 case USB_GEN11: /3rdparty/chromeec/util/genvif.c: 3160 in init_vif_component_usb_data_ufp_fields() 3154 break; 3155 case USB_GEN11: 3156 set_vif_field_itss(&vif_fields[Device_Speed], 3157 vif_component_name[Device_Speed], 3158 USB_GEN11, "USB 3.2 GEN 1x1"); 3159 break; >>> CID 1446356: (DEADCODE) >>> Execution cannot reach this statement: "case USB_GEN21:". 3160 case USB_GEN21: 3161 set_vif_field_itss(&vif_fields[Device_Speed], 3162 vif_component_name[Device_Speed], 3163 USB_GEN21, "USB 3.2 GEN 2x1"); 3164 break; 3165 case USB_GEN12: ** CID 1446355: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/keyboard_8042.c: 987 in send_aux_data_to_host_deferred() ________________________________________________________________________________________________________ *** CID 1446355: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/keyboard_8042.c: 987 in send_aux_data_to_host_deferred() 981 if (IS_ENABLED(CONFIG_DEVICE_EVENT) && 982 chipset_in_state(CHIPSET_STATE_ANY_SUSPEND)) 983 device_set_single_event(EC_DEVICE_EVENT_TRACKPAD); 984 985 while (!queue_is_empty(&aux_to_host_queue)) { 986 queue_remove_unit(&aux_to_host_queue, &data); >>> CID 1446355: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "aux_chan_enabled && ({...; 0;})" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 987 if (aux_chan_enabled && IS_ENABLED(CONFIG_8042_AUX)) 988 i8042_send_to_host(1, &data, CHAN_AUX); 989 else 990 CPRINTS("AUX Callback ignored"); 991 } 992 } ** CID 1446354: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_common.c: 459 in usb_mux_set_safe_mode() ________________________________________________________________________________________________________ *** CID 1446354: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_common.c: 459 in usb_mux_set_safe_mode() 453 USB_SWITCH_CONNECT, 454 polarity_rm_dts(pd_get_polarity(port))); 455 } 456 457 /* Isolate the SBU lines. */ 458 if (IS_ENABLED(CONFIG_USBC_PPC_SBU)) >>> CID 1446354: Control flow issues (DEADCODE) >>> Execution cannot reach this statement: "ppc_set_sbu(port, 0);". 459 ppc_set_sbu(port, 0); 460 } 461 462 static void pd_send_hard_reset(int port) 463 { 464 task_set_event(PD_PORT_TO_TASK_ID(port), PD_EVENT_SEND_HARD_RESET, 0); ** CID 1446353: (PARSE_ERROR) /3rdparty/chromeec/driver/tcpm/tcpci.c: 28 in () /3rdparty/chromeec/driver/tcpm/tcpci.c: 30 in () /3rdparty/chromeec/driver/tcpm/tcpci.c: 28 in () /3rdparty/chromeec/driver/tcpm/tcpci.c: 28 in () ________________________________________________________________________________________________________ *** CID 1446353: (PARSE_ERROR) /3rdparty/chromeec/driver/tcpm/tcpci.c: 28 in () 22 #include "usb_pd_tcpc.h" 23 #include "util.h" 24 25 #define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) 26 #define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) 27 >>> CID 1446353: (PARSE_ERROR) >>> expression must be an integral constant expression 28 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 29 bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 30 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 31 int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 32 33 #define TCPC_FLAGS_VSAFE0V(_flags) \ /3rdparty/chromeec/driver/tcpm/tcpci.c: 30 in () 24 25 #define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) 26 #define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) 27 28 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 29 bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT]; >>> CID 1446353: (PARSE_ERROR) >>> expression must be an integral constant expression 30 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 31 int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 32 33 #define TCPC_FLAGS_VSAFE0V(_flags) \ 34 ((_flags & TCPC_FLAGS_TCPCI_REV2_0) && \ 35 !(_flags & TCPC_FLAGS_TCPCI_REV2_0_NO_VSAFE0V)) /3rdparty/chromeec/driver/tcpm/tcpci.c: 28 in () 22 #include "usb_pd_tcpc.h" 23 #include "util.h" 24 25 #define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) 26 #define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) 27 >>> CID 1446353: (PARSE_ERROR) >>> function call is not allowed in a constant expression 28 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 29 bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 30 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 31 int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 32 33 #define TCPC_FLAGS_VSAFE0V(_flags) \ /3rdparty/chromeec/driver/tcpm/tcpci.c: 28 in () 22 #include "usb_pd_tcpc.h" 23 #include "util.h" 24 25 #define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args) 26 #define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args) 27 >>> CID 1446353: (PARSE_ERROR) >>> expression must have integral type 28 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 29 bool sop_prime_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 30 STATIC_IF(CONFIG_USB_PD_DECODE_SOP) 31 int rx_en[CONFIG_USB_PD_PORT_MAX_COUNT]; 32 33 #define TCPC_FLAGS_VSAFE0V(_flags) \ ** CID 1446352: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/motion_sense.c: 1101 in host_cmd_motion_sense() ________________________________________________________________________________________________________ *** CID 1446352: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/motion_sense.c: 1101 in host_cmd_motion_sense() 1095 out->info_3.min_frequency = sensor->min_frequency; 1096 out->info_3.max_frequency = sensor->max_frequency; 1097 out->info_3.fifo_max_event_count = CONFIG_ACCEL_FIFO_SIZE; 1098 args->response_size = sizeof(out->info_3); 1099 } 1100 if (args->version >= 4) { >>> CID 1446352: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && sensor->drv->read_temp" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 1101 if (IS_ENABLED(CONFIG_ONLINE_CALIB) && 1102 sensor->drv->read_temp) 1103 out->info_4.flags |= 1104 MOTION_SENSE_CMD_INFO_FLAG_ONLINE_CALIB; 1105 args->response_size = sizeof(out->info_4); 1106 } ** CID 1446351: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_policy.c: 422 in is_usb4_vdo() ________________________________________________________________________________________________________ *** CID 1446351: Control flow issues (DEADCODE) /3rdparty/chromeec/common/usb_pd_policy.c: 422 in is_usb4_vdo() 416 if (IS_PD_IDH_UFP_PTYPE(ptype)) { 417 /* 418 * Ref: USB Type-C Cable and Connector Specification 419 * Figure 5-1 USB4 Discovery and Entry Flow Model 420 * Device USB4 VDO detection. 421 */ >>> CID 1446351: Control flow issues (DEADCODE) >>> Execution cannot reach the expression "is_vdo_present(cnt, 4)" inside this statement: "return ({ int __undefined...". 422 return IS_ENABLED(CONFIG_USB_PD_USB4) && 423 is_vdo_present(cnt, VDO_INDEX_PTYPE_UFP1_VDO) && 424 PD_PRODUCT_IS_USB4(payload[VDO_INDEX_PTYPE_UFP1_VDO]); 425 } 426 return false; 427 } ** CID 1446350: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/driver/charger/isl923x.c: 1027 in console_command_amon_bmon() ________________________________________________________________________________________________________ *** CID 1446350: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/driver/charger/isl923x.c: 1027 in console_command_amon_bmon() 1021 int chgnum = 0; 1022 char *e; 1023 1024 if (argc >= 2) { 1025 print_ac = (argv[1][0] == 'a'); 1026 print_battery = (argv[1][0] == 'b'); >>> CID 1446350: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && argv[1][1] != 0" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 1027 if (IS_ENABLED(CHARGER_ISL9238X) && argv[1][1] != '\0') { 1028 print_charge = (argv[1][1] == 'c'); 1029 print_discharge = (argv[1][1] == 'd'); 1030 } 1031 if (argc >= 3) { 1032 chgnum = strtoi(argv[2], &e, 10); ** CID 1446349: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/i2c_controller.c: 331 in platform_ec_i2c_write() ________________________________________________________________________________________________________ *** CID 1446349: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/i2c_controller.c: 331 in platform_ec_i2c_write() 325 const uint16_t slave_addr_flags, 326 const uint8_t *out, int out_size) 327 { 328 if (!IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) 329 return EC_ERROR_UNIMPLEMENTED; 330 >>> CID 1446349: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && slave_addr_flags & (8192U /* 1U << 13 */)" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 331 if (IS_ENABLED(CONFIG_SMBUS_PEC) && I2C_USE_PEC(slave_addr_flags)) { 332 int i, rv; 333 uint8_t addr_8bit = I2C_STRIP_FLAGS(slave_addr_flags) << 1; 334 uint8_t pec; 335 336 pec = cros_crc8(&addr_8bit, 1); ** CID 1446348: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/gpio.c: 209 in gpio_or_ioex_set_level() ________________________________________________________________________________________________________ *** CID 1446348: Integer handling issues (CONSTANT_EXPRESSION_RESULT) /3rdparty/chromeec/common/gpio.c: 209 in gpio_or_ioex_set_level() 203 cprints(channel, "Set %s: %d", gpio_get_name(signal), value); 204 gpio_set_level(signal, value); 205 } 206 207 void gpio_or_ioex_set_level(int signal, int value) 208 { >>> CID 1446348: Integer handling issues (CONSTANT_EXPRESSION_RESULT) >>> "({...; 0;}) && signal_is_ioex(signal)" is always false regardless of the values of its operands. This occurs as the logical operand of "if". 209 if (IS_ENABLED(CONFIG_IO_EXPANDER) && signal_is_ioex(signal)) 210 ioex_set_level(signal, value); 211 else 212 gpio_set_level(signal, value); 213 } 214 ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u15810271.ct.sendgrid.net/ls/click?upn=HRESupC-2F2Czv4BOaCWWCy7my0P…

1 0

Testing code present in SMM
by Mick 08 Feb '21

08 Feb '21

Dear everyone, For my master project I will apply hardening techniques (sanitizers/CFI) to System Mangement Mode (SMM). Now for my evaluation, I want to test code in SMM and ideally cover all SMI handlers coreboot offers. However, in my experience, System Management Interrupts (SMIs) rarely trigger and the variety in SMIs is also rather low (testing via QEMU). I was wondering whether anyone is familiar with testing such a low-level component. In the coreboot repository, I couldn't find any tests related to SMM and looking online also hasn't provided me any answers. Is there anyone who has experience with similar problems or can perhaps point me into the right direction, as I am inexperienced with testing such low-level components. I hope I've explained myself clearly, if not, please indicate so! Kind regards, Mick

3 4

coreboot image forIntel Harcuvar CRB
by Tirumalesh 07 Feb '21

07 Feb '21

Hi, I am trying to boot Coreboot on Intel Harcuvar CRB. The steps I tried -> make menuconfig selected Intel->Harcuvar ->make (got coreboot.rom 16MB) -> split –b 8M –a 1 –d coreboot.rom coreboot with dediprog programmed last 8M with coreboot1 (file generated with Split) Not able to see any output on UART. please let me know if Sam missing any configs/steps here. Any help is greatly appreciated. Thanks, Tirumalesh.

5 7

Seabios cannot boot Linux on custom mainboard
by Anatolii Vorobev 07 Feb '21

07 Feb '21

Dear Coreboot list, I'm still trying to bring up custom mainboard with Apollo Lake E3950 SoC and LPDDR4 memory. I have successfully built images with different payloads that passes all the initializations but all of them fails to boot further: 1. Coreboot + Seabios + bootable USB with Linux. Stuck when booting from USB (but I am able to reboot the system using a Ctr-Alt-Del on a keyboard) 2. Coreboot + Seabios + memtest. Stuck on booting memtest (CtrAltDel does nothing) 3. Coreboot + Seabios + coreinfo. General protection fault 4. Coreboot + LinuxBoot. Works on QEMU, hangs on my board (CtrAltDel does nothing) Looks like a hardware or FSP configuration issue. But I cannot find a way to debug this thing and find the reason. For instance, how I can understand why Linux kernel (or memtest) fails to boot when there is no debug output at all? You will find Coreboot logs and .config for Seabios image (memtest, coreinfo, usb). PS Still have no HDMI output and DCI debug. Serial console is my only option for now. Best Regards, Anatolii Vorobev

2 1

Please review a tiny CB:48616 URL fix for a tint payload
by Mike Banon 06 Feb '21

06 Feb '21

https://review.coreboot.org/c/coreboot/+/48616 - without this tiny URL fix, building a secondary tint payload results in an error (since the old archive became unavailable). Would be nice if you can review this patch to bring back a wonderful tint game -- Best regards, Mike Banon Open Source Community Manager of 3mdeb - https://3mdeb.com/

1 0

Which of these mini-ITX mainboards is best supported?
by U'll Be King Of The Stars 06 Feb '21

06 Feb '21

Hello! I am presently doing a massive hardware clearance and this includes selling (or giving away) many mainboards that are coreboot compatible. I'm not super experienced with getting my hands dirty with coreboot development. I am jumping in the deep end with these -- and a few other models -- and I would like to keep the boards of the model that are supported best by coreboot. The boards I refer to are the following. I have each of the following models in some quantity: - Intel D510MO (my personal favorite of this list) - Intel D945GCLF (and D945GCLF2, D945GCLF2D) - Intel D410PT (doesn't seem to be in current source tree) - Gigabyte GA-G41M-ES2L Can somebody please advise? As indicated I would like to keep the D510MO boards for coreboot hacking and experimenting, and for cluster builds. But I heard somebody say the D510MO presently has issues (I don't know any more details than this at present and they weren't able to elaborate). If there is a better choice of board to keep, while clearing out the others, I'd like to know. But if the issue with the D510MO is of the nature that somebody like me (experienced software engineer; kind of new to coreboot) has a pretty good chance of fixing up to a high standard, please let me know!! I'm hope to hear from somebody soon! Thanks!! Kind regards, Andrew

5 6

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2021