coreboot image forIntel Harcuvar CRB

[Tirumalesh]

Hi,

I am trying to boot Coreboot on Intel Harcuvar CRB.

The steps I tried
-> make menuconfig
selected Intel->Harcuvar
->make (got coreboot.rom 16MB)

-> split –b 8M –a 1 –d coreboot.rom coreboot
with dediprog programmed last 8M with coreboot1 (file generated with Split)

Not able to see any output on UART. please let me know if Sam missing any configs/steps here.
Any help is greatly appreciated.

Thanks,
Tirumalesh.

[Tirumalesh]

Hi,

I also tried

- config_intel_harcuvar config
- Built complete image with Intel flash image tool

Still not able to see anything on UART. Please some one help with some pointers here.

Thanks,
Tirumalesh.
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Monday, February 1, 2021 12:02 PM, Tirumalesh via coreboot  wrote:
> Hi,
>
> I am trying to boot Coreboot on Intel Harcuvar CRB.
>
> The steps I tried
> -> make menuconfig
> selected Intel->Harcuvar
> ->make (got coreboot.rom 16MB)
>
> -> split –b 8M –a 1 –d coreboot.rom coreboot
> with dediprog programmed last 8M with coreboot1 (file generated with Split)
>
> Not able to see any output on UART. please let me know if Sam missing any configs/steps here.
> Any help is greatly appreciated.
>
> Thanks,
> Tirumalesh.

[Julien Viard de Galbert]

Hi,

You should probably try an older version of coreboot, close to when the
harcuvar board was introduced and check if that version outputs anything
on UART.
I did that on a custom board using denverton recently and already
proposed a few fix, but I don't have an harcuvar board to test.

Hope this helps,

Julien
On Tue, Feb 02, 2021 at 08:27:03AM +0000, Tirumalesh wrote:
> Hi,
>
> I also tried
> config_intel_harcuvar config
> Built complete image with Intel flash image tool
>
> Still not able to see anything on UART. Please some one help with some pointers here.
>
> Thanks,
> Tirumalesh.
> ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> On Monday, February 1, 2021 12:02 PM, Tirumalesh via coreboot  wrote:
> > Hi,
> >
> > I am trying to boot Coreboot on Intel Harcuvar CRB.
> >
> > The steps I tried
> > -> make menuconfig
> > selected Intel->Harcuvar
> > ->make (got coreboot.rom 16MB)
> >
> > -> split –b 8M –a 1 –d coreboot.rom coreboot
> > with dediprog programmed last 8M with coreboot1 (file generated with Split)
> >
> > Not able to see any output on UART. please let me know if Sam missing any configs/steps here.
> > Any help is greatly appreciated.
> >
> > Thanks,
> > Tirumalesh.
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

[Tirumalesh]

Thanks for the suggestion I will try that.
If you can point me to your fixes I can try them in harcuvar and let you know.

Thanks,
Tirumalesh

On Fri, Feb 5, 2021 at 1:43 AM, Julien Viard de Galbert  wrote:
> Hi,
>
> You should probably try an older version of coreboot, close to when the
> harcuvar board was introduced and check if that version outputs anything
> on UART.
> I did that on a custom board using denverton recently and already
> proposed a few fix, but I don't have an harcuvar board to test.
>
> Hope this helps,
>
> Julien
> On Tue, Feb 02, 2021 at 08:27:03AM +0000, Tirumalesh wrote:
> > Hi,
> >
> > I also tried
> > config_intel_harcuvar config
> > Built complete image with Intel flash image tool
> >
> > Still not able to see anything on UART. Please some one help with some pointers here.
> >
> > Thanks,
> > Tirumalesh.
> > ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
> > On Monday, February 1, 2021 12:02 PM, Tirumalesh via coreboot  wrote:
> > > Hi,
> > >
> > > I am trying to boot Coreboot on Intel Harcuvar CRB.
> > >
> > > The steps I tried
> > > -> make menuconfig
> > > selected Intel->Harcuvar
> > > ->make (got coreboot.rom 16MB)
> > >
> > > -> split –b 8M –a 1 –d coreboot.rom coreboot
> > > with dediprog programmed last 8M with coreboot1 (file generated with Split)
> > >
> > > Not able to see any output on UART. please let me know if Sam missing any configs/steps here.
> > > Any help is greatly appreciated.
> > >
> > > Thanks,
> > > Tirumalesh.
> > coreboot mailing list -- [e-mail]
> > To unsubscribe send an email to [e-mail]
>
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

[Javier Galindo]

Did you set the following in your config file --> CONFIG_LEGACY_UART_MODE=y

Also have you setup all the proper fsp/ucode binaries that are commented out in the config file (just did a quick review):

#Sample settings for Denverton-NS FSP.
#CONFIG_ADD_FSP_BINARIES=y
#CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
#CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
#CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
#CONFIG_FSP_CAR=y

#Sample settings for microcode definitions.
#CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
#CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y

Unfortunately all my harcuvar work has also been on a fairly old tree of coreboot.

I'll give it a try on my Harcuvar if you don't make any progress, but it won't be until the weekend.

[Tirumalesh]

It seems the FSP binaries are auto included, and the configs seems to be of no effect.
Is it not right?

If so I will try to add binaries and microcode header file.

Thanks,
Tirumalesh

On Fri, Feb 5, 2021 at 11:22 AM, Javier Galindo  wrote:
> Did you set the following in your config file --> CONFIG_LEGACY_UART_MODE=y
>
> Also have you setup all the proper fsp/ucode binaries that are commented out in the config file (just did a quick review):
>
> #Sample settings for Denverton-NS FSP.
> #CONFIG_ADD_FSP_BINARIES=y
> #CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
> #CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
> #CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
> #CONFIG_FSP_CAR=y
>
> #Sample settings for microcode definitions.
> #CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
> #CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y
>
> Unfortunately all my harcuvar work has also been on a fairly old tree of coreboot.
>
> I'll give it a try on my Harcuvar if you don't make any progress, but it won't be until the weekend.
> _______________________________________________
> coreboot mailing list -- [e-mail]
> To unsubscribe send an email to [e-mail]

[Szafranski, MariuszX]

Hi Tirumalesh,

Please verify if FSP is correctly integrated. Especially if FSP-T part is enabled and used for setting up CAR.
config mainboard section:
vendor->Intel,
model->Harcuvar,
romsize ->16M, (insert your actual SPI flash size)
cbfs size 8M (0x800000) (or adjust for your needs)
config chipset:
                check  Enable High-speed UART debug port selected by UART_FOR_CONSOLE (enable for non legacy UART mode, disable for legacy)
                cache as ram implementation -> Use FSP CAR
                UART mode – leave at default non legacy mode (or enable if needed – adjust other settings for legacy mode)
                Verify if generate from tree is selected for microcode (Include CPU microcode in CBFS (Generate from tree))
config generic drivers:
                UART's PCI bus, device, function address - 0x8000d000
                Verify if “serial port” on superior is unchecked (need to be when using UART in legacy mode)
config console:
                verify if two first options (bootblock console and postcar console) are enabled

As I remember there are two serial port connectors – check if you are using correct one (try both)

BR,
Mariusz

From: Tirumalesh 
Sent: Friday, February 5, 2021 8:54 AM
To: Javier Galindo ; [e-mail]
Subject: [coreboot] Re: coreboot image forIntel Harcuvar CRB

It seems the FSP binaries are auto included, and the configs seems to be of no effect.
Is it not right?

If so I will try to add binaries and microcode header file.

Thanks,
Tirumalesh

On Fri, Feb 5, 2021 at 11:22 AM, Javier Galindo <[e-mail]> wrote:
Did you set the following in your config file --> CONFIG_LEGACY_UART_MODE=y

Also have you setup all the proper fsp/ucode binaries that are commented out in the config file (just did a quick review):

#Sample settings for Denverton-NS FSP.
#CONFIG_ADD_FSP_BINARIES=y
#CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
#CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
#CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
#CONFIG_FSP_CAR=y

#Sample settings for microcode definitions.
#CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
#CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y

Unfortunately all my harcuvar work has also been on a fairly old tree of coreboot.

I'll give it a try on my Harcuvar if you don't make any progress, but it won't be until the weekend.
_______________________________________________
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To unsubscribe send an email to [e-mail]

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[Tirumalesh]

Hi Mariusz,

Thank you!, that helped.

Thanks,
Tirumalesh.

‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐
On Friday, February 5, 2021 3:01 PM, Szafranski, MariuszX  wrote:
> Hi Tirumalesh,
>
> Please verify if FSP is correctly integrated. Especially if FSP-T part is enabled and used for setting up CAR.
>
> config mainboard section:
>
> vendor->Intel,
>
> model->Harcuvar,
>
> romsize ->16M, (insert your actual SPI flash size)
>
> cbfs size 8M (0x800000) (or adjust for your needs)
>
> config chipset:
>
> check Enable High-speed UART debug port selected by UART_FOR_CONSOLE (enable for non legacy UART mode, disable for legacy)
>
> cache as ram implementation -> Use FSP CAR
>
> UART mode – leave at default non legacy mode (or enable if needed – adjust other settings for legacy mode)
>
> Verify if generate from tree is selected for microcode (Include CPU microcode in CBFS (Generate from tree))
>
> config generic drivers:
>
> UART's PCI bus, device, function address - 0x8000d000
>
> Verify if “serial port” on superior is unchecked (need to be when using UART in legacy mode)
>
> config console:
>
> verify if two first options (bootblock console and postcar console) are enabled
>
> As I remember there are two serial port connectors – check if you are using correct one (try both)
>
> BR,
>
> Mariusz
>
> From: Tirumalesh 
> Sent: Friday, February 5, 2021 8:54 AM
> To: Javier Galindo ; [e-mail]
> Subject: [coreboot] Re: coreboot image forIntel Harcuvar CRB
>
> It seems the FSP binaries are auto included, and the configs seems to be of no effect.
>
> Is it not right?
>
> If so I will try to add binaries and microcode header file.
>
> Thanks,
>
> Tirumalesh
>
> On Fri, Feb 5, 2021 at 11:22 AM, Javier Galindo  wrote:
> > Did you set the following in your config file --> CONFIG_LEGACY_UART_MODE=y
> >
> > Also have you setup all the proper fsp/ucode binaries that are commented out in the config file (just did a quick review):
> >
> > #Sample settings for Denverton-NS FSP.
> > #CONFIG_ADD_FSP_BINARIES=y
> > #CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
> > #CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
> > #CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
> > #CONFIG_FSP_CAR=y
> >
> > #Sample settings for microcode definitions.
> > #CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
> > #CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y
> >
> > Unfortunately all my harcuvar work has also been on a fairly old tree of coreboot.
> >
> > I'll give it a try on my Harcuvar if you don't make any progress, but it won't be until the weekend.
> > _______________________________________________
> > coreboot mailing list -- [e-mail]
> > To unsubscribe send an email to [e-mail]
>
> Intel Research and Development Ireland Limited
> Registered in Ireland
> Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
> Registered Number: 308263
>
> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.