Hi Libgfxinit folks,
I am using Libgfxinit built for Skylake platform to enable early graphics from within a baremetal application. The platform connects to an LCD via HDMI. Enabling debug log in Libgfxinit, I get the following from which it seems that the initialization completed successfully but the LCD remains powered off (orange light). Is there anything outside of this mode set sequence that I need to do to enable the display?
[106.904524] HW.GFX.GMA.Initialize [106.907477] HW.GFX.GMA.Panel.Setup_PP_Sequencer [106.911825] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS [106.919119] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS [106.926500] HW.GFX.GMA.Registers.Read: 0x0004af00 <- 0x000c7210:PCH_PP_DIVISOR [106.933613] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS [106.939872] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS [106.947159] HW.GFX.GMA.Registers.Write: 0x08340001 -> 0x000c7208:PCH_PP_ON_DELAYS [106.954454] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS [106.960798] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS [106.968173] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS [106.975554] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_DIVISOR [106.981639] HW.GFX.GMA.Registers.Read: 0x0004af00 <- 0x000c7210:PCH_PP_DIVISOR [106.988754] HW.GFX.GMA.Registers.Write: 0x0004af07 -> 0x000c7210:PCH_PP_DIVISOR [106.995874] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL [107.002307] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7204:PCH_PP_CONTROL [107.009420] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL [107.016542] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [107.021925] HW.GFX.GMA.Registers.Read: 0x00000081 <- 0x00064000:DDI_BUF_CTL_A [107.028959] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [107.034870] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL [107.041810] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL [107.048757] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [107.053973] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP [107.060828] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [107.066738] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL [107.073678] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL [107.080626] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [107.085842] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP [107.092696] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL [107.098606] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL [107.105547] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL [107.112495] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP [107.117710] HW.GFX.GMA.Registers.Read: 0x00000006 <- 0x000c2014:SFUSE_STRAP [107.124563] HW.GFX.GMA.Registers.Unset_Mask: 0x03130303 !S SHOTPLUG_CTL [107.130995] HW.GFX.GMA.Registers.Read: 0x10001010 <- 0x000c4030:SHOTPLUG_CTL [107.137936] HW.GFX.GMA.Registers.Write: 0x10001010 -> 0x000c4030:SHOTPLUG_CTL [107.144883] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e00:DDI_BUF_TRANS_A_S0T1 [107.152525] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2 [107.160166] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1 [107.167808] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2 [107.175450] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1 [107.183090] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e14:DDI_BUF_TRANS_A_S2T2 [107.190733] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1 [107.198373] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2 [107.206015] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e20:DDI_BUF_TRANS_A_S4T1 [107.213657] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e24:DDI_BUF_TRANS_A_S4T2 [107.221299] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1 [107.228940] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2 [107.236582] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1 [107.244222] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2 [107.251864] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1 [107.259505] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2 [107.267146] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1 [107.274788] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2 [107.282431] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1 [107.290072] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2 [107.297714] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e60:DDI_BUF_TRANS_B_S0T1 [107.305355] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2 [107.312996] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1 [107.320637] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2 [107.328280] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1 [107.335920] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e74:DDI_BUF_TRANS_B_S2T2 [107.343562] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1 [107.351204] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2 [107.358845] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e80:DDI_BUF_TRANS_B_S4T1 [107.366487] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064e84:DDI_BUF_TRANS_B_S4T2 [107.374129] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1 [107.381770] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2 [107.389410] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1 [107.397054] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2 [107.404694] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1 [107.412336] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2 [107.419978] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1 [107.427618] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2 [107.435260] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1 [107.442902] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2 [107.450542] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1 [107.458184] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2 [107.465827] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1 [107.473467] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2 [107.481109] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1 [107.488750] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2 [107.496393] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1 [107.504034] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2 [107.511676] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1 [107.519316] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2 [107.526957] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1 [107.534599] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2 [107.542242] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1 [107.549883] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2 [107.557525] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1 [107.565165] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064efc:DDI_BUF_TRANS_C_S7T2 [107.572807] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1 [107.580448] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2 [107.588089] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1 [107.595731] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2 [107.603372] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f20:DDI_BUF_TRANS_D_S0T1 [107.611014] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064f24:DDI_BUF_TRANS_D_S0T2 [107.618655] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f28:DDI_BUF_TRANS_D_S1T1 [107.626297] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f2c:DDI_BUF_TRANS_D_S1T2 [107.633939] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064f30:DDI_BUF_TRANS_D_S2T1 [107.641580] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f34:DDI_BUF_TRANS_D_S2T2 [107.649222] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064f38:DDI_BUF_TRANS_D_S3T1 [107.656863] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f3c:DDI_BUF_TRANS_D_S3T2 [107.664505] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f40:DDI_BUF_TRANS_D_S4T1 [107.672146] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f44:DDI_BUF_TRANS_D_S4T2 [107.679787] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f48:DDI_BUF_TRANS_D_S5T1 [107.687429] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f4c:DDI_BUF_TRANS_D_S5T2 [107.695070] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064f50:DDI_BUF_TRANS_D_S6T1 [107.702713] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f54:DDI_BUF_TRANS_D_S6T2 [107.710355] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f58:DDI_BUF_TRANS_D_S7T1 [107.717995] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064f5c:DDI_BUF_TRANS_D_S7T2 [107.725636] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f60:DDI_BUF_TRANS_D_S8T1 [107.733278] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f64:DDI_BUF_TRANS_D_S8T2 [107.740919] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f68:DDI_BUF_TRANS_D_S9T1 [107.748562] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f6c:DDI_BUF_TRANS_D_S9T2 [107.756203] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064f80:DDI_BUF_TRANS_E_S0T1 [107.763844] HW.GFX.GMA.Registers.Write: 0x000000a0 -> 0x00064f84:DDI_BUF_TRANS_E_S0T2 [107.771486] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064f88:DDI_BUF_TRANS_E_S1T1 [107.779127] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064f8c:DDI_BUF_TRANS_E_S1T2 [107.786769] HW.GFX.GMA.Registers.Write: 0x00007011 -> 0x00064f90:DDI_BUF_TRANS_E_S2T1 [107.794410] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064f94:DDI_BUF_TRANS_E_S2T2 [107.802052] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064f98:DDI_BUF_TRANS_E_S3T1 [107.809692] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f9c:DDI_BUF_TRANS_E_S3T2 [107.817335] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064fa0:DDI_BUF_TRANS_E_S4T1 [107.824977] HW.GFX.GMA.Registers.Write: 0x0000009b -> 0x00064fa4:DDI_BUF_TRANS_E_S4T2 [107.832618] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064fa8:DDI_BUF_TRANS_E_S5T1 [107.840260] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064fac:DDI_BUF_TRANS_E_S5T2 [107.847901] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064fb0:DDI_BUF_TRANS_E_S6T1 [107.855542] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064fb4:DDI_BUF_TRANS_E_S6T2 [107.863183] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064fb8:DDI_BUF_TRANS_E_S7T1 [107.870825] HW.GFX.GMA.Registers.Write: 0x000000df -> 0x00064fbc:DDI_BUF_TRANS_E_S7T2 [107.878466] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064fc0:DDI_BUF_TRANS_E_S8T1 [107.886108] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064fc4:DDI_BUF_TRANS_E_S8T2 [107.893749] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064fc8:DDI_BUF_TRANS_E_S9T1 [107.901392] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064fcc:DDI_BUF_TRANS_E_S9T2 [107.909033] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0 [107.915633] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0 [107.923274] HW.GFX.GMA.Registers.Write: 0x00124900 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0 [107.930915] HW.GFX.GMA.Power_And_Clocks_Haswell.PSR_Off [107.935952] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_EDP [107.941162] HW.GFX.GMA.Registers.Read: 0x00100001 <- 0x0006f800:SRD_CTL_EDP [107.948021] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_A [107.953058] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00060800:SRD_CTL_A [107.959745] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_B [107.964781] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00061800:SRD_CTL_B [107.971468] HW.GFX.GMA.Registers.Is_Set_Mask: SRD_CTL_C [107.976504] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00062800:SRD_CTL_C [107.983190] HW.GFX.GMA.Panel.Backlight_Off [107.987097] HW.GFX.GMA.Registers.Unset_Mask: 0x00000004 !S PCH_PP_CONTROL [107.993703] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL [108.000818] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL [108.007937] HW.GFX.GMA.Panel.Off [108.010978] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL [108.016455] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL [108.023569] HW.GFX.GMA.Registers.Unset_Mask: 0x00000009 !S PCH_PP_CONTROL [108.030174] HW.GFX.GMA.Registers.Read: 0x00000002 <- 0x000c7204:PCH_PP_CONTROL [108.037288] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c7204:PCH_PP_CONTROL [108.044408] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS [108.052577] HW.GFX.GMA.Pipe_Setup.All_Off [108.056493] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL [108.062644] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL [108.069590] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL [108.076537] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [108.083225] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000700a0:CUR_FBC_CTL_A [108.090257] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPACNTR [108.096250] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070280:SPACNTR [108.102762] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070280:SPACNTR [108.109274] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007017c:CUR_BUF_CFG_A [108.116307] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070140:CUR_WM_A_0 [108.123081] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070144:CUR_WM_A_1 [108.129854] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070148:CUR_WM_A_2 [108.136629] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007014c:CUR_WM_A_3 [108.143401] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070150:CUR_WM_A_4 [108.150174] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070154:CUR_WM_A_5 [108.156948] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070158:CUR_WM_A_6 [108.163721] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007015c:CUR_WM_A_7 [108.170493] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007027c:PLANE_BUF_CFG_1_A [108.177875] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070240:PLANE_WM_1_A_0 [108.184994] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070244:PLANE_WM_1_A_1 [108.192114] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070248:PLANE_WM_1_A_2 [108.199236] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007024c:PLANE_WM_1_A_3 [108.206356] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070250:PLANE_WM_1_A_4 [108.213478] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070254:PLANE_WM_1_A_5 [108.220597] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070258:PLANE_WM_1_A_6 [108.227718] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007025c:PLANE_WM_1_A_7 [108.234837] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045270:WM_LINETIME_A [108.241872] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPACNTR [108.247951] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070180:DSPACNTR [108.254549] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070180:DSPACNTR [108.261150] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF [108.267749] HW.GFX.GMA.Registers.Read: 0x00030000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.275478] HW.GFX.GMA.Registers.Is_Set_Mask: PIPE_EDP_CONF [108.280860] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0007f008:PIPE_EDP_CONF [108.287894] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x0007f008:PIPE_EDP_CONF [108.296057] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.303786] HW.GFX.GMA.Registers.Is_Set_Mask: PIPEACONF [108.308822] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00070008:PIPEACONF [108.315508] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00070008:PIPEACONF [108.323323] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00060400:PIPEA_DDI_FUNC_CTL [108.330792] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A [108.337131] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A [108.343990] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A [108.350850] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A [108.357884] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A [108.364222] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A [108.371082] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A [108.377943] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A [108.384976] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046140:TRANSA_CLK_SEL [108.392097] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071080:CUR_CTL_B [108.398783] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000710a0:CUR_FBC_CTL_B [108.405817] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPBCNTR [108.411808] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071280:SPBCNTR [108.418321] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071280:SPBCNTR [108.424833] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007117c:CUR_BUF_CFG_B [108.431867] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071140:CUR_WM_B_0 [108.438640] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071144:CUR_WM_B_1 [108.445414] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071148:CUR_WM_B_2 [108.452187] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007114c:CUR_WM_B_3 [108.458959] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071150:CUR_WM_B_4 [108.465733] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071154:CUR_WM_B_5 [108.472507] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071158:CUR_WM_B_6 [108.479278] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007115c:CUR_WM_B_7 [108.486052] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007127c:PLANE_BUF_CFG_1_B [108.493433] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071240:PLANE_WM_1_B_0 [108.500553] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071244:PLANE_WM_1_B_1 [108.507674] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071248:PLANE_WM_1_B_2 [108.514795] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007124c:PLANE_WM_1_B_3 [108.521915] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071250:PLANE_WM_1_B_4 [108.529035] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071254:PLANE_WM_1_B_5 [108.536156] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071258:PLANE_WM_1_B_6 [108.543276] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007125c:PLANE_WM_1_B_7 [108.550397] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045274:WM_LINETIME_B [108.557432] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPBCNTR [108.563509] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071180:DSPBCNTR [108.570109] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00071180:DSPBCNTR [108.576708] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007119c:DSPBSURF [108.583309] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.591037] HW.GFX.GMA.Registers.Is_Set_Mask: PIPEBCONF [108.596073] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00071008:PIPEBCONF [108.602759] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00071008:PIPEBCONF [108.610574] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00061400:PIPEB_DDI_FUNC_CTL [108.618041] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_B [108.624381] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068980:PS_CTRL_1_B [108.631241] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068980:PS_CTRL_1_B [108.638101] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068974:PS_WIN_SZ_1_B [108.645135] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_B [108.651473] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068a80:PS_CTRL_2_B [108.658334] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068a80:PS_CTRL_2_B [108.665193] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068a74:PS_WIN_SZ_2_B [108.672227] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046144:TRANSB_CLK_SEL [108.679348] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072080:CUR_CTL_C [108.686034] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000720a0:CUR_FBC_CTL_C [108.693067] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S SPCCNTR [108.699059] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072280:SPCCNTR [108.705572] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072280:SPCCNTR [108.712083] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007217c:CUR_BUF_CFG_C [108.719117] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072140:CUR_WM_C_0 [108.725891] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072144:CUR_WM_C_1 [108.732663] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072148:CUR_WM_C_2 [108.739438] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007214c:CUR_WM_C_3 [108.746210] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072150:CUR_WM_C_4 [108.752984] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072154:CUR_WM_C_5 [108.759757] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072158:CUR_WM_C_6 [108.766530] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007215c:CUR_WM_C_7 [108.773302] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007227c:PLANE_BUF_CFG_1_C [108.780685] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072240:PLANE_WM_1_C_0 [108.787804] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072244:PLANE_WM_1_C_1 [108.794924] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072248:PLANE_WM_1_C_2 [108.802045] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007224c:PLANE_WM_1_C_3 [108.809167] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072250:PLANE_WM_1_C_4 [108.816286] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072254:PLANE_WM_1_C_5 [108.823407] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072258:PLANE_WM_1_C_6 [108.830528] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007225c:PLANE_WM_1_C_7 [108.837647] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00045278:WM_LINETIME_C [108.844681] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DSPCCNTR [108.850759] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072180:DSPCCNTR [108.857359] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00072180:DSPCCNTR [108.863958] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007219c:DSPCSURF [108.870559] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006f400:PIPE_EDP_DDI_FUNC_CTL [108.878288] HW.GFX.GMA.Registers.Is_Set_Mask: PIPECCONF [108.883323] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00072008:PIPECCONF [108.890010] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00072008:PIPECCONF [108.897825] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00062400:PIPEC_DDI_FUNC_CTL [108.905292] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_C [108.911631] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00069180:PS_CTRL_1_C [108.918492] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00069180:PS_CTRL_1_C [108.925351] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00069174:PS_WIN_SZ_1_C [108.932385] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046148:TRANSC_CLK_SEL [108.939505] HW.GFX.GMA.Connectors.DDI.Off [108.943327] HW.GFX.GMA.Connectors.DDI.Digital_Off [108.947842] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A [108.953225] HW.GFX.GMA.Registers.Read: 0x00000081 <- 0x00064000:DDI_BUF_CTL_A [108.960260] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_A [108.966598] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064040:DP_TP_CTL_A [108.973457] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064040:DP_TP_CTL_A [108.980319] HW.GFX.GMA.Registers.Set_Mask: 0x00008000 .S DPLL_CTRL2 [108.986396] HW.GFX.GMA.Registers.Read: 0x00a10018 <- 0x0006c05c:DPLL_CTRL2 [108.993169] HW.GFX.GMA.Registers.Write: 0x00a18018 -> 0x0006c05c:DPLL_CTRL2 [108.999943] HW.GFX.GMA.Connectors.DDI.Off [109.003763] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.008279] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_B [109.013663] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064100:DDI_BUF_CTL_B [109.020696] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_B [109.027036] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064140:DP_TP_CTL_B [109.033894] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064140:DP_TP_CTL_B [109.040754] HW.GFX.GMA.Registers.Set_Mask: 0x00010000 .S DPLL_CTRL2 [109.046834] HW.GFX.GMA.Registers.Read: 0x00a18018 <- 0x0006c05c:DPLL_CTRL2 [109.053608] HW.GFX.GMA.Registers.Write: 0x00a18018 -> 0x0006c05c:DPLL_CTRL2 [109.060380] HW.GFX.GMA.Connectors.DDI.Off [109.064200] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.068716] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_C [109.074099] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064200:DDI_BUF_CTL_C [109.081134] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_C [109.087472] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064240:DP_TP_CTL_C [109.094333] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064240:DP_TP_CTL_C [109.101192] HW.GFX.GMA.Registers.Set_Mask: 0x00020000 .S DPLL_CTRL2 [109.107271] HW.GFX.GMA.Registers.Read: 0x00a18018 <- 0x0006c05c:DPLL_CTRL2 [109.114045] HW.GFX.GMA.Registers.Write: 0x00a38018 -> 0x0006c05c:DPLL_CTRL2 [109.120816] HW.GFX.GMA.Connectors.DDI.Off [109.124639] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.129154] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_D [109.134537] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064300:DDI_BUF_CTL_D [109.141570] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_D [109.147911] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064340:DP_TP_CTL_D [109.154770] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064340:DP_TP_CTL_D [109.161630] HW.GFX.GMA.Registers.Set_Mask: 0x00040000 .S DPLL_CTRL2 [109.167708] HW.GFX.GMA.Registers.Read: 0x00a38018 <- 0x0006c05c:DPLL_CTRL2 [109.174481] HW.GFX.GMA.Registers.Write: 0x00a78018 -> 0x0006c05c:DPLL_CTRL2 [109.181255] HW.GFX.GMA.Connectors.DDI.Off [109.185075] HW.GFX.GMA.Connectors.DDI.Digital_Off [109.189590] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_E [109.194975] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064400:DDI_BUF_CTL_E [109.202008] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DP_TP_CTL_E [109.208346] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064440:DP_TP_CTL_E [109.215206] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064440:DP_TP_CTL_E [109.222066] HW.GFX.GMA.Registers.Set_Mask: 0x00080000 .S DPLL_CTRL2 [109.228145] HW.GFX.GMA.Registers.Read: 0x00a78018 <- 0x0006c05c:DPLL_CTRL2 [109.234919] HW.GFX.GMA.Registers.Write: 0x00af8018 -> 0x0006c05c:DPLL_CTRL2 [109.241691] HW.GFX.GMA.PLLs.All_Off [109.244992] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL2_CTL [109.251244] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00046014:LCPLL2_CTL [109.258016] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00046014:LCPLL2_CTL [109.264791] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S WRPLL_CTL_2 [109.271129] HW.GFX.GMA.Registers.Read: 0x00202418 <- 0x00046060:WRPLL_CTL_2 [109.277988] HW.GFX.GMA.Registers.Write: 0x00202418 -> 0x00046060:WRPLL_CTL_2 [109.284848] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S WRPLL_CTL_1 [109.291187] HW.GFX.GMA.Registers.Read: 0x00202418 <- 0x00046040:WRPLL_CTL_1 [109.298049] HW.GFX.GMA.Registers.Write: 0x00202418 -> 0x00046040:WRPLL_CTL_1 [109.304908] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.310031] PD is 3 [109.311942] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.319323] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.326876] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.334259] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.341725] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.348759] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.355793] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.360917] PD is 4 [109.362826] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.370208] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.377763] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.385143] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.392611] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.399646] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.406679] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.411802] PD is 5 [109.413713] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.421094] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.428648] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.436029] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.443497] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.450530] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.457564] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.462687] PD is 6 [109.464598] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.471978] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.479534] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.486914] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.494381] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.501416] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.508449] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.513573] PD is 2 [109.515484] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.522864] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.530418] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.537801] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.545268] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.552301] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.559335] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S DBUF_CTL [109.565413] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL [109.572012] HW.GFX.GMA.Registers.Write: 0x0000000a -> 0x00045008:DBUF_CTL [109.578612] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045008:DBUF_CTL [109.586340] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S LCPLL1_CTL [109.592592] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL [109.599366] HW.GFX.GMA.Registers.Write: 0x40000000 -> 0x00046010:LCPLL1_CTL [109.606140] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL [109.614041] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.619165] PD is 2 [109.621076] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.628457] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.636011] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.643392] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.650859] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.657894] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.664926] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404: [109.673611] HW.GFX.GMA.Registers.Unset_Mask: 0x00000002 !S PWR_WELL_CTL_BIOS [109.680470] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [109.687851] HW.GFX.GMA.Registers.Write: 0x30000001 -> 0x00045400:PWR_WELL_CTL_BIOS [109.695232] HW.GFX.GMA.Registers.Unset_Mask: 0x00000002 !S PWR_WELL_CTL_DRIVER [109.702266] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.709821] HW.GFX.GMA.Registers.Write: 0x30000003 -> 0x00045404:PWR_WELL_CTL_DRIVER [109.717376] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_Off
[109.722499] PD is 2 [109.724410] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.731790] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.739344] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.746726] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.754194] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.761228] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.768260] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404: [109.776944] HW.GFX.GMA.Registers.Unset_Mask: 0x20000000 !S PWR_WELL_CTL_BIOS [109.783804] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.791184] HW.GFX.GMA.Registers.Write: 0x10000001 -> 0x00045400:PWR_WELL_CTL_BIOS [109.798566] HW.GFX.GMA.Registers.Unset_Mask: 0x20000000 !S PWR_WELL_CTL_DRIVER [109.805600] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.813155] HW.GFX.GMA.Registers.Write: 0x10000003 -> 0x00045404:PWR_WELL_CTL_DRIVER [109.820713] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT [109.827135] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT [109.834255] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT [109.841376] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS [109.849364] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[109.854401] PD is 2 [109.856311] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.863692] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.871248] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.878629] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.886097] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.893131] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.900163] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_BIOS [109.906849] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.914230] HW.GFX.GMA.Registers.Write: 0x30000001 -> 0x00045400:PWR_WELL_CTL_BIOS [109.921610] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045400:PWR_WELL_CTL_BIOS [109.930122] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS [109.938110] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[109.943146] PD is 2 [109.945057] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [109.952439] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [109.959994] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [109.967375] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [109.974841] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [109.981876] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [109.988908] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_BIOS [109.995596] HW.GFX.GMA.Registers.Read: 0x30000001 <- 0x00045400:PWR_WELL_CTL_BIOS [110.002977] HW.GFX.GMA.Registers.Write: 0x30000003 -> 0x00045400:PWR_WELL_CTL_BIOS [110.010357] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045400:PWR_WELL_CTL_BIOS [110.018867] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL [110.025552] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1 [110.031283] HW.GFX.GMA.Registers.Read: 0x00000845 <- 0x0006c058:DPLL_CTRL1 [110.038057] HW.GFX.GMA.Registers.Write: 0x00000847 -> 0x0006c058:DPLL_CTRL1 [110.044830] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL [110.050909] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00046010:LCPLL1_CTL [110.057682] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046010:LCPLL1_CTL [110.064455] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL [110.072357] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write [110.078175] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.086076] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA [110.093285] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [110.100665] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX [110.107439] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.115342] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA [110.122547] HW.GFX.GMA.Power_And_Clocks_Skylake.GT_Mailbox_Write [110.128365] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.136268] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA [110.143475] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1 [110.150856] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX [110.157629] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX [110.165532] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL [110.171436] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL [110.178035] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL [110.184634] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL [110.192363] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ [110.198535] HW.GFX.GMA.Registers.Read: 0x00000018 <- 0x000c6204:PCH_RAWCLK_FREQ [110.205735] HW.GFX.GMA.Registers.Write: 0x00000018 -> 0x000c6204:PCH_RAWCLK_FREQ [110.212949] HW.GFX.GMA.Display_Probing.Read_EDID [110.217372] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[110.222408] PD is 2 [110.224319] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.231699] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.239253] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.246636] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.254104] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.261137] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.268170] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x40000000 & 0x00045404: [110.276854] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_BIOS [110.283540] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.290920] HW.GFX.GMA.Registers.Write: 0xb0000003 -> 0x00045400:PWR_WELL_CTL_BIOS [110.298302] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045400:PWR_WELL_CTL_BIOS [110.306811] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [110.314802] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [110.321661] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.329215] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.336769] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [110.345453] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [110.353444] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[110.358478] PD is 5 [110.360389] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.367771] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.375325] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.382705] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.390174] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.397207] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.404242] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404: [110.412924] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_BIOS [110.419611] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS [110.426991] HW.GFX.GMA.Registers.Write: 0xf0000023 -> 0x00045400:PWR_WELL_CTL_BIOS [110.434374] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045400:PWR_WELL_CTL_BIOS [110.442882] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER [110.449744] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.457298] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.464851] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404: [110.473535] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [110.478919] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B [110.485952] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [110.493247] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [110.499238] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B [110.506271] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [110.513305] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [110.521470] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.528503] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [110.533886] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.540919] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [110.548213] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [110.554206] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.561238] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [110.568273] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [110.576436] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.583469] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [110.588852] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.595886] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [110.603180] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [110.609172] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.616205] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [110.623240] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [110.631403] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [110.638436] HW.GFX.GMA.Display_Probing.Read_EDID [110.642864] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[110.647900] PD is 2 [110.649810] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045400:PWR_WELL_CTL_BIOS [110.657192] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.664747] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.672128] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.679595] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.686629] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.693662] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [110.700522] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.708077] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.715631] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [110.724316] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [110.732305] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[110.737341] PD is 4 [110.739251] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045400:PWR_WELL_CTL_BIOS [110.746633] HW.GFX.GMA.Registers.Read: 0x70000013 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.754186] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [110.761567] HW.GFX.GMA.Registers.Read: 0x50000011 <- 0x0004540c:PWR_WELL_CTL_DEBUG [110.769036] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [110.776069] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [110.783103] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404: [110.791785] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_BIOS [110.798472] HW.GFX.GMA.Registers.Read: 0xf0000033 <- 0x00045400:PWR_WELL_CTL_BIOS [110.805854] HW.GFX.GMA.Registers.Write: 0xf00000b3 -> 0x00045400:PWR_WELL_CTL_BIOS [110.813235] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045400:PWR_WELL_CTL_BIOS [110.821744] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER [110.828605] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [110.836158] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [110.843713] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404: [110.852398] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C [110.857781] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C [110.864814] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 [110.872108] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C [110.878100] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C [110.885134] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C [110.892168] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C [110.900331] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.907363] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C [110.912747] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.919781] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 [110.927075] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C [110.933067] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.940101] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C [110.947134] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C [110.955297] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.962331] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C [110.967715] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.974748] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1 [110.982042] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C [110.988033] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [110.995068] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C [111.002101] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C [111.010264] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C [111.017297] HW.GFX.GMA.Display_Probing.Read_EDID [111.021726] HW.GFX.GMA.I2C.I2C_Read [111.025026] HW.GFX.GMA.I2C.Init_GMBUS [111.028499] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D [111.035192] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [111.042567] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [111.049946] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 [111.057863] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 [111.064622] HW.GFX.GMA.Registers.Write: 0x00000005 -> 0x000c5100:PCH_GMBUS0 [111.071395] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 [111.078169] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 [111.084941] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 [111.091714] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.099630] HW.GFX.GMA.Registers.Read: 0x00008a08 <- 0x000c5108:PCH_GMBUS2 [111.106397] HW.GFX.GMA.Registers.Read: 0xffffff00 <- 0x000c510c:PCH_GMBUS3 [111.113163] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.121080] HW.GFX.GMA.Registers.Read: 0x00008a0c <- 0x000c5108:PCH_GMBUS2 [111.127844] HW.GFX.GMA.Registers.Read: 0x00ffffff <- 0x000c510c:PCH_GMBUS3 [111.134611] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.142527] HW.GFX.GMA.Registers.Read: 0x00008a10 <- 0x000c5108:PCH_GMBUS2 [111.149292] HW.GFX.GMA.Registers.Read: 0x4042ac10 <- 0x000c510c:PCH_GMBUS3 [111.156059] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.163976] HW.GFX.GMA.Registers.Read: 0x00008a14 <- 0x000c5108:PCH_GMBUS2 [111.170741] HW.GFX.GMA.Registers.Read: 0x3138364c <- 0x000c510c:PCH_GMBUS3 [111.177508] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.185423] HW.GFX.GMA.Registers.Read: 0x00008a18 <- 0x000c5108:PCH_GMBUS2 [111.192189] HW.GFX.GMA.Registers.Read: 0x03011322 <- 0x000c510c:PCH_GMBUS3 [111.198956] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.206872] HW.GFX.GMA.Registers.Read: 0x00008a1c <- 0x000c5108:PCH_GMBUS2 [111.213638] HW.GFX.GMA.Registers.Read: 0x781b2b80 <- 0x000c510c:PCH_GMBUS3 [111.220404] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.228321] HW.GFX.GMA.Registers.Read: 0x00008a20 <- 0x000c5108:PCH_GMBUS2 [111.235086] HW.GFX.GMA.Registers.Read: 0xa705b72e <- 0x000c510c:PCH_GMBUS3 [111.241853] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.249769] HW.GFX.GMA.Registers.Read: 0x00008a24 <- 0x000c5108:PCH_GMBUS2 [111.256535] HW.GFX.GMA.Registers.Read: 0x26ad3854 <- 0x000c510c:PCH_GMBUS3 [111.263301] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.271218] HW.GFX.GMA.Registers.Read: 0x00008a28 <- 0x000c5108:PCH_GMBUS2 [111.277983] HW.GFX.GMA.Registers.Read: 0xbf54500e <- 0x000c510c:PCH_GMBUS3 [111.284749] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.292665] HW.GFX.GMA.Registers.Read: 0x00008a2c <- 0x000c5108:PCH_GMBUS2 [111.299431] HW.GFX.GMA.Registers.Read: 0x4f7180ef <- 0x000c510c:PCH_GMBUS3 [111.306197] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.314114] HW.GFX.GMA.Registers.Read: 0x00008a30 <- 0x000c5108:PCH_GMBUS2 [111.320880] HW.GFX.GMA.Registers.Read: 0x00b38081 <- 0x000c510c:PCH_GMBUS3 [111.327647] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.335561] HW.GFX.GMA.Registers.Read: 0x00008a34 <- 0x000c5108:PCH_GMBUS2 [111.342327] HW.GFX.GMA.Registers.Read: 0xc0810095 <- 0x000c510c:PCH_GMBUS3 [111.349095] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.357009] HW.GFX.GMA.Registers.Read: 0x00008a38 <- 0x000c5108:PCH_GMBUS2 [111.363775] HW.GFX.GMA.Registers.Read: 0x01010081 <- 0x000c510c:PCH_GMBUS3 [111.370542] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.378458] HW.GFX.GMA.Registers.Read: 0x00008a3c <- 0x000c5108:PCH_GMBUS2 [111.385224] HW.GFX.GMA.Registers.Read: 0x39210101 <- 0x000c510c:PCH_GMBUS3 [111.391991] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.399906] HW.GFX.GMA.Registers.Read: 0x00008a40 <- 0x000c5108:PCH_GMBUS2 [111.406672] HW.GFX.GMA.Registers.Read: 0x1a623090 <- 0x000c510c:PCH_GMBUS3 [111.413439] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.421354] HW.GFX.GMA.Registers.Read: 0x00008a44 <- 0x000c5108:PCH_GMBUS2 [111.428120] HW.GFX.GMA.Registers.Read: 0xb0684027 <- 0x000c510c:PCH_GMBUS3 [111.434888] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.442804] HW.GFX.GMA.Registers.Read: 0x00008a48 <- 0x000c5108:PCH_GMBUS2 [111.449568] HW.GFX.GMA.Registers.Read: 0x0fb10036 <- 0x000c510c:PCH_GMBUS3 [111.456335] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.464251] HW.GFX.GMA.Registers.Read: 0x00008a4c <- 0x000c5108:PCH_GMBUS2 [111.471018] HW.GFX.GMA.Registers.Read: 0x1c000011 <- 0x000c510c:PCH_GMBUS3 [111.477784] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.485700] HW.GFX.GMA.Registers.Read: 0x00008a50 <- 0x000c5108:PCH_GMBUS2 [111.492464] HW.GFX.GMA.Registers.Read: 0xff000000 <- 0x000c510c:PCH_GMBUS3 [111.499233] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.507148] HW.GFX.GMA.Registers.Read: 0x00008a54 <- 0x000c5108:PCH_GMBUS2 [111.513913] HW.GFX.GMA.Registers.Read: 0x35344700 <- 0x000c510c:PCH_GMBUS3 [111.520680] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.528596] HW.GFX.GMA.Registers.Read: 0x00008a58 <- 0x000c5108:PCH_GMBUS2 [111.535362] HW.GFX.GMA.Registers.Read: 0x38394833 <- 0x000c510c:PCH_GMBUS3 [111.542130] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.550045] HW.GFX.GMA.Registers.Read: 0x00008a5c <- 0x000c5108:PCH_GMBUS2 [111.556809] HW.GFX.GMA.Registers.Read: 0x3638314b <- 0x000c510c:PCH_GMBUS3 [111.563577] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.571493] HW.GFX.GMA.Registers.Read: 0x00008a60 <- 0x000c5108:PCH_GMBUS2 [111.578257] HW.GFX.GMA.Registers.Read: 0x00000a4c <- 0x000c510c:PCH_GMBUS3 [111.585025] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.592941] HW.GFX.GMA.Registers.Read: 0x00008a64 <- 0x000c5108:PCH_GMBUS2 [111.599707] HW.GFX.GMA.Registers.Read: 0x4400fc00 <- 0x000c510c:PCH_GMBUS3 [111.606475] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.614389] HW.GFX.GMA.Registers.Read: 0x00008a68 <- 0x000c5108:PCH_GMBUS2 [111.621154] HW.GFX.GMA.Registers.Read: 0x204c4c45 <- 0x000c510c:PCH_GMBUS3 [111.627921] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.635839] HW.GFX.GMA.Registers.Read: 0x00008a6c <- 0x000c5108:PCH_GMBUS2 [111.642603] HW.GFX.GMA.Registers.Read: 0x39303032 <- 0x000c510c:PCH_GMBUS3 [111.649369] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.657285] HW.GFX.GMA.Registers.Read: 0x00008a70 <- 0x000c5108:PCH_GMBUS2 [111.664052] HW.GFX.GMA.Registers.Read: 0x20200a57 <- 0x000c510c:PCH_GMBUS3 [111.670818] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.678734] HW.GFX.GMA.Registers.Read: 0x00008a74 <- 0x000c5108:PCH_GMBUS2 [111.685501] HW.GFX.GMA.Registers.Read: 0xfd000000 <- 0x000c510c:PCH_GMBUS3 [111.692267] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.700183] HW.GFX.GMA.Registers.Read: 0x00008a78 <- 0x000c5108:PCH_GMBUS2 [111.706949] HW.GFX.GMA.Registers.Read: 0x1e4b3800 <- 0x000c510c:PCH_GMBUS3 [111.713715] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.721631] HW.GFX.GMA.Registers.Read: 0x00008a7c <- 0x000c5108:PCH_GMBUS2 [111.728395] HW.GFX.GMA.Registers.Read: 0x0a001053 <- 0x000c510c:PCH_GMBUS3 [111.735163] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.743079] HW.GFX.GMA.Registers.Read: 0x0000ca00 <- 0x000c5108:PCH_GMBUS2 [111.749844] HW.GFX.GMA.Registers.Read: 0x20202020 <- 0x000c510c:PCH_GMBUS3 [111.756611] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [111.764527] HW.GFX.GMA.Registers.Read: 0x0000ca00 <- 0x000c5108:PCH_GMBUS2 [111.771293] HW.GFX.GMA.Registers.Read: 0x40002020 <- 0x000c510c:PCH_GMBUS3 [111.778060] HW.GFX.GMA.Registers.Wait: 0x00004000 <- 0x00004000 & 0x000c5108:PCH_GMBUS2 [111.785968] HW.GFX.GMA.Registers.Write: 0x48000000 -> 0x000c5104:PCH_GMBUS1 [111.792735] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2 [111.800644] HW.GFX.GMA.I2C.Release_GMBUS [111.804371] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 [111.811143] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 [111.817916] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D [111.824783] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [111.832158] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [111.839539] EDID+0x0000: 00 ff ff ff ff ff ff 00 10 ac 42 40 4c 36 38 31 [111.846312] EDID+0x0010: 22 13 01 03 80 2b 1b 78 2e b7 05 a7 54 38 ad 26 [111.853084] EDID+0x0020: 0e 50 54 bf ef 80 71 4f 81 80 b3 00 95 00 81 c0 [111.859859] EDID+0x0030: 81 00 01 01 01 01 21 39 90 30 62 1a 27 40 68 b0 [111.866632] EDID+0x0040: 36 00 b1 0f 11 00 00 1c 00 00 00 ff 00 47 34 35 [111.873406] EDID+0x0050: 33 48 39 38 4b 31 38 36 4c 0a 00 00 00 fc 00 44 [111.880179] EDID+0x0060: 45 4c 4c 20 32 30 30 39 57 0a 20 20 00 00 00 fd [111.886950] EDID+0x0070: 00 38 4b 1e 53 10 00 0a 20 20 20 20 20 20 00 40 [111.893724] HW.GFX.GMA.Display_Probing.Read_EDID [111.898153] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[111.903189] PD is 2 [111.905100] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [111.912481] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [111.920035] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [111.927416] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [111.934885] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [111.941918] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [111.948951] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [111.955812] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [111.963366] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [111.970921] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [111.979604] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [111.987593] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[111.992630] PD is 5 [111.994541] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [112.001922] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [112.009475] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [112.016856] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [112.024325] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [112.031358] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [112.038392] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER [112.045252] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [112.052806] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [112.060362] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404: [112.069044] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [112.074429] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.081461] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [112.088757] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [112.094747] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.101780] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [112.108816] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [112.116977] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.124010] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [112.129395] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.136429] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [112.143723] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [112.149713] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.156748] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [112.163781] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [112.171944] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.178978] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B [112.184361] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.191396] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1 [112.198690] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B [112.204681] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.211714] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B [112.218748] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B [112.226912] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B [112.233945] HW.GFX.GMA.Display_Probing.Read_EDID [112.238374] HW.GFX.GMA.I2C.I2C_Read [112.241673] HW.GFX.GMA.I2C.Init_GMBUS [112.245146] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D [112.251838] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [112.259213] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D [112.266594] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2 [112.274511] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2 [112.281270] HW.GFX.GMA.Registers.Write: 0x00000004 -> 0x000c5100:PCH_GMBUS0 [112.288042] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4 [112.294816] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5 [112.301589] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1 [112.308363] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2 [112.316278] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2 [112.323037] HW.GFX.GMA.I2C.Release_GMBUS [112.326771] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0 [112.333545] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2 [112.340317] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D [112.347184] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D [112.354558] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
[112.362113] CONFIG => [112.364198] (Primary => [112.366803] (Port => HDMI1 , [112.370102] Framebuffer => [112.373140] (Width => 1680, [112.376788] Height => 1050, [112.380436] Start_X => 0, [112.383821] Start_Y => 0, [112.387209] Stride => 1680, [112.390856] V_Stride => 1050, [112.394502] Tiling => Linear , [112.398409] Rotation => No_Rotation, [112.402664] Offset => 0x00000000, [112.406574] BPC => 8), [112.409785] Mode => [112.412217] (Dotclock => 146250000, [112.417079] H_Visible => 1680, [112.421509] H_Sync_Begin => 1784, [112.425937] H_Sync_End => 1960, [112.430365] H_Total => 2240, [112.434793] V_Visible => 1050, [112.439223] V_Sync_Begin => 1053, [112.443651] V_Sync_End => 1059, [112.448080] V_Total => 1089, [112.452509] H_Sync_Active_High => False, [112.457023] V_Sync_Active_High => True, [112.461452] BPC => 5)), [112.465795] Secondary => [112.468400] (Port => Disabled, [112.471700] Framebuffer => [112.474739] (Width => 1, [112.478124] Height => 1, [112.481511] Start_X => 0, [112.484897] Start_Y => 0, [112.488285] Stride => 1, [112.491672] V_Stride => 1, [112.495058] Tiling => Linear , [112.498965] Rotation => No_Rotation, [112.503220] Offset => 0x00000000, [112.507128] BPC => 8), [112.510341] Mode => [112.512773] (Dotclock => 19200000, [112.517549] H_Visible => 1, [112.521715] H_Sync_Begin => 1, [112.525885] H_Sync_End => 1, [112.530052] H_Total => 1, [112.534220] V_Visible => 1, [112.538388] V_Sync_Begin => 1, [112.542556] V_Sync_End => 1, [112.546724] V_Total => 1, [112.550892] H_Sync_Active_High => False, [112.555408] V_Sync_Active_High => False, [112.559923] BPC => 5)), [112.564266] Tertiary => [112.566869] (Port => Disabled, [112.570170] Framebuffer => [112.573209] (Width => 1, [112.576595] Height => 1, [112.579982] Start_X => 0, [112.583369] Start_Y => 0, [112.586755] Stride => 1, [112.590141] V_Stride => 1, [112.593529] Tiling => Linear , [112.597437] Rotation => No_Rotation, [112.601691] Offset => 0x00000000, [112.605600] BPC => 8), [112.608811] Mode => [112.611244] (Dotclock => 19200000, [112.616019] H_Visible => 1, [112.620186] H_Sync_Begin => 1, [112.624354] H_Sync_End => 1, [112.628522] H_Total => 1, [112.632691] V_Visible => 1, [112.636860] V_Sync_Begin => 1, [112.641028] V_Sync_End => 1, [112.645196] V_Total => 1, [112.649365] H_Sync_Active_High => False, [112.653879] V_Sync_Active_High => False, [112.658395] BPC => 5)));
[113.471029] Success
[113.473113] Update_Power [113.475456] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[113.480494] PD is 2 [113.482403] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [113.489785] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.497339] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [113.504721] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [113.512188] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [113.519221] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [113.526255] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER [113.533116] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.540671] HW.GFX.GMA.Registers.Write: 0xf0005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [113.548226] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404: [113.556908] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS [113.564898] HW.GFX.GMA.Power_And_Clocks_Skylake.PD_On
[113.569933] PD is 5 [113.571844] HW.GFX.GMA.Registers.Read: 0xf00000f3 <- 0x00045400:PWR_WELL_CTL_BIOS [113.579225] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.586779] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR [113.594161] HW.GFX.GMA.Registers.Read: 0x50000051 <- 0x0004540c:PWR_WELL_CTL_DEBUG [113.601629] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5 [113.608663] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6 [113.615696] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER [113.622556] HW.GFX.GMA.Registers.Read: 0x70000053 <- 0x00045404:PWR_WELL_CTL_DRIVER [113.630111] HW.GFX.GMA.Registers.Write: 0x70005257 -> 0x00045404:PWR_WELL_CTL_DRIVER [113.637664] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:
[113.646522] Trying to enable port HDMI1
[113.650604] Enable_Output [113.653035] Success - Fill_Port_Config [113.656595] Success - Validate_Config [113.660069] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting [113.665538] HW.GFX.GMA.PLLs.Alloc [113.668666] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1 [113.674395] HW.GFX.GMA.Registers.Read: 0x00000847 <- 0x0006c058:DPLL_CTRL1 [113.681169] HW.GFX.GMA.Registers.Write: 0x00000847 -> 0x0006c058:DPLL_CTRL1 [113.687942] HW.GFX.GMA.Registers.Write: 0x80a0016d -> 0x0006c040:DPLL1_CFGR1 [113.694803] HW.GFX.GMA.Registers.Write: 0x000003a5 -> 0x0006c044:DPLL1_CFGR2 [113.701662] HW.GFX.GMA.Registers.Read: 0x00000847 <- 0x0006c058:DPLL_CTRL1 [113.708436] HW.GFX.GMA.Registers.Read: 0x80a0016d <- 0x0006c040:DPLL1_CFGR1 [113.715295] HW.GFX.GMA.Registers.Read: 0x000003a5 <- 0x0006c044:DPLL1_CFGR2 [113.722156] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL [113.728930] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS [113.736918] Success - PLLs Alloc [113.739963] HW.GFX.GMA.Connectors.Pre_On [113.743691] HW.GFX.GMA.Connectors.DDI.Pre_On [113.747773] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2 [113.753503] HW.GFX.GMA.Registers.Read: 0x00af8018 <- 0x0006c05c:DPLL_CTRL2 [113.760277] HW.GFX.GMA.Registers.Write: 0x00ae8018 -> 0x0006c05c:DPLL_CTRL2 [113.767050] Success - Connectors Pre_On [113.770697] HW.GFX.GMA.Pipe_Setup.On [113.774083] HW.GFX.GMA.Transcoder.Setup [113.777731] HW.GFX.GMA.Registers.Write: 0x40000000 -> 0x00046140:TRANSA_CLK_SEL [113.784851] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x00060000:HTOTAL_A [113.791449] HW.GFX.GMA.Registers.Write: 0x08bf068f -> 0x00060004:HBLANK_A [113.798049] HW.GFX.GMA.Registers.Write: 0x07a706f7 -> 0x00060008:HSYNC_A [113.804562] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x0006000c:VTOTAL_A [113.811162] HW.GFX.GMA.Registers.Write: 0x04400419 -> 0x00060010:VBLANK_A [113.817761] HW.GFX.GMA.Registers.Write: 0x0422041c -> 0x00060014:VSYNC_A [113.824274] HW.GFX.GMA.Pipe_Setup.Setup_FB [113.828182] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [113.834869] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [113.841553] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A [113.848327] HW.GFX.GMA.Pipe_Setup.Setup_Display [113.852668] HW.GFX.GMA.Registers.Write: 0x009f0008 -> 0x0007027c:PLANE_BUF_CFG_1_A [113.860051] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00070240:PLANE_WM_1_A_0 [113.867170] HW.GFX.GMA.Registers.Write: 0x00070000 -> 0x0007017c:CUR_BUF_CFG_A [113.874205] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00070140:CUR_WM_A_0 [113.880977] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane [113.885665] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00070180:DSPACNTR [113.892265] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF [113.899125] HW.GFX.GMA.Registers.Write: 0x0419068f -> 0x00070190:PLANE_SIZE_1_A [113.906246] HW.GFX.GMA.Registers.Write: 0x00000069 -> 0x00070188:DSPASTRIDE [113.913019] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007018c:PLANE_POS_1_A [113.920053] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF [113.926652] HW.GFX.GMA.Registers.Write: 0x068f0419 -> 0x0006001c:PIPEASRC [113.933252] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070030:PIPEAMISC [113.939938] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A [113.946278] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A [113.953137] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A [113.959996] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A [113.967031] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A [113.973370] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A [113.980231] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A [113.987091] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A [113.994123] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A [114.000809] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A [114.007495] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A [114.014268] HW.GFX.GMA.Registers.Write: 0x91020000 -> 0x00060400:PIPEA_DDI_FUNC_CTL [114.021738] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00070008:PIPEACONF [114.028423] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00070008:PIPEACONF [114.035109] HW.GFX.GMA.Connectors.Post_On [114.038931] HW.GFX.GMA.Connectors.DDI.Post_On [114.043099] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_B [114.049091] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064100:DDI_BUF_CTL_B [114.056124] HW.GFX.GMA.Registers.Write: 0x80000080 -> 0x00064100:DDI_BUF_CTL_B [114.063758] Enabled port HDMI1
Hi,
On 09.05.19 12:03, madeeha@gmail.com wrote:
I am using Libgfxinit built for Skylake platform to enable early graphics from within a baremetal application.
interesting. AFAIR, you are the first to ask about integrating it somewhere else :)
The platform connects to an LCD via HDMI.
Just to be sure is this a regular external display, or something embedded? External HDMI displays usually just work. If there is a signal coming, they pick it up and power on. At least that's my experience.
Enabling debug log in Libgfxinit, I get the following from which it seems that the initialization completed successfully but the LCD remains powered off (orange light). Is there anything outside of this mode set sequence that I need to do to enable the display?
There might be, I'm not sure.
First, what is not visible from the log is if you set up the frame- buffer. The Intel GPU has an MMU called graphics translator table (GTT). If nothing is mapped at address 0 (which is set in your frame- buffer config), it might be that the pipe doesn't deliver any pixels and therefore no signal is delivered. If you haven't done that yet, have a look at HW.GFX.GMA.Setup_Default_FB(). It sets up a framebuffer in the preallocated graphics memory (aka. stolen memory).
Second, there's a hardware option to tweak the HDMI signal. I have never needed it so far, so it's still hard coded to the default, but an override is prepared: DDI_HDMI_Buffer_Translation in common/hw-gfx- gma-config.ads.template). The correct value for your device should be visible in the VBT (Video BIOS Table for Intel).
What often helps to debug things is a log of a working program. If you can boot Linux on your platform, that would be most easy, just add `drm.debug=0xe` to your kernel command line. And there is `gfx_test` in the libgfxinit source code (see README.md). It's best to boot with `i915.modeset=0` to disable the Intel graphics driver, and control the machine via network or a serial console.
Hope that helps, Nico
Thanks a lot for your pointers! I am going to try all of them especially DDI_HDMI_Buffer_Translation override.
interesting. AFAIR, you are the first to ask about integrating it
somewhere else :) I am sorry I just I assumed that I can use the library for internal development. The pre-OS graphics driver that I wrote in C based on information from Skylake PRM is not working so I turned to Libgfx to see what i am missing. I hope thats ok? We can not use libgfxinit in the product that we deliver.
On Fri, May 10, 2019 at 2:14 AM Nico Huber nico.h@gmx.de wrote:
Hi,
On 09.05.19 12:03, madeeha@gmail.com wrote:
I am using Libgfxinit built for Skylake platform to enable early graphics from within a baremetal application.
interesting. AFAIR, you are the first to ask about integrating it somewhere else :)
The platform connects to an LCD via HDMI.
Just to be sure is this a regular external display, or something embedded? External HDMI displays usually just work. If there is a signal coming, they pick it up and power on. At least that's my experience.
Enabling debug log in Libgfxinit, I get the following from which it seems that the initialization completed successfully but the LCD remains powered off (orange light). Is there anything outside of this mode set sequence that I need to do to enable the display?
There might be, I'm not sure.
First, what is not visible from the log is if you set up the frame- buffer. The Intel GPU has an MMU called graphics translator table (GTT). If nothing is mapped at address 0 (which is set in your frame- buffer config), it might be that the pipe doesn't deliver any pixels and therefore no signal is delivered. If you haven't done that yet, have a look at HW.GFX.GMA.Setup_Default_FB(). It sets up a framebuffer in the preallocated graphics memory (aka. stolen memory).
Second, there's a hardware option to tweak the HDMI signal. I have never needed it so far, so it's still hard coded to the default, but an override is prepared: DDI_HDMI_Buffer_Translation in common/hw-gfx- gma-config.ads.template). The correct value for your device should be visible in the VBT (Video BIOS Table for Intel).
What often helps to debug things is a log of a working program. If you can boot Linux on your platform, that would be most easy, just add `drm.debug=0xe` to your kernel command line. And there is `gfx_test` in the libgfxinit source code (see README.md). It's best to boot with `i915.modeset=0` to disable the Intel graphics driver, and control the machine via network or a serial console.
Hope that helps, Nico
On 10.05.19 10:41, Madeeha Javed wrote:
interesting. AFAIR, you are the first to ask about integrating it somewhere else :)
I am sorry I just I assumed that I can use the library for internal development. The pre-OS graphics driver that I wrote in C based on information from Skylake PRM is not working so I turned to Libgfx to see what i am missing. I hope thats ok?
That's completely OK! libgfxinit is free software. And there is no copy-left for internal usage. It's very nice to see when our work is helpful in other ways/projects, too.
Nico
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Madeeha Javed -
madeeha＠gmail.com
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Nico Huber