coreboot March 2019

coreboot@coreboot.org

49 participants
47 discussions

Coding style and automatic code formatting
by Nico Huber 28 Mar '19

28 Mar '19

Hey folks, I overeagerly reviewed and submitted a change[1] lately, that set the column limit for our C code to 96. My reasoning was that we already live a "soft" limit of 80 chars and that tools shouldn't complain about every single 8x-chars line (personally, I find this quite annoying during review). What I missed is that people use the limit to format code automatically, resulting in less line breaks, even if they'd make sense for readability. I don't want to start a discussion about line length here! If we are going to use tools for automatic formatting, we will be limited by the tool's capabilities. So it doesn't make any sense to discuss rules before we know if our tools will allow us to follow them. So what we should discuss first: if we want to let tools format our code for us. I'll just note some questions/ideas for now. Will try to have an opinion on them later. They are not all mutually exclusive. Do we want to enforce a single editor / IDE + configuration for coreboot contributions? For instance, Vim is quite configurable and helpful when writing code. This could make all tools for later processing unneces- sary. Do we want to enforce a single tool, e.g. clang-format, that does the job for us after editing a source file? The above, even if that implies a new coding style that we might not be used to? Do we want a combination of such a tool and check-patch? For instance, clang-format has a feature to ignore broken lines. This could then be handled by check-patch, to allow more complex rules. Do we just want to keep check-patch and let authors / their editors format the code? Do we want to rely (solely) on reviewers for format checking? Do we want to encourage reviewers to educate their fellows on code style (for instance, wrt. line length, less indentation levels, shorter, more meaningful identifiers, etc.)? Nico [1] https://review.coreboot.org/c/coreboot/+/31651

7 13

What's on the clang-format agenda?
by Nico Huber 28 Mar '19

28 Mar '19

Hi, trying to figure out in which ways clang-format is (supposed to be) hooked up in our git-hooks. And what role it plays, yet. There is a lint test, that so far never did something for me because it relies on a `.clang-format-scope` file (that is not in the tree?). Still, this check seems to be actively maintained. And also a `util/lint/check-style` that is only hooked up if you run `make git-config` recently (I didn't, so I'm a little surprised). This one doesn't have a scope file, it seems? What does each of these checks do? Did anybody ever use the scope file? Is it used downstream somewhere? Same as with `check-patch`, I believe we need either a white or black listing. Imagine you'd try to work on superiotool and clang-format (with its coreboot config) is run on that. Nico

3 3

coreboot leadership meeting minutes for 27 March 2019
by Martin Roth 28 Mar '19

28 Mar '19

Attendees: Julius Werner, Patrick Georgi, Martin Roth, Stefan Reinauer, Werner Zeh, Philipp Deppenwiese Make the coreboot leadership process more open - We need to start posting the meeting minutes to the mailing list again. - Discussed whether to make the coreboot leadership meeting public. - There was a concern about people who don't contribute taking up the participant slots (25 max with hangouts) - The leadership meeting will continue to use google hangouts for now, but could switch to another method if there are problems. - Accept suggestions for agenda items from the community. - There was no discussion on how to do this - For now we'll just use the mailing list. Decision: Stefan & Werner both vote for publishing minutes and making the meeting public Marc Jones hasn't been able to attend for a while, and hasn't been as active in the community as he used to be. Martin reached out to him, and he said he was open to having his spot on the leadership board replaced. - Google and Siemens have employees on the leadership board, so others working for those companies cannot be considered. - We have several nominees and we will be reaching out to those individuals to see if they're interested before making their names public. - Take this up again in the next meeting 2 weeks from now. What is the process of decision making? - The coreboot project has 3 leaders who make decisions - currently Stefan, Werner, and Marc. - Discussed the idea of making some decisions regarding code (Like line length) up to a community vote. - Further Discussed who should be able to vote on these coding changes - Final decision was that when voting, the group will be people who have been participating in coreboot's gerrit. This means people reviewing code, writing code, commenting on code, etc. - Decision: Stefan and Werner both agree that using gerrit participation is a good method. - Martin will gather gerrit metrics and we can decide further on criteria at that point. - We could use a system such as the Condorcet Internet Voting Service: https://civs.cs.cornell.edu/civs_create.html - Stefan voices concern that anonymous voting will skew the results due to lack of culpability of voters Look at hiring someone to work on the project - Philipp suggested that the coreboot project look at hiring someone to work on the project. - Google has Patrick Georgi as the coreboot community liaison - To hire someone, the project would need to bring in a large and steady amount of money to guarantee their employment - Would it make sense to request money from companies using and contributing to coreboot? - This would be similar to Arm Trusted Firmware - Major companies make significant yearly contributions. - Not a good idea for the project to hire coders directly, for various reasons. - Stefan - If we decide we need to help with the project, it should be someone to help with communications, marketing and community building. Paying people for random code reviews sets the wrong incentives for the community - Werner - Not in favor of hiring someone to do deep technical parts, but ok with the idea of hiring a community manager. Action Items: - Martin - Send out meeting minutes to coreboot community (Done!) - Martin - Post invite for next public meeting and a way to collect agenda items (Done!) - Martin - Gather Gerrit metrics for review in the next meeting - Martin - Reach out to leadership board nominees Ongoing issues for future meetings: - Revisit coreboot leadership nominees - Discuss a vote for line lengths and automatic reformatting New agenda items for future meetings: - How do we get better/more code reviews? - Discuss a standard for changes required for adding a copyright header. The next meeting will be 2019-04-10 at 17:00 UTC - https://coreboot.org/calendar.html If there are any additional items that you'd like to have discussed in a future meeting, please respond to this email, and items will be added as time permits.

1 0

Coreboot doesn't POST on ASUS KCMA-D8
by espionage724＠posteo.net 28 Mar '19

28 Mar '19

I have a KCMA-D8 motherboard with two Opteron 4226s, and 6x4GB (24GB) Hynix HMT151R7BFR4C-H9 RAM sticks. All my attempts of getting Coreboot to POST with this board so far haven't worked. I'm compiling Coreboot from Git (master branch), and can build it without issue. A pre-built Libreboot ROM (20160907) POSTs and boots fine. For Coreboot's config, I've tried including/excluding CPU microcode updates, along with some less important-sounding options. For hardware, I've tried unplugging everything external (KB/mouse), my GPU (RX 580), and only had a single RAM stick in (slot A1). I've also tried a single CPU being powered (kept the 2nd CPU in but only had a single 4-pin CPU going to the 1st CPU). Can anyone else confirm Git builds of Coreboot booting on this board, or provide any tips as to anything I could be missing? I see this issue https://ticket.coreboot.org/issues/151 but there's a board status months after that that looks like it boots: https://review.coreboot.org/cgit/board-status.git/tree/asus/kcma-d8/4.7-789…

8 8

Questions of GSoC 2019 Project
by Asami Doi 28 Mar '19

28 Mar '19

Hello, I am Asami. I am doing a master' degree at Nagoya University in Japan. These are my quick introductions: - Done internships twice at Google (Chrome OS/Chromium) - Implemented a toy OS from scratch as my hobby (Code is https://github.com/d0iasm/haribote-os) - Love programming but still poor hardware knowledge, so I want to learn it! I am interested in contributing to the GSoC 2019 project, especially the project of "Support QEMU AArch64 or MIPS". However, I am not sure I can understand this project correctly. So, I have some questions: 1. In my understanding, I will need to implement qemu-aarch64/* or qemu-mips/* in src/mainboard/emulation and src/cpu. Is my understanding correct? 2. How can I debug this project? Is it the right way to debug by running some aarch64 or mips ROMs on QEMU? 3. How can I find reviewers? I have already pushed a trivial patch( https://review.coreboot.org/c/coreboot/+/31938) and build bot added one reviewer automatically. Is it enough to review it? Thank you, Asami Doi d0iasm.pub(a)gmail.com

3 3

Re: how to change FSP-M UPD data in coreboot
by Hilbert Tu(杜睿哲_Pegatron) 27 Mar '19

27 Mar '19

Hi Lance, I use Denverton FSP version 004 and have added following code in romstage.c: mupd->FspmConfig.SpsIccClkSscSetting = 0; And it works that FSP sends HECI message to ME to have SSC disabled. Thanks for your great help!! -Hilbert This e-mail and its attachment may contain information that is confidential or privileged, and are solely for the use of the individual to whom this e-mail is addressed. If you are not the intended recipient or have received it accidentally, please immediately notify the sender by reply e-mail and destroy all copies of this email and its attachment. Please be advised that any unauthorized use, disclosure, distribution or copying of this email or its attachment is strictly prohibited. 本電子郵件及其附件可能含有機密或依法受特殊管制之資訊，僅供本電子郵件之受文者使用。台端如非本電子郵件之受文者或誤收本電子郵件，請立即回覆郵件通知寄件人，並銷毀本電子郵件之所有複本及附件。任何未經授權而使用、揭露、散佈或複製本電子郵件或其附件之行為，皆嚴格禁止。

1 0

Re: Booting from MiniPCI on X230
by Matt B 26 Mar '19

26 Mar '19

On Tue, Mar 26, 2019 at 2:44 PM Matt B <matthewwbradley6(a)gmail.com> wrote: > Hi, > > Good to hear. Does having a regular 2.5 inch drive present affect your > ability to do this? > > The above wiki notes that an msata drive is used as cache whenever such a > drive is present under the stock BIOS on the X230. While your laptop is not > the same model I'm wondering if this behavior is a product of the chipset > or the BIOS itself (in which case, it may not be an issue under coreboot). > > Thanks, > -Matt > > On Tue, Mar 26, 2019 at 9:06 AM Evgeny Zinoviev <me(a)ch1p.com> wrote: > >> Hi. I boot my W530 from mSATA SSD using only GRUB payload. SeaBIOS also >> works. >> On 26/03/2019 01:57, Matt B wrote: >> >> Hi, >> >> Does anyone know of a payload (or payloads) that would allow booting from >> an mSATA SSD within the second MiniPCI Express slot in an X230 thinkpad? >> >> http://www.thinkwiki.org/wiki/Category:X230 notes that it's possible >> under the stock BIOS when a HDD is not present, but is it possible under >> Coreboot? Has anyone tried? >> >> Thanks, >> -Matt >> >> _______________________________________________ >> coreboot mailing list -- coreboot(a)coreboot.org >> To unsubscribe send an email to coreboot-leave(a)coreboot.org >> >> _______________________________________________ >> coreboot mailing list -- coreboot(a)coreboot.org >> To unsubscribe send an email to coreboot-leave(a)coreboot.org >> >

3 2

New Defects reported by Coverity Scan for coreboot
by scan-admin＠coverity.com 26 Mar '19

26 Mar '19

Hi, Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan. 1 new defect(s) introduced to coreboot found with Coverity Scan. 1 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan. New defect(s) Reported-by: Coverity Scan Showing 1 of 1 defect(s) ** CID 1400443: Insecure data handling (INTEGER_OVERFLOW) /src/arch/x86/smbios.c: 537 in smbios_write_type2() ________________________________________________________________________________________________________ *** CID 1400443: Insecure data handling (INTEGER_OVERFLOW) /src/arch/x86/smbios.c: 537 in smbios_write_type2() 531 t->location_in_chassis = smbios_add_string(t->eos, 532 smbios_mainboard_location_in_chassis()); 533 t->board_type = smbios_mainboard_board_type(); 534 t->chassis_handle = chassis_handle; 535 len = t->length + smbios_string_table_len(t->eos); 536 *current += len; >>> CID 1400443: Insecure data handling (INTEGER_OVERFLOW) >>> Overflowed or truncated value (or a value computed from an overflowed or truncated value) "len" used as return value. 537 return len; 538 } 539 540 static int smbios_write_type3(unsigned long *current, int handle) 541 { 542 struct smbios_type3 *t = (struct smbios_type3 *)*current; ________________________________________________________________________________________________________ To view the defects in Coverity Scan visit, https://u2389337.ct.sendgrid.net/wf/click?upn=08onrYu34A-2BWcWUl-2F-2BfV0V0…

1 0

Booting from MiniPCI on X230
by Matt B 26 Mar '19

26 Mar '19

Hi, Does anyone know of a payload (or payloads) that would allow booting from an mSATA SSD within the second MiniPCI Express slot in an X230 thinkpad? http://www.thinkwiki.org/wiki/Category:X230 notes that it's possible under the stock BIOS when a HDD is not present, but is it possible under Coreboot? Has anyone tried? Thanks, -Matt

2 1

Beginner Information - What can be a payload?
by Rafael Send 25 Mar '19

25 Mar '19

Hi, Total beginner here. In fact, I'm just researching interesting possibilities for using this and how coreboot works. In particular, I'm wondering how to create custom payloads, and what sorts of things can be payloads. According to the wiki, the target file for a payload is an ELF file. However, I'm not clear what can be turned into a payload. The wiki also says that entire (small) Linux distros can be made into payloads (and SeaBIOS can use floppy images), but I'm unclear on what this means and how to do it. For example, if I wanted to turn a TinyCore Live CD into a coreboot payload, could that be done? TinyCore copies itself to RAM and doesn't require write access in that mode, so as far was what the distro expects that would be compatible. Are there any resources or articles I can read that would provide more detailed information about this subject? Cheers, R

3 2

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot March 2019