About support for my netbook
I have attached all the log files releated to the dmidecode ectool inteltool etc. Can you read those out and tell me if it is possible to port coreboot to my netbook? If it is then how hard will it be?
Hi, The Intel FSP (Firmware Support Package) is a required part of chipset initialisation. I can't find one for Cedar View, (github.com/IntelFsp/FSP) the family your CPU, an Atom N2600, is a part of. Somebody else should confirm (I don't know your platform well), but it seems impossible about this. Sorry.
Hi, it may also be a Cedarview chipset. According to my knowledge there is no support for Cedarview chipset in coreboot. However coreboot has slightly older (1 year older) chipset support - Pineview. My experience is very little when it comes to older chipsets, but judging by how sanydbridge and ivybridge works, pineview and cedarview should have most thing in common. That said, i would try to go out from pineview northbridge in coreboot. The next question is which southbirdge to choose. There are two mainboards based on pineview. Most likely you would have to select: select CPU_INTEL_SOCKET_FCBGA559 select NORTHBRIDGE_INTEL_PINEVIEW select SOUTHBRIDGE_INTEL_I82801GX in your mainboard Kconfig. The CPU socket also matches according to Intel ARK about N2600 https://ark.intel.com/content/www/us/en/ark/products/58916/intel-atom-proces... The initialization for that particular silicon is native so no FSP required. Since it may be hard to debug, I advise to get a USB debug dongle and enable it in coreboot menuconfig. But before that, find out which USB port on this netbook is connected to EHCI debug port. Typically it is the first port on the root hub. You can find it out using lspci and lsusb in Linux (by connecting a USB-UART dongle for example to the investigated port). The dongles supported by coreboot are: FTDI232H/FTDI2232H, or you can use BeagleBone board. Regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com On 12.03.2020 06:06, Benjamin Doron wrote:
Hi, The Intel FSP (Firmware Support Package) is a required part of chipset initialisation. I can't find one for Cedar View, (github.com/IntelFsp/FSP) the family your CPU, an Atom N2600, is a part of.
Somebody else should confirm (I don't know your platform well), but it seems impossible about this. Sorry. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi, On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski <michal.zygowski@3mdeb.com> wrote:
Hi,
it may also be a Cedarview chipset. According to my knowledge there is no support for Cedarview chipset in coreboot. However coreboot has slightly older (1 year older) chipset support - Pineview.
Pineview is very different, though. Memory initialization for Pineview resembles that of Eaglelake (src/northbridge/intel/x4x). Although it only has one memory channel, the registers in MCHBAR are very similar. On the other hand, Cedarview's internal architecture differs radically from Pineview, and it is actually more like Bay Trail. Both use the IOSF architecture, and memory is initialized by interacting with various "units" inside the chip. About the southbridge, I don't know if Cedarview can use NM10 (found on Pineview) or if it must use an EG20T PCH: https://ark.intel.com/content/www/us/en/ark/products/52501/intel-platform-co...
My experience is very little when it comes to older chipsets, but judging by how sanydbridge and ivybridge works, pineview and cedarview should have most thing in common. That said, i would try to go out from pineview northbridge in coreboot. The next question is which southbirdge to choose. There are two mainboards based on pineview. Most likely you would have to select:
select CPU_INTEL_SOCKET_FCBGA559 select NORTHBRIDGE_INTEL_PINEVIEW select SOUTHBRIDGE_INTEL_I82801GX
in your mainboard Kconfig. The CPU socket also matches according to Intel ARK about N2600
https://ark.intel.com/content/www/us/en/ark/products/58916/intel-atom-proces...
Note that, even though the LGA775 socket was used for many different CPU generations, not every LGA775 mainboard can take any LGA775 CPU.
The initialization for that particular silicon is native so no FSP required. Since it may be hard to debug, I advise to get a USB debug dongle and enable it in coreboot menuconfig. But before that, find out which USB port on this netbook is connected to EHCI debug port. Typically it is the first port on the root hub. You can find it out using lspci and lsusb in Linux (by connecting a USB-UART dongle for example to the investigated port). The dongles supported by coreboot are: FTDI232H/FTDI2232H, or you can use BeagleBone board.
There's also `util/find_usbdebug` in coreboot.
Regards,
-- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com
On 12.03.2020 06:06, Benjamin Doron wrote:
Hi, The Intel FSP (Firmware Support Package) is a required part of chipset initialisation. I can't find one for Cedar View, (github.com/IntelFsp/FSP) the family your CPU, an Atom N2600, is a part of.
There is an old FSP around: QueensBayFspBinPkg. However, it will not work with current coreboot, as FSP 1.0 support had to be dropped.
Somebody else should confirm (I don't know your platform well), but it seems impossible about this. Sorry.
The first MinnowBoard uses a Cedarview chip. There is some ancient EFI firmware around: https://github.com/RafaelRMachado/MinnowBoard/tree/master There might be something better thank stinky binaries somewhere, but I don't know if it's still around after eight years...
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards, Angel Pons
Regarding FSPs: My mistake.
About the southbridge, I don't know if Cedarview can use NM10 (found on Pineview) or if it must use an EG20T PCH:
I noted that the inteltool log mentioned an NM10 On Fri., Mar. 13, 2020, 6:24 a.m. Angel Pons, <th3fanbus@gmail.com> wrote:
Hi,
On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski <michal.zygowski@3mdeb.com> wrote:
Hi,
it may also be a Cedarview chipset. According to my knowledge there is no support for Cedarview chipset in coreboot. However coreboot has slightly older (1 year older) chipset support - Pineview.
Pineview is very different, though. Memory initialization for Pineview resembles that of Eaglelake (src/northbridge/intel/x4x). Although it only has one memory channel, the registers in MCHBAR are very similar.
On the other hand, Cedarview's internal architecture differs radically from Pineview, and it is actually more like Bay Trail. Both use the IOSF architecture, and memory is initialized by interacting with various "units" inside the chip.
About the southbridge, I don't know if Cedarview can use NM10 (found on Pineview) or if it must use an EG20T PCH:
https://ark.intel.com/content/www/us/en/ark/products/52501/intel-platform-co...
My experience is very little when it comes to older chipsets, but judging by how sanydbridge and ivybridge works, pineview and cedarview should have most thing in common. That said, i would try to go out from pineview northbridge in coreboot. The next question is which southbirdge to choose. There are two mainboards based on pineview. Most likely you would have to select:
select CPU_INTEL_SOCKET_FCBGA559 select NORTHBRIDGE_INTEL_PINEVIEW select SOUTHBRIDGE_INTEL_I82801GX
in your mainboard Kconfig. The CPU socket also matches according to Intel ARK about N2600
https://ark.intel.com/content/www/us/en/ark/products/58916/intel-atom-proces...
Note that, even though the LGA775 socket was used for many different CPU generations, not every LGA775 mainboard can take any LGA775 CPU.
The initialization for that particular silicon is native so no FSP required. Since it may be hard to debug, I advise to get a USB debug dongle and enable it in coreboot menuconfig. But before that, find out which USB port on this netbook is connected to EHCI debug port. Typically it is the first port on the root hub. You can find it out using lspci and lsusb in Linux (by connecting a USB-UART dongle for example to the investigated port). The dongles supported by coreboot are: FTDI232H/FTDI2232H, or you can use BeagleBone board.
There's also `util/find_usbdebug` in coreboot.
Regards,
-- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com
On 12.03.2020 06:06, Benjamin Doron wrote:
Hi, The Intel FSP (Firmware Support Package) is a required part of chipset initialisation. I can't find one for Cedar View, (github.com/IntelFsp/FSP) the family your CPU, an Atom N2600, is a part of.
There is an old FSP around: QueensBayFspBinPkg. However, it will not work with current coreboot, as FSP 1.0 support had to be dropped.
Somebody else should confirm (I don't know your platform well), but it seems impossible about this. Sorry.
The first MinnowBoard uses a Cedarview chip. There is some ancient EFI firmware around: https://github.com/RafaelRMachado/MinnowBoard/tree/master
There might be something better thank stinky binaries somewhere, but I don't know if it's still around after eight years...
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
_______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards,
Angel Pons _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
On 3/13/20 11:23 AM, Angel Pons wrote:
Hi,
On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski <michal.zygowski@3mdeb.com> wrote:
Hi,
it may also be a Cedarview chipset. According to my knowledge there is no support for Cedarview chipset in coreboot. However coreboot has slightly older (1 year older) chipset support - Pineview.
Pineview is very different, though. Memory initialization for Pineview resembles that of Eaglelake (src/northbridge/intel/x4x). Although it only has one memory channel, the registers in MCHBAR are very similar.
On the other hand, Cedarview's internal architecture differs radically from Pineview, and it is actually more like Bay Trail. Both use the IOSF architecture, and memory is initialized by interacting with various "units" inside the chip.
About the southbridge, I don't know if Cedarview can use NM10 (found on Pineview) or if it must use an EG20T PCH: https://ark.intel.com/content/www/us/en/ark/products/52501/intel-platform-co...
Hi, isn't Cedarview a processor code name and Cedar Trail platform code name? This presentation mix both: https://manualzz.com/doc/26041007/cedar-trail-platform-bios-session Interesting slide is 21, this lead me to pre-FSP time when BLDK was used and I found this: https://www.intel.pl/content/dam/www/public/us/en/documents/guides/cedar-tra... Probably only companies that have CNDA with Intel can still obtain those, but who knows maybe it lays on some server somewhere. Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com
Hi Piotr, On Mon, May 11, 2020 at 4:02 PM Piotr Król <piotr.krol@3mdeb.com> wrote:
On 3/13/20 11:23 AM, Angel Pons wrote:
Hi,
On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski <michal.zygowski@3mdeb.com> wrote:
Hi,
it may also be a Cedarview chipset. According to my knowledge there is no support for Cedarview chipset in coreboot. However coreboot has slightly older (1 year older) chipset support - Pineview.
Pineview is very different, though. Memory initialization for Pineview resembles that of Eaglelake (src/northbridge/intel/x4x). Although it only has one memory channel, the registers in MCHBAR are very similar.
On the other hand, Cedarview's internal architecture differs radically from Pineview, and it is actually more like Bay Trail. Both use the IOSF architecture, and memory is initialized by interacting with various "units" inside the chip.
About the southbridge, I don't know if Cedarview can use NM10 (found on Pineview) or if it must use an EG20T PCH: https://ark.intel.com/content/www/us/en/ark/products/52501/intel-platform-co...
Hi, isn't Cedarview a processor code name and Cedar Trail platform code name?
Yes, I was talking about the processor. Also, looks like I confused Cedarview with the older Tunnel Creek. Cedarview would only support the EG20T PCH, it seems.
This presentation mix both: https://manualzz.com/doc/26041007/cedar-trail-platform-bios-session
Interesting slide is 21, this lead me to pre-FSP time when BLDK was used and I found this: https://www.intel.pl/content/dam/www/public/us/en/documents/guides/cedar-tra...
I recall that there were binaries for this somewhere, but can't find them anymore.
Probably only companies that have CNDA with Intel can still obtain those, but who knows maybe it lays on some server somewhere.
Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards, Angel
Thanks for attention. But my log files says the bridge chip is NM10 Express chipset. And so what do you say? Is it impossible to port coreboot to this platform? If you need log files, then please reply. I will attach them for you. Thanks. On Mon, 11 May 2020, 11:19 p.m. Angel Pons, <th3fanbus@gmail.com> wrote:
Hi Piotr,
On Mon, May 11, 2020 at 4:02 PM Piotr Król <piotr.krol@3mdeb.com> wrote:
On 3/13/20 11:23 AM, Angel Pons wrote:
Hi,
On Thu, Mar 12, 2020 at 11:07 AM Michal Zygowski <michal.zygowski@3mdeb.com> wrote:
Hi,
it may also be a Cedarview chipset. According to my knowledge there is no support for Cedarview chipset in coreboot. However coreboot has slightly older (1 year older) chipset support - Pineview.
Pineview is very different, though. Memory initialization for Pineview resembles that of Eaglelake (src/northbridge/intel/x4x). Although it only has one memory channel, the registers in MCHBAR are very similar.
On the other hand, Cedarview's internal architecture differs radically from Pineview, and it is actually more like Bay Trail. Both use the IOSF architecture, and memory is initialized by interacting with various "units" inside the chip.
About the southbridge, I don't know if Cedarview can use NM10 (found on Pineview) or if it must use an EG20T PCH:
https://ark.intel.com/content/www/us/en/ark/products/52501/intel-platform-co...
Hi, isn't Cedarview a processor code name and Cedar Trail platform code name?
Yes, I was talking about the processor.
Also, looks like I confused Cedarview with the older Tunnel Creek. Cedarview would only support the EG20T PCH, it seems.
This presentation mix both: https://manualzz.com/doc/26041007/cedar-trail-platform-bios-session
Interesting slide is 21, this lead me to pre-FSP time when BLDK was used and I found this:
https://www.intel.pl/content/dam/www/public/us/en/documents/guides/cedar-tra...
I recall that there were binaries for this somewhere, but can't find them anymore.
Probably only companies that have CNDA with Intel can still obtain those, but who knows maybe it lays on some server somewhere.
Best Regards, -- Piotr Król Embedded Systems Consultant GPG: B2EE71E967AA9E4C https://3mdeb.com | @3mdeb_com _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards,
Angel _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
participants (5)
-
Alif Ilhan -
Angel Pons -
Benjamin Doron -
Michal Zygowski -
Piotr Król