coreboot March 2020

coreboot@coreboot.org

34 participants
46 discussions

Debugging using gdb
by harshitsharmajs＠gmail.com 29 Mar '20

29 Mar '20

Hello Everybody, I am new to coreboot build environment and need your help in using gdb with coreboot. I want to use gdb to take a closer look at the stages in coreboot and the order they are executed in. I also want to single step through the code to see what functions are being called in each stage and during transition from one stage to another. Firstly, I am not even sure if gdb works during transition. Does it? These are the steps I followed: 1. First I set up the coreboot environment by following this tutorial. https://doc.coreboot.org/tutorial/part1.html. (I also enabled Gdb Wait by going to Debugging menu in coreboot's configuration.) 2. Then I ran the image on qemu $ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -s -S 3. In another terminal, I started gdb and entered the following command $ target remote localhost:1234 4. From here, I am able to single step using 'si' but I am not able to set a breakpoint using 'break' at say romstage.c or hardwaremain.c. I get the following error: ''No symbol table is loaded. Use the "file" command. Make breakpoint pending on future shared library load? (y or [n])'' Can anyone tell me where I went wrong? Thanks, Harshit

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Could anyone successfully using T440p to boot Windows share your config or build output image?
by Dalao 28 Mar '20

28 Mar '20

I have almost tried everything these days trying to boot Windows 10 using T440p with coreboot, but still haven't succeed. I had created my Windows 10 installer usb by writing the en_windows_10_business_editions_version_1909_updated_jan_2020_x64_dvd_e9cb5542.iso to usb drive through Rufus, and checked this usb works on a T420 with coreboot. But this usb does not work on T440p. I have tried SeaBIOS, Tianocore, and with/without VGA BIOS but still not work. When using SeaBIOS without VGA BIOS, I can see a loading bar at the bottom but then hanging there. When using SeaBIOS with VGA BIOS, the backlight is on but the screen shows nothing. I tried extract data.vbt from vendor BIOS and replaced the one from source with it, still not work. I did see one post on reddit mentioned that he had been able to boot Windows 10. https://www.reddit.com/r/coreboot/comments/enor0h/t440p_tianocore_and_windo… I was wondering is my hardware different from others' T440p? Then I tried cherry-pick this patch (git fetch https://review.coreboot.org/coreboot refs/changes/90/30890/10 && git cherry-pick FETCH_HEAD) and using autoport to generate source of my T440p. Then I compared it with masters' source, but there is not much difference. I tried changed CPU and RAM but still not work. Since I make a fresh install of Windows on the T440p, I tried install it on T420 and then change the hard disk to T440p. It still does not work. When I use Tianocore, the circle stopped spin and hangs at "Preparing Automatic Repair": https://imgur.com/nY9wAQR Sometimes it hangs shows a BSOD of "MACHINE CHECK EXCEPTION" But there is no further information https://imgur.com/HKio1QY (I tried to find if there are mce error logs under linux using rasdaemon but I get nothing https://wiki.archlinux.org/index.php/Machine-check_exception) I also checked C:\Windows\minidump to see if there are BSOD dumps but there is none. I almost out of idea, I will attach all my files, original BIOS (a modded one with ME cleaned, advanced menu unlocked, and whitelist unlocked), auto port generated logs and sources, and the mrc.bin, data.vbt, defconfig, and also my build coreboot.rom. https://mega.nz/#!TNlCFKjA!rXDhP5K4S8FZpSif8Ntj-NUGKML4kFYtwAG_70XTpsU Could anyone help me with this? Could anyone successfully using T440p to boot Windows share the steps you did it and your config or your coreboot.rom (last 4MB)?

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Unit testing proposal
by Jan Dąbroś 28 Mar '20

28 Mar '20

Hi everybody, Firstly, I want to introduce myself. I'm Jan Dabros and I'm working for Semihalf - embedded system company based in Poland. I am a big fan of coreboot and the idea of open firmware in general, that's why would really like to contribute to this project. Let's see how it goes :) My proposal is to start unit testing coreboot codebase to some possible extent, in order to improve its reliability, prepare subsystem for enabling quick tests and to make test-driven-development possible. Hopefully this makes sense to (at least some) of you. For this purpose, it's necessary to select some C unit test framework - unless we want to create something completely new. I have done evaluation of couple of such libraries and described its results in the document [1] along with my selected candidate and implementation proposal. This may be a good starting point for a discussion about what framework do you think fit the most and how unit testing may be applied to coreboot codebase. Together with above doc, I also created a simple example of unit test and sent it for review [2]. Commit message comprises steps for running it. Any comments and remarks are very appreciated, both to the doc and the code. Thanks in advance! [1] https://review.coreboot.org/c/coreboot/+/39893/1 [2] https://review.coreboot.org/c/coreboot/+/39894/1 Best Regards, Jan

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Google Season of Docs
by Patrick Georgi 25 Mar '20

25 Mar '20

Hi everybody, we just had our project leadership meeting and I brought up the Google Season of Docs[0] programme which is similar to Summer of Code but for documentation. (Note to meeting attendants: I mentioned that the application deadline for projects has already passed, but I was wrong about that. According to the timeline[1] we have until May 4 to decide.) The programme's goal is to connect Open Source projects (like coreboot) with technical writers and if there's one thing coreboot can benefit from, I'd say it's having somebody who knows what they're doing write documentation for the project. There was some interest in having coreboot take part there, but it requires at least two project admins (people willing to coordinate) and also mentors for the tech writers (if there's interest on their side to work with coreboot), which may or may not overlap with the project admins. I'm not sure I can do a good job managing both Summer of Code and Season of Docs (which overlap timewise), but there was nobody else able to step up. So: What's the interest for this in the wider community and do we have people who could imagine organizing our participation there? The first step would be to dig into their application procedure, and I guess I could help a bit there (if it's at all similar to Summer of Code's). If they don't take us, we'd drop out early May, otherwise admin work seems to require some attention until December. Regards, Patrick [0] https://developers.google.com/season-of-docs [1] https://developers.google.com/season-of-docs/docs/timeline -- Google Germany GmbH, ABC-Str. 19, 20354 Hamburg Registergericht und -nummer: Hamburg, HRB 86891, Sitz der Gesellschaft: Hamburg Geschäftsführer: Paul Manicle, Halimah DeLaine Prado

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Difference between GA-B75M-D3V and GA-B75M-D3H?
by Matt B 25 Mar '20

25 Mar '20

Hi, Noticed someone running a GA-B75M-D3V with coreboot but that it hadn't had a status report since 2017. I did notice that GA-B75M-D3H is still around though with a status from may of 2019. Is the GA-B75M-D3H supported in the latest master? What's the difference between these two? Thanks, -Matt

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[GSOC] Query regarding proposals
by Sindhoor Tilak 24 Mar '20

24 Mar '20

Hi All This is my first time here applying for GSoC. I'm interested in couple of ideas posted. I wanted to know if multiple proposals are accepted? Thanks. Sindhoor

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Re: Error while building libpayload for coreboot-QEMU
by Manas Gupta 23 Mar '20

23 Mar '20

Hi I am a second year student pursuing computer science and applied mathematics at IIIT-Delhi, India. I was building libpayload when I ran into some errors. >CC libpci/libpci.libpci.o >make: MMD: No such file or directory >AR build/libpci.a >make: rc: No such file or directory >make: *** [Makefile.inc:89: build/libpci.a] Error 127 I found this archived source ( https://coreboot.coreboot.narkive.com/ZD8Imata/emulating-coreboot-with-qemu) and it mentioned to use tty in order to `make config`. I tried that way too but still got the same error. Can anyone help me or point me what could be the fix? Thanks Manas

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Query related to GSoC 2020
by Shridhara Hegde 21 Mar '20

21 Mar '20

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[RFC] Documentation/Intel: s5 charging applet design document
by Paul Menzel 19 Mar '20

19 Mar '20

Dear coreboot folks, I’d like to draw your attention the change-set 37762 [1]. > Documentation/Intel: s5 charging applet design document > > This document describes design details of s5 charging applet which we > are proposing for Intel based chromebook designs. We can take advantage > of FSP utility to display battery symbol to user even before OS boots > and have enhanced user experience by showing critical battery symbol or > battery percentage when device is in s5 and being charged. > > This feature is already present in many devices across multiple OS so > idea is to bring this feature to chromebooks If I understand the proposal correctly, in low-battery situations a battery logo is supposed to be displayed by FSP or coreboot. In my opinion, displaying things in coreboot itself violates the goals of coreboot, and it should be done in a payload. If I am misunderstanding something, it’d be great, if you could clarify that. Kind regards, Paul [1]: https://review.coreboot.org/c/coreboot/+/37762

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Need PCI(e) vs PNP resource allocation help
by Keith Hui 19 Mar '20

19 Mar '20

Hi guys, I am again running into problems with my p8z77-m port[1]. My port fails to boot after trying to enable my hardware monitor. I think I am running into a I/O port allocation conflict. The hardware monitor needs to be allocated I/O port 0x290 and the actual accesses would occur at 0x295/0x296. So I need to reserve ports 0x290-0x296 for it, but I don't know how to go about this. These are the devicetree.cb entries: device pnp 2e.b on # HWM, LED io 0x60 = 0x290 # HWM address drq 0xe4 = 0xf9 # GP50,52,55 drq 0xf0 = 0x3e # Enable all fan input debouncer end Attached are serial logs with and without the HWM devicetree entries. You'll see a I/O port conflict with a PCIe root port device and the boot froze when it tries to enable that device. There is no more output after what is seen in the log with HWM. At least the normal/fallback mechanism is working so I should not have to use my Arduino again. Help again appreciated. Thanks Keith [1] https://review.coreboot.org/c/coreboot/+/38988

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coreboot March 2020