coreboot February 2012

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Patch set updated for coreboot: 7380dcf Intel cpus: copy model_6ex CAR code
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 7380dcfbd652b16fbeafb484454f3dcbcabf80cc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 00:15:30 2012 +0200 Intel cpus: copy model_6ex CAR code Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 268 +++++++++++++++++++++++++++++++++ 1 files changed, 268 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..08f5b11 --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/stack.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> + +#define CPU_MAXPHYADDR 36 +#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl $0x000C4500, %eax + movl $0xFEE00300, %esi + movl %eax, (%esi) + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + /* Enable L2 cache. */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion. */ + movl $CACHE_AS_RAM_BASE, %esi + movl %esi, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + // movl $0x23322332, %eax + xorl %eax, %eax + rep stosl + + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax +#endif + movl %eax, %esp + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function. */ + call main + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: +

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Patch set updated for coreboot: 33fd183 Intel cpus: apply some good programming practices in new CAR
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643 -gerrit commit 33fd183f1da7a734647fc876d607785990fc6d90 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 01:45:44 2012 +0200 Intel cpus: apply some good programming practices in new CAR Delete dead CAR code and whitespace fixes. Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 39 ++++++++++++-------------------- 1 files changed, 15 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index ed207db..a6cbd6b 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -21,6 +21,10 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/lapic_def.h> + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) @@ -38,9 +42,9 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -86,17 +90,16 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ @@ -131,11 +134,10 @@ clear_mtrrs: /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -146,6 +148,7 @@ clear_mtrrs: /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f) @@ -167,18 +170,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -196,7 +187,7 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx

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Patch set updated for coreboot: f6bf251 Apply cache-as-ram conditionally on socket mPGA604
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607 -gerrit commit f6bf251e4434d69c7efc33a14b449b4972cfa67c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 14:01:34 2012 +0200 Apply cache-as-ram conditionally on socket mPGA604 The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 8 +------- src/cpu/intel/socket_mPGA604/Kconfig | 17 ++++++++++++++++- src/cpu/intel/socket_mPGA604/Makefile.inc | 2 ++ 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 624b510..ce1f50b 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..4fa7569 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,5 +1,10 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X @@ -13,4 +18,14 @@ config CPU_INTEL_SOCKET_MPGA604 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..fb1cacd 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc +

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Patch set updated for coreboot: 217afa9 Intel cpus: add hyper-threading CPU support to new CAR
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit 217afa9f388738bbb43e80cd631115973b438ce1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 02:02:27 2012 +0200 Intel cpus: add hyper-threading CPU support to new CAR This improvement of CAR code starts the sibling CPU processors and clears their cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 147 ++++++++++++++++++++++++++++++--- 1 files changed, 134 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 641a2f3..18fb176 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +27,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) @@ -41,12 +44,9 @@ cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself. */ - movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax - movl %eax, (%edi) - - /* Zero out all fixed range and variable range MTRRs. */ + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -59,12 +59,127 @@ clear_mtrrs: dec %edi jnz clear_mtrrs + post_code(0x21) + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr + post_code(0x22) + + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~CPU_PHYSMASK_HI), %edx + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_init + +bsp_init: + + post_code(0x23) + + /* Send INIT IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + post_code(0x24) + + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc sipi_complete + bswapl %ebx + cmpb $01, %bh + jbe sipi_complete + +hyper_threading_cpu: + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x25) + + /* Send Start IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x26) + + /* Wait for sibling CPU to start. */ +1: movl $(MTRRphysBase_MSR(0)), %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + + +ap_init: + post_code(0x27) + + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + post_code(0x28) + + /* MTRR registers are shared between HT siblings. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(1<<12), %eax + xorl %edx, %edx + wrmsr + + post_code(0x29) + +ap_halt: + cli +1: hlt + jnz 1b + + + +sipi_complete: + + post_code(0x2a) + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax @@ -83,6 +198,8 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr + post_code(0x2b) + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). * * MSR is set when DisplayFamily_DisplayModel is one of: @@ -118,6 +235,8 @@ has_msr_11e: wrmsr no_msr_11e: + post_code(0x2c) + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax @@ -136,6 +255,8 @@ no_msr_11e: orl $(1 << 30), %eax movl %eax, %cr0 + post_code(0x2d) + #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx @@ -160,6 +281,8 @@ no_msr_11e: andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 + post_code(0x2e) + /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ @@ -173,14 +296,12 @@ no_msr_11e: movl %esp, %ebp pushl %eax - post_code(0x23) + post_code(0x2f) /* Call romstage.c main function. */ call main addl $4, %esp - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -188,7 +309,7 @@ no_msr_11e: orl $(1 << 30), %eax movl %eax, %cr0 - post_code(0x31) + post_code(0x34) /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx @@ -196,18 +317,18 @@ no_msr_11e: andl $(~MTRRdefTypeEn), %eax wrmsr - post_code(0x31) + post_code(0x35) invd - post_code(0x33) + post_code(0x36) /* Enable cache. */ movl %cr0, %eax andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 - post_code(0x36) + post_code(0x37) /* Disable cache. */ movl %cr0, %eax

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Patch set updated for coreboot: 265da9b Intel cpus: cache actual size of the Flash ROM device
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/641 -gerrit commit 265da9b2659d2e18bb59e6a99792492fac71bdc8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 00:24:15 2012 +0200 Intel cpus: cache actual size of the Flash ROM device Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 9 ++++++--- src/mainboard/Kconfig | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 08f5b11..ed207db 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -25,6 +25,9 @@ #define CPU_MAXPHYADDR 36 #define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -203,13 +206,13 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a34bd85 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -285,6 +285,10 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 +config CACHE_ROM_SIZE + hex + default ROM_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE

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Patch set updated for coreboot: ed37431 Add support for RAM-less multi-processor init
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit ed3743123e4f832be6761a9b550cab5cc8a3f934 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..0bdef34 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -31,6 +31,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help

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Patch set updated for coreboot: 6b350da Intel cpus: improve CPU compatibility of new CAR
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/644 -gerrit commit 6b350da4fd2a1f504340fdeed75c2b916220fab1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 23:12:04 2012 +0200 Intel cpus: improve CPU compatibility of new CAR Most or many Xeons have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 31 ++++++++++++++++++++++++++++++- 1 files changed, 30 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index a6cbd6b..641a2f3 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -83,11 +83,40 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr - /* Enable L2 cache. */ + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). + * + * MSR is set when DisplayFamily_DisplayModel is one of: + * 06_0x, 06_17, 06_1C + * + * Description says this bit enables use of WBINVD and FLUSH#. + * Should this be set only after the system bus and/or memory + * controller can successfully handle write cycles? + */ + +#define EAX_FAMILY(a) (a << 8) /* for family <= 0fH */ +#define EAX_MODEL(a) (((a & 0xf0) << 12) | ((a & 0xf) << 4)) + + movl $1, %eax + cpuid + movl %eax, %ebx + andl $EAX_FAMILY(0x0f), %eax + cmpl $EAX_FAMILY(0x06), %eax + jne no_msr_11e + movl %ebx, %eax + andl $EAX_MODEL(0xff), %eax + cmpl $EAX_MODEL(0x17), %eax + je has_msr_11e + cmpl $EAX_MODEL(0x1c), %eax + je has_msr_11e + andl $EAX_MODEL(0xf0), %eax + cmpl $EAX_MODEL(0x00), %eax + jne no_msr_11e +has_msr_11e: movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +no_msr_11e: /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax

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New patch to review for coreboot: 5fc1b63 Intel cpus: get MAXPHYADDR at runtime for new CAR
by Kyösti Mälkki 28 Feb '12

28 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/686 -gerrit commit 5fc1b63e0baa583b2012569ee8574fbf1dc5943b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 28 02:06:45 2012 +0200 Intel cpus: get MAXPHYADDR at runtime for new CAR Use CPUID to get MAXPHYADDR and set MTRR masks correctly. Also only BSP CPU clears MTRRs and initializes its Local APIC. Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 58 +++++++++++++++++++++++++------- 1 files changed, 45 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 18fb176..2485e20 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -29,9 +29,6 @@ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) - /* Base address to cache all of Flash ROM, just below 4GB. */ #define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) @@ -44,9 +41,14 @@ cache_as_ram: post_code(0x20) + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_init + /* Zero out all fixed range and variable range MTRRs. - * For hyper-threaded CPU MTRRs are shared so we actually - * clear them more than once, but we don't care. */ + * For hyper-threaded CPUs these are shared. + */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -69,15 +71,45 @@ clear_mtrrs: post_code(0x22) - /* Enable local apic. */ + /* Determine CPU_ADDR_BITS and load PHYSMASK high + * word to %edx. + */ + movl $0x80000000, %eax + cpuid + cmpl $0x80000008, %eax + jc addrsize_no_MSR + movl $0x80000008, %eax + cpuid + movb %al, %cl + sub $32, %cl + movl $1, %edx + shl %cl, %edx + subl $1, %edx + jmp addrsize_set_high +addrsize_no_MSR: + movl $1, %eax + cpuid + andl $(1<<6 | 1<<17), %edx /* PAE or PSE36 */ + jz addrsize_set_high + movl $0x0f, %edx + + /* Preload high word of address mask (in %edx) for Variable + * MTRRs 0 and 1 and enable local apic at default base. + */ +addrsize_set_high: + xorl %eax, %eax + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr movl $LAPIC_BASE_MSR, %ecx + not %edx + movl %edx, %ebx rdmsr - andl $(~CPU_PHYSMASK_HI), %edx + andl %ebx, %edx andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax wrmsr - andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax - jz ap_init bsp_init: @@ -188,8 +220,8 @@ sipi_complete: /* Set Cache-as-RAM mask. */ movl $(MTRRphysMask_MSR(0)), %ecx + rdmsr movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable MTRR. */ @@ -271,7 +303,7 @@ no_msr_11e: wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx + rdmsr movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif /* CONFIG_XIP_ROM_SIZE */ @@ -343,8 +375,8 @@ no_msr_11e: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx + rdmsr movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr /* Enable caching and Speculative Reads for Flash ROM device. */ @@ -353,8 +385,8 @@ no_msr_11e: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx + rdmsr movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx wrmsr post_code(0x39)

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Fwd: [Announce] Now Accepting Applications for Mentoring Organizations for GSoC 2012
by QingPei Wang 28 Feb '12

28 Feb '12

kindly reminder that GSOC 2012 is coming~~~ Best wishes QingPei Wang Phone: 86+018930528086 ---------- Forwarded message ---------- From: Carol Smith <carols(a)google.com> Date: Tue, Feb 28, 2012 at 3:47 AM Subject: [Announce] Now Accepting Applications for Mentoring Organizations for GSoC 2012 To: Google Summer of Code Mentors List < google-summer-of-code-mentors-list(a)googlegroups.com> Hi all, We're pleased to announce the applications for mentoring organizations for GoogleSummer of Code 2012 are now being accepted [1]. Please go Melange [2] to apply on behalf of your organization. Please note that the application period [3] closes on 9 March at 23:00 UTC. We will not accept any late applications for any reason. [1] - http://google-opensource.blogspot.com/2012/02/mentoring-organization-applic… [2] - http://www.google-melange.com [3] - http://www.google-melange.com/gsoc/events/google/gsoc2012 Cheers, Carol -- You received this message because you are subscribed to the Google Groups "Google Summer of Code Mentors List" group. To post to this group, send email to google-summer-of-code-mentors-list(a)googlegroups.com. To unsubscribe from this group, send email to google-summer-of-code-mentors-list+unsubscribe(a)googlegroups.com. For more options, visit this group at http://groups.google.com/group/google-summer-of-code-mentors-list?hl=en.

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Patch merged into coreboot/master: 6bfce95 asus/m4a785t-m: correct the CPU microcode patch selection
by gerrit＠coreboot.org 27 Feb '12

27 Feb '12

the following patch was just integrated into master: commit 6bfce95ce462ea42f08b20a846e07b4c37681b2c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Feb 21 22:29:30 2012 +0100 asus/m4a785t-m: correct the CPU microcode patch selection Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 <ruik> ruik@ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 <ruik> 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 <ruik> the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explained(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Build-Tested: build bot (Jenkins) at Tue Feb 21 23:49:42 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Tue Feb 21 23:02:04 2012, giving +2 See http://review.coreboot.org/669 for details. -gerrit

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coreboot February 2012