coreboot February 2012

coreboot@coreboot.org

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348 discussions

New patch to review for coreboot: 5326f5c gitconfig: Add lint-stable as pre-commit hook
by Patrick Georgi 25 Feb '12

25 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/682 -gerrit commit 5326f5c7e6a9d56bc0f030c81651050d6d280150 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 25 19:52:45 2012 +0100 gitconfig: Add lint-stable as pre-commit hook When configuring the tree with "make gitconfig", a pre-commit hook is installed that runs the stable lint tests. If any of these fail, the log is visible (on stdout) and the commit is aborted. Change-Id: Ie2a26e87f466c63b24db8dca8827057a18ac7f3e Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 2 +- util/gitconfig/pre-commit | 2 ++ 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 0f040e9..2f61a45 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -239,7 +239,7 @@ lint lint-stable: rm -f $$LINTLOG gitconfig: - if ! [ -x .git/hooks/commit-msg ]; then cp util/gitconfig/commit-msg .git/hooks/commit-msg; chmod +x .git/hooks/commit-msg; fi + for hook in commit-msg pre-commit; do if ! [ -x .git/hooks/$$hook ]; then cp util/gitconfig/$$hook .git/hooks/$$hook; chmod +x .git/hooks/$$hook; fi; done (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) crossgcc: clean-for-update diff --git a/util/gitconfig/pre-commit b/util/gitconfig/pre-commit new file mode 100755 index 0000000..8ab3e56 --- /dev/null +++ b/util/gitconfig/pre-commit @@ -0,0 +1,2 @@ +#!/bin/sh +exec make lint-stable

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New patch to review for coreboot: c0f82a7 lint: create two classes of tests, stable and dev
by Patrick Georgi 25 Feb '12

25 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/681 -gerrit commit c0f82a75b480ad90d9b4eff48a1ebf08ef592aec Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 25 19:42:59 2012 +0100 lint: create two classes of tests, stable and dev We have tests that pass (and should be enforced soonish) and those that don't pass yet (and thus shouldn't break the build). The plan is simple: As soon as a test passes, it's marked stable so things remain that way. "make lint" runs all tests, "make lint-stable" runs only those that shouldn't fail. Change-Id: Iaa85d71141606d9756e29b37c7a34c2a15e573ac Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 6 +- util/lint/lint-002-build-dir-handling | 63 -------------------------- util/lint/lint-003-whitespace | 39 ---------------- util/lint/lint-stable-002-build-dir-handling | 63 ++++++++++++++++++++++++++ util/lint/lint-stable-003-whitespace | 39 ++++++++++++++++ 5 files changed, 105 insertions(+), 105 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index e12cc92..0f040e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -34,7 +34,7 @@ coreboot: $(obj)/coreboot.rom ####################################################################### # our phony targets -PHONY+= clean-abuild coreboot +PHONY+= clean-abuild coreboot lint lint-stable ####################################################################### # root source directories of coreboot @@ -218,9 +218,9 @@ printcrt0s: update: dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF -lint: +lint lint-stable: FAILED=0; LINTLOG=`mktemp`; \ - for script in util/lint/lint-*; do \ + for script in util/lint/$@-*; do \ echo; echo `basename $$script`; \ grep "^# DESCR:" $$script | sed "s,.*DESCR: *,," ; \ echo ========; \ diff --git a/util/lint/lint-002-build-dir-handling b/util/lint/lint-002-build-dir-handling deleted file mode 100755 index c4f57d6..0000000 --- a/util/lint/lint-002-build-dir-handling +++ /dev/null @@ -1,63 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Patrick Georgi <patrick(a)georgi-clan.de> -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# DESCR: Check that build directories can be chosen freely - -# $1: command to test for GNU make -search_make() { -if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi -} - -# if $1 and $2 differ, exit with failure -compare_output() { -if ! [ "$1" = "$2" ]; then - echo \'$1\' should be \'$2\' - exit 1 -fi -} - -# $1: object directory -run_printall() { -$MAKE CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s, ,\n,g" -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," -} - -# find GNU make -search_make make -search_make gmake -search_make gnumake - -if [ "$MAKE" = "" ]; then - echo Could not identify GNU make - exit 1 -fi - -# prepare a config to use -TMPCONFIG=`mktemp .tmpconfig.XXXXXX` -rm -f $TMPCONFIG -$MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null - -# look up parent directory -PARENTDIR=`dirname $PWD` - -compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" -compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" -compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" -compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" - -rm -f $TMPCONFIG - diff --git a/util/lint/lint-003-whitespace b/util/lint/lint-003-whitespace deleted file mode 100755 index fe305bf..0000000 --- a/util/lint/lint-003-whitespace +++ /dev/null @@ -1,39 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright (C) 2011 Patrick Georgi <patrick(a)georgi-clan.de> -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -# -# DESCR: Check for superfluous whitespace in the tree - -LC_ALL=C export LC_ALL -find src util -name .svn -type d -prune -o \ - -name .git -type d -prune -o \ - -name README -prune -o \ - -name LICENSE -prune -o \ - -name TODO -prune -o \ - -name COPYING -prune -o \ - -name \*.txt -prune -o \ - -name microcode-\*.h -prune -o \ - -name \*.?_shipped -prune -o \ - -name \*.[18] -prune -o \ - -name kconfig -type d -prune -o \ - -name romcc -type d -prune -o \ - -name crossgcc -type d -prune -o \ - -name vendorcode -type d -prune -o \ - -type f -exec \ - grep -l "[[:space:]][[:space:]]*$" {} + | \ - sed -e "s,^.*$,File & has lines ending with whitespace.," - diff --git a/util/lint/lint-stable-002-build-dir-handling b/util/lint/lint-stable-002-build-dir-handling new file mode 100755 index 0000000..c4f57d6 --- /dev/null +++ b/util/lint/lint-stable-002-build-dir-handling @@ -0,0 +1,63 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Patrick Georgi <patrick(a)georgi-clan.de> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# DESCR: Check that build directories can be chosen freely + +# $1: command to test for GNU make +search_make() { +if [ -n "`$1 --version 2>&1 |grep GNU`" ]; then MAKE=$1; fi +} + +# if $1 and $2 differ, exit with failure +compare_output() { +if ! [ "$1" = "$2" ]; then + echo \'$1\' should be \'$2\' + exit 1 +fi +} + +# $1: object directory +run_printall() { +$MAKE CONFIG_CCACHE=n CONFIG_SCANBUILD_ENABLE=n NOMKDIR=1 DOTCONFIG=$TMPCONFIG obj=$1 printall |sed -e "s,^ *,," -e "s, ,\n,g" -e "s,^ramstage-objs:=,," -e "s,mainboard/[^/]*/[^/]*/,.../," |grep "/static.*\.[co]" |sort |tr '\012\015' ' ' |sed -e "s, *, ,g" -e "s, *$,," +} + +# find GNU make +search_make make +search_make gmake +search_make gnumake + +if [ "$MAKE" = "" ]; then + echo Could not identify GNU make + exit 1 +fi + +# prepare a config to use +TMPCONFIG=`mktemp .tmpconfig.XXXXXX` +rm -f $TMPCONFIG +$MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null + +# look up parent directory +PARENTDIR=`dirname $PWD` + +compare_output "`run_printall build`" "build/.../static.c build/.../static.ramstage.o" +compare_output "`run_printall ../obj`" "$PARENTDIR/obj/.../static.c $PARENTDIR/obj/.../static.ramstage.o" +compare_output "`run_printall /tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" +compare_output "`run_printall /../tmp`" "/tmp/.../static.c /tmp/.../static.ramstage.o" + +rm -f $TMPCONFIG + diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace new file mode 100755 index 0000000..fe305bf --- /dev/null +++ b/util/lint/lint-stable-003-whitespace @@ -0,0 +1,39 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Patrick Georgi <patrick(a)georgi-clan.de> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# DESCR: Check for superfluous whitespace in the tree + +LC_ALL=C export LC_ALL +find src util -name .svn -type d -prune -o \ + -name .git -type d -prune -o \ + -name README -prune -o \ + -name LICENSE -prune -o \ + -name TODO -prune -o \ + -name COPYING -prune -o \ + -name \*.txt -prune -o \ + -name microcode-\*.h -prune -o \ + -name \*.?_shipped -prune -o \ + -name \*.[18] -prune -o \ + -name kconfig -type d -prune -o \ + -name romcc -type d -prune -o \ + -name crossgcc -type d -prune -o \ + -name vendorcode -type d -prune -o \ + -type f -exec \ + grep -l "[[:space:]][[:space:]]*$" {} + | \ + sed -e "s,^.*$,File & has lines ending with whitespace.," +

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New patch to review for coreboot: a4cc213 Fix lint test for build directories
by Patrick Georgi 25 Feb '12

25 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/680 -gerrit commit a4cc21352ce28579466fe338dc4ee6ef3b4711e9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Feb 25 15:33:43 2012 +0100 Fix lint test for build directories config files are rename()d, which fails across filesystem borders. So force temporary config files in current directory. Change-Id: I583c2ab9a822a6f99f838778aa17ffd2d47eaed1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/lint/lint-002-build-dir-handling | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/util/lint/lint-002-build-dir-handling b/util/lint/lint-002-build-dir-handling index f10db17..c4f57d6 100755 --- a/util/lint/lint-002-build-dir-handling +++ b/util/lint/lint-002-build-dir-handling @@ -47,7 +47,7 @@ if [ "$MAKE" = "" ]; then fi # prepare a config to use -TMPCONFIG=`mktemp` +TMPCONFIG=`mktemp .tmpconfig.XXXXXX` rm -f $TMPCONFIG $MAKE NOMKDIR=1 DOTCONFIG=$TMPCONFIG allyesconfig >/dev/null

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New patch to review for coreboot: b2b6c53 AMD southbridge: remove sp5100
by Kyösti Mälkki 25 Feb '12

25 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/679 -gerrit commit b2b6c535a1e8cdd5d39fc1a13267b14ac1fd2edb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 23 18:42:55 2012 +0200 AMD southbridge: remove sp5100 Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 +- src/mainboard/supermicro/h8scm_fam10/devicetree.cb | 4 +- src/southbridge/amd/Makefile.inc | 1 - src/southbridge/amd/sb700/Kconfig | 19 +++++++---- src/southbridge/amd/sb700/early_setup.c | 8 ++-- src/southbridge/amd/sb700/lpc.c | 2 +- src/southbridge/amd/sb700/sata.c | 5 +-- src/southbridge/amd/sb700/sb700.c | 4 +- src/southbridge/amd/sp5100/chip.h | 33 -------------------- 9 files changed, 24 insertions(+), 56 deletions(-) diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index cbd3119..844763e 100755 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -8,14 +8,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 select SUPERIO_WINBOND_W83627HF select SUPERIO_NUVOTON_WPCM450 select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index c6ccecb..9aa4406 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -36,7 +36,7 @@ chip northbridge/amd/amdfam10/root_complex register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 register "port_enable" = "0x1ffc" end - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB @@ -92,7 +92,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sp5100 + end #southbridge/amd/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc index 54245f2..65e4729 100644 --- a/src/southbridge/amd/Makefile.inc +++ b/src/southbridge/amd/Makefile.inc @@ -8,7 +8,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650 -subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SP5100) += sb700 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536 diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 05f7d09..924e2df 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -19,29 +19,34 @@ config SOUTHBRIDGE_AMD_SB700 bool + +if SOUTHBRIDGE_AMD_SB700 + +config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET -config SOUTHBRIDGE_AMD_SP5100 +# Set for southbridge SP5100 which also uses SB700 driver +config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool - select IOAPIC - select HAVE_USBDEBUG + default n config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/amd/sb700/bootblock.c" - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT bool default n - depends on (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) config EHCI_BAR hex - default 0xfef00000 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0xe0 if (SOUTHBRIDGE_AMD_SB700 || SOUTHBRIDGE_AMD_SP5100) + default 0xe0 + +endif # SOUTHBRIDGE_AMD_SB700 diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 1f46da2..2dc84d8 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -154,7 +154,7 @@ void sb7xx_51xx_lpc_init(void) reg32 |= 1 << 20; pci_write_config32(dev, 0x64, reg32); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 post_code(0x66); dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */ reg8 = pci_read_config8(dev, 0xBB); @@ -168,7 +168,7 @@ void sb7xx_51xx_lpc_init(void) // XXX Serial port decode on LPC is hardcoded to 0x3f8 reg8 = pci_read_config8(dev, 0x44); reg8 |= 1 << 6; -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 #if CONFIG_TTYS0_BASE == 0x2f8 reg8 |= 1 << 7; #endif @@ -358,7 +358,7 @@ static void sb700_devices_por_init(void) { device_t dev; u8 byte; -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 u32 dword; #endif @@ -494,7 +494,7 @@ static void sb700_devices_por_init(void) /* Enable PCIB_DUAL_EN_UP will fix potential problem with PCI cards. */ pci_write_config8(dev, 0x50, 0x01); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* SP5100 default SATA mode is RAID5 MODE */ dev = pci_locate_device(PCI_ID(0x1002, 0x4393), 0); /* Set SATA Operation Mode, Set to IDE mode */ diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 3e596c2..5dd7d69 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) /* Disable LPC MSI Capability */ byte = pci_read_config8(dev, 0x78); byte &= ~(1 << 1); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* Disable FlowContrl, Always service the request from Host * whenever there is a request from Host pending */ diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 58b72ad..bdbb08a 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -86,9 +86,6 @@ static void sata_init(struct device *dev) u16 sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; int i, j; - struct southbridge_ati_sb700_config *conf; - conf = dev->chip_info; - device_t sm_dev; /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); @@ -189,7 +186,7 @@ static void sata_init(struct device *dev) byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 /* Master Latency Timer */ pci_write_config32(dev, 0xC, 0x00004000); #endif diff --git a/src/southbridge/amd/sb700/sb700.c b/src/southbridge/amd/sb700/sb700.c index 845c82c..304bd07 100644 --- a/src/southbridge/amd/sb700/sb700.c +++ b/src/southbridge/amd/sb700/sb700.c @@ -226,8 +226,8 @@ void sb7xx_51xx_enable(device_t dev) } } -#if CONFIG_SOUTHBRIDGE_AMD_SP5100 -struct chip_operations southbridge_amd_sp5100_ops = { +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 +struct chip_operations southbridge_amd_sb700_ops = { CHIP_NAME("ATI SP5100") .enable_dev = sb7xx_51xx_enable, }; diff --git a/src/southbridge/amd/sp5100/chip.h b/src/southbridge/amd/sp5100/chip.h deleted file mode 100644 index 569e511..0000000 --- a/src/southbridge/amd/sp5100/chip.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SP5100_CHIP_H -#define SP5100_CHIP_H - -struct southbridge_amd_sp5100_config -{ - u32 ide0_enable : 1; - u32 sata0_enable : 1; - u32 boot_switch_sata_ide : 1; - u32 hda_viddid; -}; -struct chip_operations; -extern struct chip_operations southbridge_amd_sp5100_ops; - -#endif /* SP5100_CHIP_H */

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Re: [coreboot] Asus M2V-MX memory init
by Rudolf Marek 24 Feb '12

24 Feb '12

Hi, I think something wrong went with PCI/memory mapping. It looks somehow a hole for PCI is not created. Try setting CONFIG_HW_MEM_HOLE_SIZEK. it should create 0-3GB ram and 1GB hole by default. Also I did not check if VIA chipset will work with memory above 4GB (in fact never owned so much memory :) maybe correct top of memory needs to be present for the chipset. The option above will configure the memory hole which will allow the PCI devices to exists and rest of memory will be remapped above. Again, never played with that but it might work. Thanks Rudolf

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Patch set updated for coreboot: 3bbce45 Update xcompile to search for x86_64 toolchain.
by Marc Jones 24 Feb '12

24 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673 -gerrit commit 3bbce4576d5a61da1831d0ca749ffcf78d357697 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/xcompile/xcompile | 17 +++++++++++------ 1 files changed, 11 insertions(+), 6 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4926394..3930460 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -36,14 +36,19 @@ done GCCPREFIX=invalid XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} -echo '#XGCCPATH='${XGCCPATH} +echo '# XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE -# This should be a loop over all supported architectures -TARCH=i386 +# This loops over all supported architectures in TARCH +TARCH=('i386' 'x86_64') TWIDTH=32 -for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do +for search_for in "${TARCH[@]}"; do + TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-) +done +echo '# TARCH_SEARCH='${TARCH_SEARCH[@]} + +for gccprefixes in "${TARCH_SEARCH[@]}" ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi @@ -63,8 +68,8 @@ for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS=--32 - CFLAGS="-m32 " - LDFLAGS="-b elf32-i386" + CFLAGS="-m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 " + LDFLAGS="-b elf32-i386 -melf_i386" break fi fi

1 0

Patch merged into coreboot/master: aafcf93 Ati video: Apply un-written naming rules
by gerrit＠coreboot.org 24 Feb '12

24 Feb '12

the following patch was just integrated into master: commit aafcf93e1a8d5b51ccdf4e7f4bd62de5a5c81f15 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 23 13:54:23 2012 +0200 Ati video: Apply un-written naming rules Rename Kconfig to match directory name. Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Feb 24 11:21:47 2012, giving +2 See http://review.coreboot.org/678 for details. -gerrit

1 0

Re: [coreboot] Asus M2V-MX memory init
by David Hillman 23 Feb '12

23 Feb '12

Thanks for the quick reply. My experience with Coreboot is very limited; I started playing with the code a few weeks ago. As far as getting this particular board going, I started with the code from the Asus M2V-MX_SE (different SuperIO, mainly). Then, I changed info in devicetree.cb, romstage.c, mainboard.c and Kconfig files as needed. "what is 12.0?" It is listed as VIA LAN in devicetree.cb. I turned it off because M2V-MX has separate Realtek chip. I don't know why it is still there. What do fn_ctrl_lo and fn_ctrl_hi in devicetree.cb do? I don't really understand them, so I left them alone. It seems devicetree.cb needs to be looked at. I will investigate more to get a better understanding. coreboot-request(a)coreboot.org wrote: Send coreboot mailing list submissions to coreboot(a)coreboot.org To subscribe or unsubscribe via the World Wide Web, visit http://www.coreboot.org/mailman/listinfo/coreboot or, via email, send a message with subject or body 'help' to coreboot-request(a)coreboot.org You can reach the person managing the list at coreboot-owner(a)coreboot.org When replying, please edit your Subject line so it is more specific than "Re: Contents of coreboot digest..." Today's Topics: 1. Re: Asus M2V-MX memory init (Peter Stuge) 2. Re: flash-chip (and compatibles) (Oliver Schinagl) 3. Patch merged into coreboot/master: 3d3abb2 Remove old AMD fam10 fixme comment (gerrit(a)coreboot.org) 4. Re: Coreboot support for ASUS M5 A99X EVO ? (Bernhard Urban) ---------------------------------------------------------------------- Message: 1 Date: Wed, 22 Feb 2012 04:40:06 +0100 From: Peter Stuge <peter(a)stuge.se> To: coreboot(a)coreboot.org Subject: Re: [coreboot] Asus M2V-MX memory init Message-ID: <20120222034006.29372.qmail(a)stuge.se> Content-Type: text/plain; charset=us-ascii David Hillman wrote: > It looks like I am missing something to properly initialize memory > to get correct SPD info. Maybe SMBUS isn't working properly? I think SMBUS is OK and memory init too. Here's the diff between your two logs with some comments, but there may be more relevant stuff than what I see. Next time when posting logs please make sure that they do not wrap. One good way is to send them as attachments, under all circumstances with text/plain mime type. --- m2v_mx-2g 2012-02-22 04:13:21.309138502 +0100 +++ m2v_mx-4g 2012-02-22 04:13:02.663139149 +0100 @@ -1,4 +1,4 @@ -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings @@ -47,16 +47,21 @@ sdram_set_spd_registers: paramx :000ceee8 Device error Device error -Device error +Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved -RAM end at 0x00200000 kB +RAM end at 0x00400000 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB +Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB +Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB +Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB +Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB +Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done @@ -68,41 +73,45 @@ TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 +TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 - CTLRMaxDelay=43 + CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 -Writing 17161515 of size 4 to nvram pos: 4 +Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 -Writing 17171918 of size 4 to nvram pos: 17 -Writing 17191718 of size 4 to nvram pos: 21 +Writing 18171819 of size 4 to nvram pos: 17 +Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 -Writing 33 of size 1 to nvram pos: 26 +Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 -Writing 111222 of size 4 to nvram pos: 30 -Writing 0 of size 4 to nvram pos: 34 -Writing 0 of size 4 to nvram pos: 38 -Writing 0 of size 1 to nvram pos: 42 -Writing 0 of size 4 to nvram pos: 43 -Writing 2f2f2f2f of size 4 to nvram pos: 47 -Writing 2f2f2f2f of size 4 to nvram pos: 51 -Writing 0 of size 1 to nvram pos: 55 -Writing 43 of size 1 to nvram pos: 56 +Writing 113222 of size 4 to nvram pos: 30 +Writing 15141615 of size 4 to nvram pos: 34 +Writing 15141515 of size 4 to nvram pos: 38 +Writing 15 of size 1 to nvram pos: 42 +Writing 202520 of size 4 to nvram pos: 43 +Writing 17191818 of size 4 to nvram pos: 47 +Writing 18191716 of size 4 to nvram pos: 51 +Writing 16 of size 1 to nvram pos: 55 +Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 -Writing 741080ab of size 4 to nvram pos: 60 -DQS Training:tsc[00]=000000005eac6acb -DQS Training:tsc[01]=000000006087914d -DQS Training:tsc[02]=0000000060879156 -DQS Training:tsc[03]=00000000df309c2e -DQS Training:tsc[04]=00000000f2a194b3 +Writing 7410809b of size 4 to nvram pos: 60 +DQS Training:tsc[00]=000000008cbdd63c +DQS Training:tsc[01]=000000008f476e2e +DQS Training:tsc[02]=000000008f476e37 +DQS Training:tsc[03]=000000015b152149 +DQS Training:tsc[04]=000000016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a @@ -121,7 +130,7 @@ 0x100000 Stage: done loading. Jumping to image. -coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... +coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 @@ -147,7 +156,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 -PCI: 00:12.0: enabled 0 +PCI: 00:12.0: enabled 1 Why is 12.0 enabled with 4G? What is 12.0? PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -177,7 +186,7 @@ PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 - PCI: 00:12.0: enabled 0 + PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 @@ -265,7 +274,7 @@ PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops -K8M890: UMA base is 7e000000 size is 32 (MB) +K8M890: UMA base is fa000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -275,7 +284,7 @@ 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -80: ff ff ff 30 00 80 19 00 80 00 00 00 00 00 00 00 +80: ff ff ff 30 00 fc 19 00 fc 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -363,7 +372,7 @@ d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 -PCI: 00:03.0 PCIe link up after 15000 us +PCI: 00:03.0 PCIe link up after 15100 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 @@ -399,6 +408,7 @@ PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled +PCI: Static device PCI: 00:12.0 not found, disabling it. Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 @@ -978,10 +988,10 @@ PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 -node 0 : uma_memory_base/1024=0x001f8000, mmio_basek=0x00300000, -basek=0x00000300, limitk=0x00200000 -node 0: UMA memory starts below mmio_basek -0: mmio_basek=00300000, basek=00000300, limitk=00200000 +node 0 : uma_memory_base/1024=0x003e8000, mmio_basek=0x00300000, +basek=0x00000300, limitk=0x00400000 + split: 1088K table at =f9ef0000 +0: mmio_basek=00300000, basek=00300000, limitk=00400000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link @@ -1114,9 +1124,11 @@ limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 - PCI_DOMAIN: 0000 resource base c0000 size 7df40000 align 0 gran 0 limit 0 + PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 - PCI_DOMAIN: 0000 resource base 7e000000 size 2000000 align 0 gran 0 limit + PCI_DOMAIN: 0000 resource base c0000000 size 3fffe000000 align 0 gran 0 limit 0 flags e0004200 index 30 + PCI_DOMAIN: 0000 resource base fa000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 The size for the c0000000 domain is crazy. This is worth looking into further. I did some manual line unwrapping above. The email had extra line endings damaging the log messages. It will be easier for you if you fix that. PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff @@ -1368,7 +1380,9 @@ DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff -Setting variable MTRR 1, base: 2016MB, range: 32MB, type UC +Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB +ADDRESS_MASK_HIGH=0xff +Setting variable MTRR 2, base: 4000MB, range: 32MB, type UC Find out why the 32 MB framebuffer ends at TOM on 2GB, but ends at TOM-64MB on 4GB, what the top 64MB is for. Hopefully PCI resources but 64MB is unexpectedly small for that. Investigate. ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's @@ -1493,7 +1507,7 @@ 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 -90: 00 06 19 88 a0 cc 00 00 00 3a 00 00 00 00 00 00 +90: 00 04 99 88 a0 cc 00 02 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -1506,7 +1520,7 @@ 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 -50: 00 03 33 03 00 04 01 80 08 00 01 80 00 00 00 00 +50: 00 03 33 03 00 04 01 fc 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 @@ -1605,14 +1619,14 @@ PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 -Initializing CBMEM area to 0x7def0000 (1114112 bytes) -Adding CBMEM entry as no. 1 -Moving GDT to 7def0200...ok -High Tables Base is 7def0000. -Adding CBMEM entry as no. 2 -ACPI: Writing ACPI tables at 7def0400... +Initializing CBMEM area to 0xf9ef0000 (1114112 bytes) +ERROR: CBMEM was not initialized yet. +Error: Could not relocate GDT. +High Tables Base is f9ef0000. +ERROR: CBMEM was not initialized yet. This is very bad. Investigate. The CBMEM code should be easy to follow. +ACPI: Writing ACPI tables at f0000... ACPI: * FACS -ACPI: * DSDT @ 7def0540 Length ba5 +ACPI: * DSDT @ 000f0140 Length ba5 So with 2GB ACPI tables are written high, with 4GB because CBMEM fails they end up in F-segment. ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET @@ -1626,7 +1640,9 @@ set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 -set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001f7d00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00300000, sizek=ffff8000 At least the last one is bogus. ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 @@ -1645,9 +1661,8 @@ 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. -ACPI tables: 4677 bytes. -Adding CBMEM entry as no. 3 -smbios_write_tables: 7defb800 +ERROR: CBMEM was not initialized yet. +smbios_write_tables: 000f1400 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) @@ -1697,36 +1712,37 @@ PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () -SMBIOS tables: 277 bytes. -Adding CBMEM entry as no. 4 +SMBIOS size 277 bytes +ERROR: CBMEM was not initialized yet. Writing high table forward entry at 0x00000500 -Wrote coreboot table at: 00000500 - 00000518 checksum c1ee +Wrote coreboot table at: 00000500 - 00000518 checksum eaaf New low_table_end: 0x00000518 -Now going to write high coreboot table at 0x7defc000 -rom_table_end = 0x7defc000 +Now going to write high coreboot table at 0x000f1520 +rom_table_end = 0x000f1520 Adjust low_table_end from 0x00000518 to 0x00001000 -Adjust rom_table_end from 0x7defc000 to 0x7df00000 +Adjust rom_table_end from 0x000f1520 to 0x00100000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM - 2. 00000000000c0000-000000007deeffff: RAM - 3. 000000007def0000-000000007dffffff: CONFIGURATION TABLES - 4. 000000007e000000-000000007fffffff: RESERVED - 5. 00000000e0000000-00000000efffffff: RESERVED - 6. 00000000fec00000-00000000fec000ff: RESERVED - 7. 00000000fecc0000-00000000fecc00ff: RESERVED - 8. 00000000ff000000-00000000ffffffff: RESERVED -Wrote coreboot table at: 7defc000 - 7defc214 checksum 336b -coreboot table: 532 bytes. -Adding CBMEM entry as no. 5 + 2. 00000000000c0000-00000000000effff: RAM + 3. 00000000000f0000-00000000000fffff: CONFIGURATION TABLES + 4. 0000000000100000-00000000bfffffff: RAM + 5. 00000000c0000000-00000000dfffffff: RAM + 6. 00000000e0000000-00000000efffffff: RESERVED + 7. 00000000f0000000-00000000f9eeffff: RAM + 8. 00000000f9ef0000-00000000f9ffffff: CONFIGURATION TABLES + 9. 00000000fa000000-00000000fbffffff: RESERVED +10. 00000000fc000000-00000000febfffff: RAM +11. 00000000fec00000-00000000fec000ff: RESERVED +12. 00000000fec00100-00000000fecbffff: RAM +13. 00000000fecc0000-00000000fecc00ff: RESERVED +14. 00000000fecc0100-00000000feffffff: RAM +15. 00000000ff000000-00000000ffffffff: RESERVED +16. 0000000100000000-00000400bdffffff: RAM Here, coreboot says that you have almost 4 TB of RAM. Investigate. +Wrote coreboot table at: 000f1520 - 000f17d4 checksum f32e +ERROR: CBMEM was not initialized yet. Multiboot Information structure has been written. - 0. FREE SPACE 7dffe000 00002000 - 1. GDT 7def0200 00000200 - 2. ACPI 7def0400 0000b400 - 3. SMBIOS 7defb800 00000800 - 4. COREBOOT 7defc000 00002000 - 5. ACPI RESUME7defe000 00100000 Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom @@ -1737,26 +1753,30 @@ Loading segment from rom address 0xfffad538 data (compression=1) - New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8aa - (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8aa + New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8ba + (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8ba Loading segment from rom address 0xfffad554 Entry Point 0x00000000 -Loading Segment: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: -0x000000000000c8aa -lb: [0x0000000000100000, 0x0000000000198000) -Post relocation: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: -0x000000000000c8aa -using LZMA -[ 0x000e6b54, 00100000, 0x00100000) <- fffad570 -dest 000e6b54, end 00100000, bouncebuffer 7ddc0000 -Loaded segments -Jumping to boot code at fc8e4 -entry = 0x000fc8e4 -lb_start = 0x00100000 -lb_size = 0x00098000 -adjust = 0x7dd58000 -buffer = 0x7ddc0000 - elf_boot_notes = 0x001270c8 -adjusted_boot_notes = 0x7de7f0c8 -Start bios (version 1.6.3-20120215_224505-debby) +No matching ram area found for range: + [0x00000000000e6b54, 0x0000000000100000) And finally instead of the "Start bios" message from SeaBIOS it's not possible to load the payload to it's address, because.. +Ram areas + [0x0000000000000000, 0x0000000000001000) Reserved + [0x0000000000001000, 0x00000000000a0000) RAM + [0x00000000000c0000, 0x00000000000f0000) RAM + [0x00000000000f0000, 0x0000000000100000) Reserved ..the F segment has been marked reserved, because this is where the ACPI tables were written to, because the highmem address was not available, because CBMEM failed to initialize. The error isn't really with hardware init I believe, but with calculation, generation and preparation of system description data for the payload and later the operating system. You need to find out why coreboot gets upset with 4G of memory. //Peter ------------------------------ Message: 2 Date: Wed, 22 Feb 2012 10:35:54 +0100 From: Oliver Schinagl <oliver(a)schinagl.nl> To: coreboot(a)coreboot.org Subject: Re: [coreboot] flash-chip (and compatibles) Message-ID: <4F44B6FA.8070509(a)schinagl.nl> Content-Type: text/plain; charset="iso-8859-1"; Format="flowed" Having trouble ordering from several webshops in Europe (The only want to send you parts if you order in huge quantities or if you are a company) I've found the following at digikey in the US. http://search.digikey.com/nl/en/products/SST25VF032B-80-4I-S2AF/SST25VF032B… http://search.digikey.com/nl/en/products/W25Q64FVSSIG/W25Q64FVSSIG-ND/28159… I know they are 8-SOIC but have ordered (and received) 8-SOIC -> 8-DIP pcb's so can easily convert between the sockets. I guess these should work just fine? On 16-02-12 02:44, Peter Stuge wrote: > Oliver Schinagl wrote: >> I was pointed to this one: A25L032-F >> http://nl.farnell.com/amic/a25l032-f/memory-flash-spi-32m-8dip/dp/1907085 >> >> (There's also a Q version, which I don't think is what I'd want). > Correct. Q is a WSON package which does not fit at all. Make sure you > buy farnell nr. 1907085 and nothing else. A25L032-F is indeed the > accurate manufacturer's part number, if you order somewhere else. > > >> I haven't found a 64Mbit chip yet, so I hope I could use a linux >> kernel as payload using a 4MB one (the current 32Mbit) > Winbond W25Q64CV > > But Winbond's distributors AVNET and Digi-Key, > > http://www.winbond-usa.com/winbondcms/Application/member/Distributors.aspx?… > > only have SO-8 in stock, and you wanted DIP. You could look for > adapters, but then you must do some soldering. > > http://search.digikey.com/scripts/DkSearch/dksus.dll?site=us&lang=en&v=256&… > > AVNET only have SO-8 stock in Asia. You'll have to pay import fees > and tax. Digi-Keys f-ing website barfs some idiotic error at me > whenever I try to use it nowadays. > > > You can buy DIP from bios-repair.co.uk, but they only have the older > revision W25Q64BVAIG. For once they don't charge more than AVNET&co > in single quantity. > > http://bios-repair.co.uk/Products/EEPROM/SPI-SerialFlash-EEPROM.html > > Click Winbond, then there's W25Q64BVAIG 64Mb PDIP top left in the > product listing. > > > //Peter >

1 0

Dual SPI Flash
by Oliver Schinagl 23 Feb '12

23 Feb '12

Hi list, I noticed an intersting hack on the coreboot wiki: http://www.coreboot.org/Developer_Manual/Tools/Dual_Flash It lists a neat trick to double stack two spi flash modules to make testing/developping/flashing coreboot easier. However there's no schematic or other information available on how to actually build this setup. Could the author possibly supply this extra information? Since not even the resitor values or switch connection is documented. Thanks, Oliver

2 1

New patch to review for coreboot: aafcf93 Ati video: Apply un-written naming rules
by Kyösti Mälkki 23 Feb '12

23 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/678 -gerrit commit aafcf93e1a8d5b51ccdf4e7f4bd62de5a5c81f15 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 23 13:54:23 2012 +0200 Ati video: Apply un-written naming rules Rename Kconfig to match directory name. Change-Id: Idebc203bbc9a02599dfc3e65be021aa9e1b23d61 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/ati/ragexl/Kconfig | 2 +- src/drivers/ati/ragexl/Makefile.inc | 2 +- src/mainboard/intel/jarrell/Kconfig | 2 +- src/mainboard/iwill/dk8s2/Kconfig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/ati/ragexl/Kconfig b/src/drivers/ati/ragexl/Kconfig index 117aa66..86109b1 100644 --- a/src/drivers/ati/ragexl/Kconfig +++ b/src/drivers/ati/ragexl/Kconfig @@ -1,2 +1,2 @@ -config ATI_RAGE_XL +config DRIVERS_ATI_RAGEXL bool diff --git a/src/drivers/ati/ragexl/Makefile.inc b/src/drivers/ati/ragexl/Makefile.inc index 107885e..8b59597 100644 --- a/src/drivers/ati/ragexl/Makefile.inc +++ b/src/drivers/ati/ragexl/Makefile.inc @@ -1 +1 @@ -driver-$(CONFIG_ATI_RAGE_XL) += xlinit.c +driver-$(CONFIG_DRIVERS_ATI_RAGEXL) += xlinit.c diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig index 282ec4b..a3c34f4 100644 --- a/src/mainboard/intel/jarrell/Kconfig +++ b/src/mainboard/intel/jarrell/Kconfig @@ -15,7 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select UDELAY_TSC select USE_WATCHDOG_ON_BOOT - select ATI_RAGE_XL + select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_2048 config MAINBOARD_DIR diff --git a/src/mainboard/iwill/dk8s2/Kconfig b/src/mainboard/iwill/dk8s2/Kconfig index f9f1b57..1c35cb2 100644 --- a/src/mainboard/iwill/dk8s2/Kconfig +++ b/src/mainboard/iwill/dk8s2/Kconfig @@ -14,7 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT - select ATI_RAGE_XL + select DRIVERS_ATI_RAGEXL select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT

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coreboot February 2012