coreboot February 2012

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New patch to review for coreboot: 448996a Rename vendor identifiers in Kconfig
by Patrick Georgi 22 Feb '12

22 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/674 -gerrit commit 448996ad975da9f3d620a2e4feb1373d1c67dfd9 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Tue Jan 10 18:45:34 2012 +0100 Rename vendor identifiers in Kconfig Board identifiers use them without underscore, too. Unify that. Change-Id: I146384ef6dbe601ad131dada8224f43e6c18433d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/Kconfig | 4 ++-- src/mainboard/artecgroup/Kconfig | 4 ++-- src/mainboard/digitallogic/Kconfig | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a73f445 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -16,7 +16,7 @@ config VENDOR_AMD bool "AMD" config VENDOR_ARIMA bool "Arima" -config VENDOR_ARTEC_GROUP +config VENDOR_ARTECGROUP bool "Artec Group" config VENDOR_ASI bool "ASI" @@ -42,7 +42,7 @@ config VENDOR_COMPAQ bool "Compaq" config VENDOR_DELL bool "Dell" -config VENDOR_DIGITAL_LOGIC +config VENDOR_DIGITALLOGIC bool "DIGITAL-LOGIC" config VENDOR_EAGLELION bool "EagleLion" diff --git a/src/mainboard/artecgroup/Kconfig b/src/mainboard/artecgroup/Kconfig index 5e63f09..b6923ae 100644 --- a/src/mainboard/artecgroup/Kconfig +++ b/src/mainboard/artecgroup/Kconfig @@ -1,4 +1,4 @@ -if VENDOR_ARTEC_GROUP +if VENDOR_ARTECGROUP choice prompt "Mainboard model" @@ -14,4 +14,4 @@ config MAINBOARD_VENDOR string default "Artec Group" -endif # VENDOR_ARTEC_GROUP +endif # VENDOR_ARTECGROUP diff --git a/src/mainboard/digitallogic/Kconfig b/src/mainboard/digitallogic/Kconfig index a98aa1d..9f490b0 100644 --- a/src/mainboard/digitallogic/Kconfig +++ b/src/mainboard/digitallogic/Kconfig @@ -1,4 +1,4 @@ -if VENDOR_DIGITAL_LOGIC +if VENDOR_DIGITALLOGIC choice prompt "Mainboard model" @@ -20,4 +20,4 @@ config MAINBOARD_VENDOR string default "DIGITAL-LOGIC" -endif # VENDOR_DIGITAL_LOGIC +endif # VENDOR_DIGITALLOGIC

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Patch set updated for coreboot: 7ba552e ACPI: More ../../.. removal
by Patrick Georgi 22 Feb '12

22 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/649 -gerrit commit 7ba552ebc7c8b7804741f918e0e80f836454e097 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:16:14 2012 +0100 ACPI: More ../../.. removal CPP is ran with src/ as part of its search path, so using <northbridge/...> and the like is safe. Change-Id: I644d60190ac92ef284d5f0b4acf44f7db3c788ee Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/advansus/a785e-i/dsdt.asl | 4 ++-- src/mainboard/amd/bimini_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/dbm690t/dsdt.asl | 4 ++-- src/mainboard/amd/inagua/dsdt.asl | 4 ++-- src/mainboard/amd/mahogany/dsdt.asl | 4 ++-- src/mainboard/amd/mahogany_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/persimmon/dsdt.asl | 4 ++-- src/mainboard/amd/pistachio/dsdt.asl | 4 ++-- src/mainboard/amd/south_station/dsdt.asl | 4 ++-- src/mainboard/amd/tilapia_fam10/dsdt.asl | 4 ++-- src/mainboard/amd/torpedo/dsdt.asl | 4 ++-- src/mainboard/amd/union_station/dsdt.asl | 4 ++-- src/mainboard/asrock/939a785gmh/dsdt.asl | 4 ++-- src/mainboard/asrock/e350m1/dsdt.asl | 4 ++-- src/mainboard/asus/m4a78-em/dsdt.asl | 4 ++-- src/mainboard/asus/m4a785-m/dsdt.asl | 4 ++-- src/mainboard/asus/m4a785t-m/dsdt.asl | 4 ++-- src/mainboard/asus/m5a88-v/dsdt.asl | 4 ++-- src/mainboard/avalue/eax-785e/dsdt.asl | 4 ++-- src/mainboard/getac/p470/dsdt.asl | 8 ++++---- src/mainboard/gigabyte/ma785gmt/dsdt.asl | 4 ++-- src/mainboard/gigabyte/ma78gm/dsdt.asl | 4 ++-- src/mainboard/ibase/mb899/dsdt.asl | 8 ++++---- src/mainboard/iei/kino-780am2-fam10/dsdt.asl | 4 ++-- src/mainboard/intel/d945gclf/dsdt.asl | 8 ++++---- src/mainboard/iwave/iWRainbowG6/dsdt.asl | 8 ++++---- src/mainboard/jetway/pa78vm5/dsdt.asl | 4 ++-- src/mainboard/kontron/986lcd-m/dsdt.asl | 8 ++++---- src/mainboard/kontron/kt690/dsdt.asl | 4 ++-- src/mainboard/lenovo/t60/dsdt.asl | 8 ++++---- src/mainboard/lenovo/x60/dsdt.asl | 8 ++++---- src/mainboard/msi/ms9652_fam10/dsdt.asl | 2 +- src/mainboard/roda/rk886ex/dsdt.asl | 8 ++++---- src/mainboard/supermicro/h8qgi/dsdt.asl | 4 ++-- src/mainboard/supermicro/h8scm_fam10/dsdt.asl | 4 ++-- src/mainboard/technexion/tim5690/dsdt.asl | 4 ++-- src/mainboard/technexion/tim8690/dsdt.asl | 4 ++-- 37 files changed, 89 insertions(+), 89 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/dsdt.asl b/src/mainboard/advansus/a785e-i/dsdt.asl index 78d3220..52ca3b9 100644 --- a/src/mainboard/advansus/a785e-i/dsdt.asl +++ b/src/mainboard/advansus/a785e-i/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/bimini_fam10/dsdt.asl b/src/mainboard/amd/bimini_fam10/dsdt.asl index 3ff6dab..e54723c 100644 --- a/src/mainboard/amd/bimini_fam10/dsdt.asl +++ b/src/mainboard/amd/bimini_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/dbm690t/dsdt.asl b/src/mainboard/amd/dbm690t/dsdt.asl index 1b24e18..2b1aab8 100644 --- a/src/mainboard/amd/dbm690t/dsdt.asl +++ b/src/mainboard/amd/dbm690t/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/inagua/dsdt.asl b/src/mainboard/amd/inagua/dsdt.asl index 4a61328..361adbb 100644 --- a/src/mainboard/amd/inagua/dsdt.asl +++ b/src/mainboard/amd/inagua/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/mahogany/dsdt.asl b/src/mainboard/amd/mahogany/dsdt.asl index 33c4620..4920e2f 100644 --- a/src/mainboard/amd/mahogany/dsdt.asl +++ b/src/mainboard/amd/mahogany/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1120,7 +1120,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/mahogany_fam10/dsdt.asl b/src/mainboard/amd/mahogany_fam10/dsdt.asl index 8bba547..b7e2a4a 100644 --- a/src/mainboard/amd/mahogany_fam10/dsdt.asl +++ b/src/mainboard/amd/mahogany_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/persimmon/dsdt.asl b/src/mainboard/amd/persimmon/dsdt.asl index c7ceb02..b480c33 100644 --- a/src/mainboard/amd/persimmon/dsdt.asl +++ b/src/mainboard/amd/persimmon/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/pistachio/dsdt.asl b/src/mainboard/amd/pistachio/dsdt.asl index bd5f73e..045db08 100644 --- a/src/mainboard/amd/pistachio/dsdt.asl +++ b/src/mainboard/amd/pistachio/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1122,7 +1122,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/south_station/dsdt.asl b/src/mainboard/amd/south_station/dsdt.asl index c4b69bd..7f03a43 100644 --- a/src/mainboard/amd/south_station/dsdt.asl +++ b/src/mainboard/amd/south_station/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/tilapia_fam10/dsdt.asl b/src/mainboard/amd/tilapia_fam10/dsdt.asl index 93724e3..666cebe 100644 --- a/src/mainboard/amd/tilapia_fam10/dsdt.asl +++ b/src/mainboard/amd/tilapia_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/torpedo/dsdt.asl b/src/mainboard/amd/torpedo/dsdt.asl index bc812e4..a8a731d 100755 --- a/src/mainboard/amd/torpedo/dsdt.asl +++ b/src/mainboard/amd/torpedo/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -798,7 +798,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/amd/union_station/dsdt.asl b/src/mainboard/amd/union_station/dsdt.asl index 04952d3..5c8b661 100644 --- a/src/mainboard/amd/union_station/dsdt.asl +++ b/src/mainboard/amd/union_station/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asrock/939a785gmh/dsdt.asl b/src/mainboard/asrock/939a785gmh/dsdt.asl index 70fca4d..da4d06a 100644 --- a/src/mainboard/asrock/939a785gmh/dsdt.asl +++ b/src/mainboard/asrock/939a785gmh/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ #include "northbridge/amd/amdk8/util.asl" Name(HPBA, 0xFED00000) /* Base address of HPET table */ @@ -460,7 +460,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asrock/e350m1/dsdt.asl b/src/mainboard/asrock/e350m1/dsdt.asl index 8dc40d0..97533c1 100644 --- a/src/mainboard/asrock/e350m1/dsdt.asl +++ b/src/mainboard/asrock/e350m1/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/i386/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/i386/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1138,7 +1138,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a78-em/dsdt.asl b/src/mainboard/asus/m4a78-em/dsdt.asl index 7c28398..0d08d29 100644 --- a/src/mainboard/asus/m4a78-em/dsdt.asl +++ b/src/mainboard/asus/m4a78-em/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a785-m/dsdt.asl b/src/mainboard/asus/m4a785-m/dsdt.asl index 34ddd3a..7ea5672 100644 --- a/src/mainboard/asus/m4a785-m/dsdt.asl +++ b/src/mainboard/asus/m4a785-m/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m4a785t-m/dsdt.asl b/src/mainboard/asus/m4a785t-m/dsdt.asl index fe2bfa5..9e6ce88 100644 --- a/src/mainboard/asus/m4a785t-m/dsdt.asl +++ b/src/mainboard/asus/m4a785t-m/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/asus/m5a88-v/dsdt.asl b/src/mainboard/asus/m5a88-v/dsdt.asl index b9a699b..a248766 100644 --- a/src/mainboard/asus/m5a88-v/dsdt.asl +++ b/src/mainboard/asus/m5a88-v/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/avalue/eax-785e/dsdt.asl b/src/mainboard/avalue/eax-785e/dsdt.asl index 1287f95..b835128 100644 --- a/src/mainboard/avalue/eax-785e/dsdt.asl +++ b/src/mainboard/avalue/eax-785e/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1156,7 +1156,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/getac/p470/dsdt.asl b/src/mainboard/getac/p470/dsdt.asl index 9728ea2..baca3da 100644 --- a/src/mainboard/getac/p470/dsdt.asl +++ b/src/mainboard/getac/p470/dsdt.asl @@ -35,7 +35,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -49,11 +49,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> } diff --git a/src/mainboard/gigabyte/ma785gmt/dsdt.asl b/src/mainboard/gigabyte/ma785gmt/dsdt.asl index fdd3a3e..a29bb2a 100644 --- a/src/mainboard/gigabyte/ma785gmt/dsdt.asl +++ b/src/mainboard/gigabyte/ma785gmt/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/gigabyte/ma78gm/dsdt.asl b/src/mainboard/gigabyte/ma78gm/dsdt.asl index 03d8fcd..c850b9e 100644 --- a/src/mainboard/gigabyte/ma78gm/dsdt.asl +++ b/src/mainboard/gigabyte/ma78gm/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/ibase/mb899/dsdt.asl b/src/mainboard/ibase/mb899/dsdt.asl index f06b225..601c329 100644 --- a/src/mainboard/ibase/mb899/dsdt.asl +++ b/src/mainboard/ibase/mb899/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> } diff --git a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl index 7ae6bd5..66f8254 100644 --- a/src/mainboard/iei/kino-780am2-fam10/dsdt.asl +++ b/src/mainboard/iei/kino-780am2-fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/intel/d945gclf/dsdt.asl b/src/mainboard/intel/d945gclf/dsdt.asl index 49b6033..62fa0af 100644 --- a/src/mainboard/intel/d945gclf/dsdt.asl +++ b/src/mainboard/intel/d945gclf/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" @@ -44,11 +44,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> } diff --git a/src/mainboard/iwave/iWRainbowG6/dsdt.asl b/src/mainboard/iwave/iWRainbowG6/dsdt.asl index f19ffb9..5bf59a7 100644 --- a/src/mainboard/iwave/iWRainbowG6/dsdt.asl +++ b/src/mainboard/iwave/iWRainbowG6/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/sch/acpi/globalnvs.asl" + #include <southbridge/intel/sch/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/sch/acpi/sch.asl" - #include "../../../southbridge/intel/sch/acpi/sch.asl" + #include <northbridge/intel/sch/acpi/sch.asl> + #include <southbridge/intel/sch/acpi/sch.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/sch/acpi/sleepstates.asl" + #include <southbridge/intel/sch/acpi/sleepstates.asl> } diff --git a/src/mainboard/jetway/pa78vm5/dsdt.asl b/src/mainboard/jetway/pa78vm5/dsdt.asl index 38de9b9..8f75019 100644 --- a/src/mainboard/jetway/pa78vm5/dsdt.asl +++ b/src/mainboard/jetway/pa78vm5/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1162,7 +1162,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/kontron/986lcd-m/dsdt.asl b/src/mainboard/kontron/986lcd-m/dsdt.asl index 2235f62..a32015f 100644 --- a/src/mainboard/kontron/986lcd-m/dsdt.asl +++ b/src/mainboard/kontron/986lcd-m/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" @@ -40,11 +40,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> } diff --git a/src/mainboard/kontron/kt690/dsdt.asl b/src/mainboard/kontron/kt690/dsdt.asl index 20ecb5b..a740a8b 100644 --- a/src/mainboard/kontron/kt690/dsdt.asl +++ b/src/mainboard/kontron/kt690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/lenovo/t60/dsdt.asl b/src/mainboard/lenovo/t60/dsdt.asl index 905c94a..52a5edb 100644 --- a/src/mainboard/lenovo/t60/dsdt.asl +++ b/src/mainboard/lenovo/t60/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -43,13 +43,13 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/lenovo/x60/dsdt.asl b/src/mainboard/lenovo/x60/dsdt.asl index 905c94a..52a5edb 100644 --- a/src/mainboard/lenovo/x60/dsdt.asl +++ b/src/mainboard/lenovo/x60/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -43,13 +43,13 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> // Dock support code #include "acpi/dock.asl" diff --git a/src/mainboard/msi/ms9652_fam10/dsdt.asl b/src/mainboard/msi/ms9652_fam10/dsdt.asl index fe34112..c889841 100644 --- a/src/mainboard/msi/ms9652_fam10/dsdt.asl +++ b/src/mainboard/msi/ms9652_fam10/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE ", "COREBOOT", 1) { - #include "../../../../src/northbridge/amd/amdk8/util.asl" + #include <northbridge/amd/amdk8/util.asl> /* For now only define 2 power states: * - S0 which is fully on diff --git a/src/mainboard/roda/rk886ex/dsdt.asl b/src/mainboard/roda/rk886ex/dsdt.asl index e3a62a3..58e78ec 100644 --- a/src/mainboard/roda/rk886ex/dsdt.asl +++ b/src/mainboard/roda/rk886ex/dsdt.asl @@ -32,7 +32,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include "../../../southbridge/intel/i82801gx/acpi/globalnvs.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> // General Purpose Events #include "acpi/gpe.asl" @@ -46,11 +46,11 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - #include "../../../northbridge/intel/i945/acpi/i945.asl" - #include "../../../southbridge/intel/i82801gx/acpi/ich7.asl" + #include <northbridge/intel/i945/acpi/i945.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> } } /* Chipset specific sleep states */ - #include "../../../southbridge/intel/i82801gx/acpi/sleepstates.asl" + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> } diff --git a/src/mainboard/supermicro/h8qgi/dsdt.asl b/src/mainboard/supermicro/h8qgi/dsdt.asl index 3f10012..137a90d 100644 --- a/src/mainboard/supermicro/h8qgi/dsdt.asl +++ b/src/mainboard/supermicro/h8qgi/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl"*/ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1132,7 +1132,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl index e8139c4..dd3c897 100644 --- a/src/mainboard/supermicro/h8scm_fam10/dsdt.asl +++ b/src/mainboard/supermicro/h8scm_fam10/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1180,7 +1180,7 @@ DefinitionBlock ( /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/technexion/tim5690/dsdt.asl b/src/mainboard/technexion/tim5690/dsdt.asl index 409d941..9279b5f 100644 --- a/src/mainboard/technexion/tim5690/dsdt.asl +++ b/src/mainboard/technexion/tim5690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */ diff --git a/src/mainboard/technexion/tim8690/dsdt.asl b/src/mainboard/technexion/tim8690/dsdt.asl index 5fd3e3e..b13d2ec 100644 --- a/src/mainboard/technexion/tim8690/dsdt.asl +++ b/src/mainboard/technexion/tim8690/dsdt.asl @@ -27,7 +27,7 @@ DefinitionBlock ( 0x00010001 /* OEM Revision */ ) { /* Start of ASL file */ - /* #include "../../../arch/x86/acpi/debug.asl" */ /* Include global debug methods if needed */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ /* Data to be patched by the BIOS during POST */ /* FIXME the patching is not done yet! */ @@ -1123,7 +1123,7 @@ DefinitionBlock ( /* South Bridge */ Scope(\_SB) { /* Start \_SB scope */ - #include "../../../arch/x86/acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ /* _SB.PCI0 */ /* Note: Only need HID on Primary Bus */

1 0

Patch set updated for coreboot: 5cb35be amd/sb600: Move HAVE_HARD_RESET to southbridge
by Patrick Georgi 22 Feb '12

22 Feb '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/660 -gerrit commit 5cb35be4906ab6df74545feeca67b10a444ab8bd Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:45:56 2012 +0100 amd/sb600: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/amd/dbm690t/Kconfig | 1 - src/mainboard/amd/pistachio/Kconfig | 1 - src/mainboard/kontron/kt690/Kconfig | 1 - src/mainboard/siemens/sitemp_g1p1/Kconfig | 1 - src/mainboard/technexion/tim5690/Kconfig | 1 - src/mainboard/technexion/tim8690/Kconfig | 1 - src/southbridge/amd/sb600/Kconfig | 1 + 7 files changed, 1 insertions(+), 6 deletions(-) diff --git a/src/mainboard/amd/dbm690t/Kconfig b/src/mainboard/amd/dbm690t/Kconfig index 3d3a04c..d1bf72f 100644 --- a/src/mainboard/amd/dbm690t/Kconfig +++ b/src/mainboard/amd/dbm690t/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/amd/pistachio/Kconfig b/src/mainboard/amd/pistachio/Kconfig index 487a599..d140878 100644 --- a/src/mainboard/amd/pistachio/Kconfig +++ b/src/mainboard/amd/pistachio/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/mainboard/kontron/kt690/Kconfig b/src/mainboard/kontron/kt690/Kconfig index 91d6b67..6a1909f 100644 --- a/src/mainboard/kontron/kt690/Kconfig +++ b/src/mainboard/kontron/kt690/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_MAINBOARD_RESOURCES select GFXUMA - select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/siemens/sitemp_g1p1/Kconfig b/src/mainboard/siemens/sitemp_g1p1/Kconfig index 1bc7406..b2cae03 100644 --- a/src/mainboard/siemens/sitemp_g1p1/Kconfig +++ b/src/mainboard/siemens/sitemp_g1p1/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_MAINBOARD_RESOURCES select HAVE_BUS_CONFIG - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig index 21cfa7b..404ddfe 100644 --- a/src/mainboard/technexion/tim5690/Kconfig +++ b/src/mainboard/technexion/tim5690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select HAVE_ACPI_TABLES select GFXUMA diff --git a/src/mainboard/technexion/tim8690/Kconfig b/src/mainboard/technexion/tim8690/Kconfig index 5af6ace..293590c 100644 --- a/src/mainboard/technexion/tim8690/Kconfig +++ b/src/mainboard/technexion/tim8690/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select WAIT_BEFORE_CPUS_INIT select HAVE_ACPI_TABLES diff --git a/src/southbridge/amd/sb600/Kconfig b/src/southbridge/amd/sb600/Kconfig index 07028a0..8ec3967 100644 --- a/src/southbridge/amd/sb600/Kconfig +++ b/src/southbridge/amd/sb600/Kconfig @@ -21,6 +21,7 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC select HAVE_USBDEBUG + select HAVE_HARD_RESET if SOUTHBRIDGE_AMD_SB600 config BOOTBLOCK_SOUTHBRIDGE_INIT

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New patch to review for coreboot: 1041a87 Update xcompile to search for x86_64 toolchain.
by Marc Jones 22 Feb '12

22 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/673 -gerrit commit 1041a87f618b4772f6ec9796c3224258888d3645 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Wed Feb 22 11:46:17 2012 -0700 Update xcompile to search for x86_64 toolchain. This adds detection of x86_64 gcc toolchain (which buildgcc can build if provided the option). Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/xcompile/xcompile | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 4926394..f8a69bb 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -36,14 +36,19 @@ done GCCPREFIX=invalid XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} -echo '#XGCCPATH='${XGCCPATH} +echo '# XGCCPATH='${XGCCPATH} TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` touch $TMPFILE -# This should be a loop over all supported architectures -TARCH=i386 +# This loops over all supported architectures in TARCH +TARCH=('i386' 'x86_64') TWIDTH=32 -for gccprefixes in ${XGCCPATH}${TARCH}-elf- ${TARCH}-elf- ""; do +for search_for in "${TARCH[@]}"; do + TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-) +done +echo '# TARCH_SEARCH='${TARCH_SEARCH[@]} + +for gccprefixes in "${TARCH_SEARCH[@]}" ""; do if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi

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Re: [coreboot] New patch to review for coreboot: 617edf7 Revert "Fix multipleVGA cards resource conflict on Windows"
by She Kairui 22 Feb '12

22 Feb '12

Hi Marc, > From: Marc Jones <gerrit(a)coreboot.org> > Date: Wed, 22 Feb 2012 01:46:33 +0100 > Subject: [coreboot] New patch to review for coreboot: 617edf7 Revert > "Fix multipleVGA cards resource conflict on Windows" > To: coreboot(a)coreboot.org > > Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to > gerrit, which you can find at http://review.coreboot.org/671 > > -gerrit > > commit 617edf7e746df87616e4ada8a40decabe1231341 > Author: Marc Jones <marcj303(a)gmail.com> > Date: Tue Feb 21 17:44:35 2012 +0100 > > Revert "Fix multipleVGA cards resource conflict on Windows" > > This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e > > This commit has been found to cause problems with vbios and option rom > init > in seabios. It has been found by several people and requires more > analysis > before being recommitted. > http://review.coreboot.org/#change,489 Patch Set 4 is another way to resolve the multiVGA problem in windows. does your platform booting with this patch set? Thanks Kerry > Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230 > Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> > --- > src/devices/device.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/src/devices/device.c b/src/devices/device.c > index 8ad9787..a2619bf 100644 > --- a/src/devices/device.c > +++ b/src/devices/device.c > @@ -932,6 +932,10 @@ void dev_configure(void) > struct device *root; > struct device *child; > > +#if CONFIG_VGA_BRIDGE_SETUP == 1 > + set_vga_bridge_bits(); > +#endif > + > printk(BIOS_INFO, "Allocating resources...\n"); > > root = &dev_root; > @@ -1024,10 +1028,6 @@ void dev_configure(void) > printk(BIOS_INFO, "Done setting resources.\n"); > print_resource_tree(root, BIOS_SPEW, "After assigning values."); > > -#if CONFIG_VGA_BRIDGE_SETUP == 1 > - set_vga_bridge_bits(); > -#endif > - > printk(BIOS_INFO, "Done allocating resources.\n"); > } > > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot >

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Re: [coreboot] Coreboot support for ASUS M5 A99X EVO ?
by Bernhard Urban 22 Feb '12

22 Feb '12

hi, so finally, I spent some time on porting coreboot to the asus board "m5a99x evo". http://www.asus.com/Motherboards/AMD_AM3Plus/M5A99X_EVO/ I was equipped with three DIP chips and decided to use my target machine also for developing. I had also set up a quite complicated configuration for serial debugging, as I didn't own a second machine with a rs232 board. Although the first try (just flash the "m5a88-v" configuration) showed some output :-) ( http://tinyurl.com/89a33m5 ), the build cycle was a pain in the ass. (0) building coreboot (takes some seconds...) (1) flashing the chip (~30seconds, without verifying) (2) reboot (~20sec) (3) starting coreboot and analyse the output (between 1sec and some minutes ;-)) (4) switch chip with vendor bios on it (some seconds) (5) booting vendor bios and linux (35sec + 11sec. yes, the vendor firmware takes three times longer than linux + x11. BOAR ;-)) (6) switch chip again. So I was looking for alternatives. I remembered the ft2232 stuff by Uwe. I had it anyway on my "order it some day"-list, so it was the right time ;-) In the meanwhile, I refit my old machine with a new hdd and a reasoneable graphic card. Luckily, it has also a serial port :-) I was a bit afraid of building a programmer (the ft2232 thingy) as I'm not really the hardware guy. However, the first dump was successful. Writing was working too. I was impressed :-) Thanks to Uwe at this point! So the build cycle is more convenient now: (0) building coreboot (takes longer than on my new machine, but it's okay ;-)) (1) flash the chip with the ft2232 thingy (~30 seconds, without verifying) (2) put the chip onto the mainboard (3) start machine and watch serial output all in all, it take like one minute to test one build. nice! So, now I was able to do some serious coreboot hacking. I started from the "m5a88-v" port. What I did: - Changed the southbridge from "SB800" to "SB900" - Adapted some compile-breaks due to this change. - hardcoded some pci device instead of locating it @ early.c -> ohai ramstage :-) - again, some pci related change/hack (aborting the enumeration earlier). I didn't really understand what I did here, I just figured out it hangs here (could be related with the quirk below). After that -> OHAI SEABIOS! I was very happy ;) However, SeaBIOS itself hang somewhere. In the meanwhile, Kerry pushed RD890 patches, which seemed to be more appropriate for my board (i used RS780 code so far, hence the ugly hacks mentioned above I guess). So I used them, and it felt much cleaner immediately. The payload was still loading -> nice. After that, I investigated a bit what the problem is with SeaBIOS. At this moment, it hanged after printing "Relocating init from 0x000e8450 to 0xcffd57a0 (size 42812)" (see http://tinyurl.com/78evzex ). I looked into the SeaBIOS code and found out, that you can disable relocation. So I did. The result was a bit more confusing. http://tinyurl.com/7uh8xty The output get distorted (which seems not to be deterministically, http://tinyurl.com/6opakzl ) and something issues a soft reset (but not everytime...). Eventually I gave up at this point (had to do other stuff anyway). I guess it is something wrong with RAM initialization as relocation in higher memory regions doesn't work. Also, the graphic card isn't found on the pci bus as the RD890 code inlcudes a quirk which "disable all pcie bridges" aka `sr56x0_rd890_disable_pcie_bridge()'. According to `lspci' (with vendor bios), the graphic card is on bus 1, so this seem reasonably. @Kerry: is there some way to enable it again after "early"? my WIP branch is available here (please tell me if you pull from it, because atm I'm rebasing stuff on it and using `git push -f' to overwrite it...): http://wien.tomnetworks.com/gitweb/?p=coreboot.git;a=shortlog;h=refs/heads/… full logs (including config and rom images) are available here: http://wien.tomnetworks.com/gitweb/?p=cbimages.git;a=tree Some questions: - What does "CIMX" stands for? I grep'd my #coreboot logs for it. One guy asked that already, but he didn't get an answer :-/ - What's the best/easiest way to verify if RAM init was successful? - I think it would be nice to have an entry on the wiki page for this board. How I get an account? Stefan? :-) I appreciate any comment, I know resources are short :-( anyways, it was fun and exciting so far :-) thanks! regards, bernhard On Wed, Nov 23, 2011 at 10:29 PM, Bernhard Urban <lewurm(a)gmail.com> wrote: > Hi Chris, > > I reported flashrom compatibility here: > http://www.flashrom.org/pipermail/flashrom/2011-October/008152.html > > Regarding coreboot support: I'll try to port coreboot to this board. I > already have two additional flashchips and at the moment I'm waiting > for a serial port connector. I don't know how long it'll talke to port > it, but don't except anything useful in less than three months, since > I'm new to coreboot (and lazy :-)) > > > Bernhard > > On Sat, Nov 19, 2011 at 6:33 PM, Christopher Huang-Leaver > <zeonglow(a)googlemail.com> wrote: >> Hello, >> I noticed earlier versions of this board are fully supported, but not this >> one. >> I have attached the output of, lspci, flashrom and dmidecode, if that is >> any use to anyone. >> The spec sheet is easy to find by typing ASUS M5 A99X into Google. The >> board does have a neat feature of being able to flash the BIOS from within >> the BIOS menu, which I have already used to update it. >> Many thanks >> Chris

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Patch merged into coreboot/master: 3d3abb2 Remove old AMD fam10 fixme comment
by gerrit＠coreboot.org 22 Feb '12

22 Feb '12

the following patch was just integrated into master: commit 3d3abb2e9ce3a175c9182b6bc3ad17bc3487735b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 21 17:53:13 2012 -0700 Remove old AMD fam10 fixme comment The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Wed Feb 22 11:35:17 2012, giving +2 See http://review.coreboot.org/672 for details. -gerrit

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flaschip (and compatibles)
by Oliver Schinagl 22 Feb '12

22 Feb '12

Hey list, I want (in the far? future) play with coreboot on my new board, an Asus M5A97 (900 series amd chipset) thing. Having it not even build into my case yet, I was wondering if you guys know what a compatible flash chip is. I have an 8 legged little socketable chip on here, with the following markings: MXIC b111376-12G MX25L3206EPI 3F204500 So far I found the best results from google with the MX25L3206EPI labeling but the few links I got where mostly in chinese and the datasheet links where the 'pay' kind. Any pointers what I can ask for when I go to my local hardware store so I can order 3 or 4? Shouldn't be too expensive right? Anything in NL/BE/DE I suppose would work best :)

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Asus M2V-MX memory init
by David Hillman 21 Feb '12

21 Feb '12

Northbridge: K8M890 Southbridge: VT8237A Superio: ITE IT8716F I finally got past booting this board. The system boots fine with a 2GB stick of memory, but it freezes with 4GB. It looks like I am missing something to properly initialize memory to get correct SPD info. Maybe SMBUS isn't working properly? What should I check? Here is the log for 4GB (2 sticks): coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change Current fid_cur: 0x2, fid_max: 0x12 Requested fid_new: 0x12 FidVid table step fidvid: 0xe FidVid table step fidvid: 0x10 200MHZ step fidvid: 0x12 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000ceee8 Device error Device error Enabling dual channel memory Unbuffered 400MHz 400MHz Interleaved RAM end at 0x00400000 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB Setting variable MTRR 3, base: 2048MB, range: 1024MB, type WB Setting variable MTRR 4, base: 3072MB, range: 512MB, type WB Setting variable MTRR 5, base: 3584MB, range: 256MB, type WB Setting variable MTRR 6, base: 3840MB, range: 128MB, type WB Setting variable MTRR 7, base: 3968MB, range: 64MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce950 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=34 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 Writing 17151515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 Writing 18171819 of size 4 to nvram pos: 17 Writing 18181718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 Writing 32 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 Writing 113222 of size 4 to nvram pos: 30 Writing 15141615 of size 4 to nvram pos: 34 Writing 15141515 of size 4 to nvram pos: 38 Writing 15 of size 1 to nvram pos: 42 Writing 202520 of size 4 to nvram pos: 43 Writing 17191818 of size 4 to nvram pos: 47 Writing 18191716 of size 4 to nvram pos: 51 Writing 16 of size 1 to nvram pos: 55 Writing 34 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 Writing 7410809b of size 4 to nvram pos: 60 DQS Training:tsc[00]=000000008cbdd63c DQS Training:tsc[01]=000000008f476e2e DQS Training:tsc[02]=000000008f476e37 DQS Training:tsc[03]=000000015b152149 DQS Training:tsc[04]=000000016daed79e Ram4 v_esp=000cef28 testx = 5a5a5a5a IN TEST WAKEUP 800Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (622592 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-2000-g91be49b-dirty Wed Feb 15 22:11:37 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [1106/0336] ops VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled Capability: type 0x02 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x08 @ 0x60 flags: 0x0060 PCI: 00:00.0 count: 0003 static_count: 0014 PCI: 00:00.0 [1106/0336] enabled next_unitid: 0014 PCI: pci_scan_bus for bus 00 VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled PCI: 00:00.1 [1106/1336] ops K8x8xx: Enabling NB error reporting: Done VIA_X_1 device dump: 00: 06 11 36 13 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.1 [1106/1336] enabled PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops K8M890: UMA base is fa000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff 30 00 fc 19 00 fc 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.3 [1106/3336] enabled PCI: 00:00.4 [1106/4336] enabled PCI: 00:00.5 [1106/5336] ops PCI: 00:00.5 [1106/5336] enabled PCI: 00:00.6 [1106/6290] enabled PCI: 00:00.7 [1106/7336] ops PCI: 00:00.7 [1106/7336] enabled PCI: 00:01.0 [1106/b188] bus ops B188 device dump 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 40: 91 40 08 44 31 3a 88 b1 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 0e 70 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 80 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.0 [1106/b188] enabled PCI: 00:02.0 [1106/a238] bus ops Configuring PCIe PEG 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c 12 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 07 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 PCIe link timeout 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 7c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c f0 40 81 00 00 03 00 01 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 0b 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 [1106/a238] enabled PCI: 00:03.0 [1106/c238] bus ops Configuring PCIe PEXs 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 PCIe link up after 15100 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 [1106/c238] enabled PCI: 00:0f.0 [1106/0591] ops PCI: 00:0f.0 [1106/0591] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled PCI: 00:11.0 [1106/3337] bus ops PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled PCI: Static device PCI: 00:12.0 not found, disabling it. Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.0 [1106/337b] enabled Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.1 [1106/337a] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3230] ops PCI: 01:00.0 [1106/3230] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [197b/2363] enabled PCI: pci_scan_bus returning with max=003 Capability: type 0x01 @ 0x68 Capability: type 0x10 @ 0x50 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:11.0 smbus: PCI: 00:11.0[0]->I2C: 01:50 enabled smbus: PCI: 00:11.0[0]->I2C: 01:51 enabled smbus: PCI: 00:11.0[0]->I2C: 01:52 enabled smbus: PCI: 00:11.0[0]->I2C: 01:53 enabled PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 disabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:11.0 done do_pci_scan_bridge for PCI: 00:13.0 PCI: pci_scan_bus for bus 04 PCI: 04:01.0 [1106/3288] enabled PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:13.1 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:02.0 read_resources bus 2 link: 0 PCI: 00:02.0 read_resources bus 2 link: 0 done PCI: 00:03.0 read_resources bus 3 link: 0 PCI: 00:03.0 read_resources bus 3 link: 0 done PCI: 00:11.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:11.0 read_resources bus 1 link: 0 done PCI: 00:13.0 read_resources bus 4 link: 0 PCI: 00:13.0 read_resources bus 4 link: 0 done PCI: 00:13.1 read_resources bus 5 link: 0 PCI: 00:13.1 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8 PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 10000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 03:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 03:00.0 20 * [0x0 - 0xf] io PCI: 03:00.0 10 * [0x10 - 0x17] io PCI: 03:00.0 18 * [0x18 - 0x1f] io PCI: 03:00.0 14 * [0x20 - 0x23] io PCI: 03:00.0 1c * [0x24 - 0x27] io PCI: 00:03.0 compute_resources_io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 1c * [0x0 - 0xfff] io PCI: 00:0f.0 24 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI: 00:18.0 compute_resources_io: base: 14b8 size: 2000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 24 * [0x10000000 - 0x1fffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 14 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:01.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 30 * [0x0 - 0xffff] mem PCI: 03:00.0 24 * [0x10000 - 0x11fff] mem PCI: 00:03.0 compute_resources_mem: base: 12000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:01.0 10 * [0x0 - 0x3fff] mem PCI: 00:13.0 compute_resources_mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.5 61 * [0x0 - 0xfffffff] mem PCI: 00:01.0 20 * [0x10000000 - 0x110fffff] mem PCI: 00:03.0 20 * [0x11100000 - 0x111fffff] mem PCI: 00:13.0 20 * [0x11200000 - 0x112fffff] mem PCI: 00:10.4 10 * [0x11300000 - 0x113000ff] mem PCI: 00:18.0 compute_resources_mem: base: 11300100 size: 11400000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 02 * [0x0 - 0x1fffffff] prefmem PCI: 00:18.0 01 * [0x20000000 - 0x313fffff] mem PCI: 00:18.3 94 * [0x34000000 - 0x37ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.5 constrain_resources: PCI: 00:00.6 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:11.0 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.4 constrain_resources: PCI: 00:11.7 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 04:01.0 constrain_resources: PCI: 00:13.1 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:ffff Assigned: PCI: 00:03.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:0f.0 24 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI: 00:18.0 allocate_resources_io: next_base: 24b8 size: 2000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:00.0 20 * [0x1000 - 0x100f] io Assigned: PCI: 03:00.0 10 * [0x1010 - 0x1017] io Assigned: PCI: 03:00.0 18 * [0x1018 - 0x101f] io Assigned: PCI: 03:00.0 14 * [0x1020 - 0x1023] io Assigned: PCI: 03:00.0 1c * [0x1024 - 0x1027] io PCI: 00:03.0 allocate_resources_io: next_base: 1028 size: 1000 align: 12 gran: 12 done PCI: 00:13.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:13.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:febfffff Assigned: PCI: 00:18.0 02 * [0xc0000000 - 0xdfffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xe0000000 - 0xf13fffff] mem Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.0 10 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:01.0 24 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:d0000000 size:10000000 align:28 gran:20 limit:febfffff Assigned: PCI: 01:00.0 10 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: e0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:e0000000 size:11400000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.5 61 * [0xe0000000 - 0xefffffff] mem Assigned: PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem Assigned: PCI: 00:03.0 20 * [0xf1100000 - 0xf11fffff] mem Assigned: PCI: 00:13.0 20 * [0xf1200000 - 0xf12fffff] mem Assigned: PCI: 00:10.4 10 * [0xf1300000 - 0xf13000ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: f1300100 size: 11400000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:f0000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 01:00.0 14 * [0xf0000000 - 0xf0ffffff] mem Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf100ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: f1010000 size: 1100000 align: 24 gran: 20 done PCI: 00:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:f1100000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 03:00.0 30 * [0xf1100000 - 0xf110ffff] mem Assigned: PCI: 03:00.0 24 * [0xf1110000 - 0xf1111fff] mem PCI: 00:03.0 allocate_resources_mem: next_base: f1112000 size: 100000 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_mem: base:f1200000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 04:01.0 10 * [0xf1200000 - 0xf1203fff] mem PCI: 00:13.0 allocate_resources_mem: next_base: f1204000 size: 100000 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 node 0 : uma_memory_base/1024=0x003e8000, mmio_basek=0x00300000, basek=0x00000300, limitk=0x00400000 split: 1088K table at =f9ef0000 0: mmio_basek=00300000, basek=00300000, limitk=00400000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io <node 0 link 0> PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 prefmem <node 0 link 0> PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f13fffff] size 0x11400000 gran 0x14 mem <node 0 link 0> PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:00.0 14 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f100ffff] size 0x00010000 gran 0x10 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:03.0 20 <- [0x00f1100000 - 0x00f11fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 03:00.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io PCI: 03:00.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io PCI: 03:00.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io PCI: 03:00.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 03:00.0 24 <- [0x00f1110000 - 0x00f1111fff] size 0x00002000 gran 0x0d mem PCI: 03:00.0 30 <- [0x00f1100000 - 0x00f110ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00f1300000 - 0x00f13000ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 1 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000230 - 0x0000000237] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PCI: 00:11.0 assign_resources, bus 1 link: 0 PCI: 00:13.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:13.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:13.0 20 <- [0x00f1200000 - 0x00f12fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 04:01.0 10 <- [0x00f1200000 - 0x00f1203fff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 00:13.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:13.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:13.1 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base c0000000 size 3fffe000000 align 0 gran 0 limit 0 flags e0004200 index 30 PCI_DOMAIN: 0000 resource base fa000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff flags 60080100 index 1c0 PCI: 00:18.0 resource base c0000000 size 20000000 align 28 gran 20 limit febfffff flags 60081200 index 1b8 PCI: 00:18.0 resource base e0000000 size 11400000 align 28 gran 20 limit febfffff flags 60080200 index 1b0 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 70000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base d0000000 size 10000000 align 28 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base d0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 14 PCI: 01:00.0 resource base f1000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:03.0 resource base f1100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 03:00.0 resource base f1110000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 24 PCI: 03:00.0 resource base f1100000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base f1300000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.0 resource base f1200000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base f1200000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/0000 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/0000 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/0000 PCI: 00:00.0 cmd <- 02 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 cmd <- 06 PCI: 00:00.3 cmd <- 06 PCI: 00:00.4 cmd <- 06 PCI: 00:00.5 cmd <- 06 PCI: 00:00.6 cmd <- 06 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 001f PCI: 00:01.0 cmd <- 07 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 07 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 01 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:11.0 subsystem <- 1043/0000 PCI: 00:11.0 cmd <- 01 PCI: 00:11.7 cmd <- 00 PCI: 00:13.0 bridge ctrl <- 0003 PCI: 00:13.0 cmd <- 07 PCI: 00:13.1 bridge ctrl <- 0003 PCI: 00:13.1 cmd <- 01 PCI: 01:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 03 PCI: 04:01.0 cmd <- 02 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 50ff3 CPU: family 0f, model 5f, stepping 03 Enabling cache CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 2048MB, range: 1024MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 2, base: 4000MB, range: 32MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 Processor 4000+ Setting up local apic... apic_id: 0x00 done. Scrubbing Disabled ECC Disabled CPU #0 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:18.1 init Searching for pci1022,1101.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1101.rom'. PCI: 00:18.2 init Searching for pci1022,1102.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1102.rom'. PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:00.0 init PCI: 00:00.3 init K8M890: Using a 32MB framebuffer. PCI: 00:00.4 init Searching for pci1106,4336.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,4336.rom'. PCI: 00:00.6 init Searching for pci1106,6290.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,6290.rom'. PCI: 00:00.7 init K8x8xx: Initializing V-Link to VT8237R sb: VT8237R LPC not found ! PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0xb Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:11.0 init SLP_TYP type was 800 0 RTC Init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 00: 06 11 37 33 01 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 7f f8 0b 00 00 00 00 0c 20 00 00 44 00 00 08 50: c0 0d 09 00 00 00 00 00 43 80 00 0b 00 00 00 00 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 90: 00 04 99 88 a0 cc 00 02 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 08 00 24 69 10 80 00 00 00 00 04 00 00 00 f0: 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00 PCI: 00:11.7 init 00: 06 11 7e 28 00 00 10 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 50: 00 03 33 03 00 04 01 fc 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: fd 3f df 00 00 00 00 e0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 50 ee 88 8a 88 00 03 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 19 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 b0 00 00 00 PCI: 01:00.0 init Chrome: Using 32MB Framebuffer at 0xD0000000. Chrome VGA Textmode initialized. PCI: 03:00.0 init Searching for pci197b,2363.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci197b,2363.rom'. On card, ROM address for PCI: 03:00.0 = f1100000 PCI expansion ROM, signature 0x7f7f, INIT size 0xfe00, data ptr 0x7f7f Incorrect expansion ROM header signature 7f7f PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.3 init PNP: 002e.4 init FAN_CTL: reg = 0x02a9, read value = 0x50 FAN_CTL: reg = 0x02a9, writing value = 0xd7 PCI: 04:01.0 init Searching for pci1106,3288.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,3288.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.5: enabled 1 PCI: 00:00.6: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.7: enabled 1 PCI: 01:00.0: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 Initializing CBMEM area to 0xf9ef0000 (1114112 bytes) ERROR: CBMEM was not initialized yet. Error: Could not relocate GDT. High Tables Base is f9ef0000. ERROR: CBMEM was not initialized yet. ACPI: Writing ACPI tables at f0000... ACPI: * FACS ACPI: * DSDT @ 000f0140 Length ba5 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET ACPI: added table 2/32, length now 44 ACPI: * MADT ACPI: added table 3/32, length now 48 ACPI: * MCFG ACPI: added table 4/32, length now 52 ACPI: * SRAT SRAT: lapic cpu_index=00, node_id=00, apic_id=00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0030 startk=00300000, sizek=ffff8000 ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 ACPI: * SSDT processor_brand=AMD Athlon(tm) 64 Processor 4000+ Pstates Algorithm ... Pstate_freq[0] = 2600MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw Pstate_freq[1] = 2400MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 566975mw Pstate_freq[2] = 2200MHz Pstate_vid[2] = 12 Pstate_volt[2] = 1250mv Pstate_power[2] = 480516mw Pstate_freq[3] = 2000MHz Pstate_vid[3] = 14 Pstate_volt[3] = 1200mv Pstate_power[3] = 402585mw Pstate_freq[4] = 1000MHz Pstate_vid[4] = 18 Pstate_volt[4] = 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. ERROR: CBMEM was not initialized yet. smbios_write_tables: 000f1400 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) PCI_DOMAIN: 0000 (AMD K8 Root Complex) PCI: 00:18.0 (AMD K8 Northbridge) PCI: 00:00.0 (VIA VT8237R Southbridge) PCI: 00:0f.1 (VIA VT8237R Southbridge) PCI: 00:11.0 (VIA VT8237R Southbridge) I2C: 01:50 () I2C: 01:51 () I2C: 01:52 () I2C: 01:53 () PNP: 002e.0 (ITE IT8716F Super I/O) PNP: 002e.1 (ITE IT8716F Super I/O) PNP: 002e.2 (ITE IT8716F Super I/O) PNP: 002e.3 (ITE IT8716F Super I/O) PNP: 002e.4 (ITE IT8716F Super I/O) PNP: 002e.5 (ITE IT8716F Super I/O) PNP: 002e.6 (ITE IT8716F Super I/O) PNP: 002e.7 (ITE IT8716F Super I/O) PNP: 002e.8 (ITE IT8716F Super I/O) PNP: 002e.9 (ITE IT8716F Super I/O) PNP: 002e.a (ITE IT8716F Super I/O) PCI: 00:12.0 (VIA VT8237R Southbridge) PCI: 00:13.0 (VIA VT8237R Southbridge) PCI: 00:13.1 (VIA VT8237R Southbridge) PCI: 00:18.1 (AMD K8 Northbridge) PCI: 00:18.2 (AMD K8 Northbridge) PCI: 00:18.3 (AMD K8 Northbridge) PCI: 00:00.1 () PCI: 00:00.2 () PCI: 00:00.3 () PCI: 00:00.4 () PCI: 00:00.5 () PCI: 00:00.6 () PCI: 00:00.7 () PCI: 00:01.0 () PCI: 00:02.0 () PCI: 00:03.0 () PCI: 00:0f.0 () PCI: 00:10.0 () PCI: 00:10.1 () PCI: 00:10.2 () PCI: 00:10.3 () PCI: 00:10.4 () PCI: 00:11.7 () PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () SMBIOS size 277 bytes ERROR: CBMEM was not initialized yet. Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum eaaf New low_table_end: 0x00000518 Now going to write high coreboot table at 0x000f1520 rom_table_end = 0x000f1520 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x000f1520 to 0x00100000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-00000000000effff: RAM 3. 00000000000f0000-00000000000fffff: CONFIGURATION TABLES 4. 0000000000100000-00000000bfffffff: RAM 5. 00000000c0000000-00000000dfffffff: RAM 6. 00000000e0000000-00000000efffffff: RESERVED 7. 00000000f0000000-00000000f9eeffff: RAM 8. 00000000f9ef0000-00000000f9ffffff: CONFIGURATION TABLES 9. 00000000fa000000-00000000fbffffff: RESERVED 10. 00000000fc000000-00000000febfffff: RAM 11. 00000000fec00000-00000000fec000ff: RESERVED 12. 00000000fec00100-00000000fecbffff: RAM 13. 00000000fecc0000-00000000fecc00ff: RESERVED 14. 00000000fecc0100-00000000feffffff: RAM 15. 00000000ff000000-00000000ffffffff: RESERVED 16. 0000000100000000-00000400bdffffff: RAM Wrote coreboot table at: 000f1520 - 000f17d4 checksum f32e ERROR: CBMEM was not initialized yet. Multiboot Information structure has been written. Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfffad538 data (compression=1) New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8ba (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8ba Loading segment from rom address 0xfffad554 Entry Point 0x00000000 No matching ram area found for range: [0x00000000000e6b54, 0x0000000000100000) Ram areas [0x0000000000000000, 0x0000000000001000) Reserved [0x0000000000001000, 0x00000000000a0000) RAM [0x00000000000c0000, 0x00000000000f0000) RAM [0x00000000000f0000, 0x0000000000100000) Reserved [0x0000000000100000, 0x00000000c0000000) RAM [0x00000000c0000000, 0x00000000e0000000) RAM [0x00000000e0000000, 0x00000000f0000000) Reserved [0x00000000f0000000, 0x00000000f9ef0000) RAM [0x00000000f9ef0000, 0x00000000fa000000) Reserved [0x00000000fa000000, 0x00000000fc000000) Reserved [0x00000000fc000000, 0x00000000fec00000) RAM [0x00000000fec00000, 0x00000000fec00100) Reserved [0x00000000fec00100, 0x00000000fecc0000) RAM [0x00000000fecc0000, 0x00000000fecc0100) Reserved [0x00000000fecc0100, 0x00000000ff000000) RAM [0x00000000ff000000, 0x0000000000000000) Reserved [0x0000000000000000, 0x00000000be000000) RAM SELFBOOT RETURNED! Boot failed. ======================================================= ...and 2GB (1 stick): coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 starting... now booting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done core0 started: now booting... All core 0 started started ap apicid: SBLink=00 NC node|link=00 00entering optimize_link_incoherent_ht sysinfo->link_pair_num=0x1 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. pos=0x6e, unfiltered freq_cap=0x75 pos=0x6e, filtered freq_cap=0x75 Limiting HT to 800/600/400/200 MHz until K8M890 HT1000 is fixed. freq_cap1=0x35, freq_cap2=0x35 dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 after ht_optimize_link for link pair 0, reset_needed=0x0 after optimize_link_read_pointers_chain, reset_needed=0x0 00K8M890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change Current fid_cur: 0x2, fid_max: 0x12 Requested fid_new: 0x12 FidVid table step fidvid: 0xe FidVid table step fidvid: 0x10 200MHZ step fidvid: 0x12 Ram1.00 setting up CPU 00 northbridge registers done. Ram2.00 sdram_set_spd_registers: paramx :000ceee8 Device error Device error Device error Unbuffered 400MHz 400MHz Interleaved RAM end at 0x00200000 kB Ram3 IN TEST WAKEUP 800Initializing memory: done Setting variable MTRR 2, base: 0MB, range: 2048MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=1d done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce950 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 TrainDQSPos: MutualCSPassW[48] :000ce828 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=43 done DQS SAVE NVRAM: c2000 Writing 113222 of size 4 to nvram pos: 0 Writing 17161515 of size 4 to nvram pos: 4 Writing 17171615 of size 4 to nvram pos: 8 Writing 15 of size 1 to nvram pos: 12 Writing 202520 of size 4 to nvram pos: 13 Writing 17171918 of size 4 to nvram pos: 17 Writing 17191718 of size 4 to nvram pos: 21 Writing 17 of size 1 to nvram pos: 25 Writing 33 of size 1 to nvram pos: 26 Writing 0 of size 1 to nvram pos: 27 Writing 0 of size 1 to nvram pos: 28 Writing 0 of size 1 to nvram pos: 29 Writing 111222 of size 4 to nvram pos: 30 Writing 0 of size 4 to nvram pos: 34 Writing 0 of size 4 to nvram pos: 38 Writing 0 of size 1 to nvram pos: 42 Writing 0 of size 4 to nvram pos: 43 Writing 2f2f2f2f of size 4 to nvram pos: 47 Writing 2f2f2f2f of size 4 to nvram pos: 51 Writing 0 of size 1 to nvram pos: 55 Writing 43 of size 1 to nvram pos: 56 Writing 0 of size 1 to nvram pos: 57 Writing 0 of size 1 to nvram pos: 58 Writing 0 of size 1 to nvram pos: 59 Writing 741080ab of size 4 to nvram pos: 60 DQS Training:tsc[00]=000000005eac6acb DQS Training:tsc[01]=000000006087914d DQS Training:tsc[02]=0000000060879156 DQS Training:tsc[03]=00000000df309c2e DQS Training:tsc[04]=00000000f2a194b3 Ram4 v_esp=000cef28 testx = 5a5a5a5a IN TEST WAKEUP 800Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Searching for fallback/coreboot_ram Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (622592 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-2000-g91be49b-dirty Mon Feb 20 22:44:53 EST 2012 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 00:50: enabled 1 I2C: 00:51: enabled 1 I2C: 00:52: enabled 1 I2C: 00:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: Using configuration type 1 PCI: 00:00.0 [1106/0336] ops VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled Capability: type 0x02 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x08 @ 0x60 flags: 0x0060 PCI: 00:00.0 count: 0003 static_count: 0014 PCI: 00:00.0 [1106/0336] enabled next_unitid: 0014 PCI: pci_scan_bus for bus 00 VIA_X_0 device dump: 00: 06 11 36 03 00 00 10 22 00 00 00 06 00 00 80 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 80 63 08 00 00 00 00 00 01 00 1f c4 00 04 00 01 50: 01 60 02 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 08 58 60 00 20 00 11 11 d0 00 00 00 22 05 75 00 70: 02 00 00 00 00 00 00 00 00 00 00 00 08 00 00 00 80: 02 50 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 0f 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 08 00 00 98 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.0 [1106/0336] enabled PCI: 00:00.1 [1106/1336] ops K8x8xx: Enabling NB error reporting: Done VIA_X_1 device dump: 00: 06 11 36 13 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 81 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.1 [1106/1336] enabled PCI: 00:00.2 [1106/2336] ops PCI: 00:00.2 [1106/2336] enabled PCI: 00:00.3 [1106/3336] ops K8M890: UMA base is 7e000000 size is 32 (MB) VIA_X_3 device dump: 00: 06 11 36 33 06 00 00 02 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 22 22 00 00 00 00 e4 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: ff ff ff 30 00 80 19 00 80 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 80 00 00 00 00 3f 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:00.3 [1106/3336] enabled PCI: 00:00.4 [1106/4336] enabled PCI: 00:00.5 [1106/5336] ops PCI: 00:00.5 [1106/5336] enabled PCI: 00:00.6 [1106/6290] enabled PCI: 00:00.7 [1106/7336] ops PCI: 00:00.7 [1106/7336] enabled PCI: 00:01.0 [1106/b188] bus ops B188 device dump 00: 06 11 88 b1 07 00 30 02 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 20 02 20: f0 ff 00 00 f0 ff 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 70 00 00 00 00 00 00 00 00 00 16 00 40: 91 40 08 44 31 3a 88 b1 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 0e 70 35 00 0b 0a 00 1f 00 00 00 00 28 00 00 00 90: 80 00 00 00 00 08 01 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 80 63 08 00 00 00 00 00 00 00 1f c4 00 04 00 00 c0: 08 00 0b ff 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:01.0 [1106/b188] enabled PCI: 00:02.0 [1106/a238] bus ops Configuring PCIe PEG 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c 12 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 07 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 PCIe link timeout 00: 06 11 38 a2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0e 00 00 00 00 10 00 01 0d 10 00 50: 00 00 01 00 60 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 c3 a0: 01 04 00 00 7c 00 00 00 00 00 00 00 00 00 00 00 b0: 0c f0 40 81 00 00 03 00 01 00 00 00 00 00 00 00 c0: 03 00 27 00 44 44 44 44 44 44 44 44 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 0c 0b 81 9a f8 00 00 00 81 82 f8 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:02.0 [1106/a238] enabled PCI: 00:03.0 [1106/c238] bus ops Configuring PCIe PEXs 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b 59 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 PCIe link up after 15000 us 00: 06 11 38 c2 00 00 10 00 00 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00 40: 10 68 41 01 01 0f 00 00 00 00 10 00 11 0c 10 01 50: 00 00 11 20 60 00 00 00 00 00 48 00 00 00 00 00 60: 00 00 00 00 00 00 00 00 01 70 22 c8 00 00 00 00 70: 05 dc 80 01 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 0d 00 00 00 06 11 36 d3 a0: 01 04 00 00 5c 00 00 00 00 00 00 00 00 00 00 00 b0: 3b f0 40 81 00 00 03 00 00 00 00 00 00 00 00 00 c0: 03 00 27 8a 44 44 00 00 00 00 00 00 00 00 00 00 d0: 50 00 00 00 02 00 00 00 00 00 00 00 08 00 02 a8 e0: 00 0b 01 9a f8 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 06 00 00 00 00 00 00 00 00 00 00 00 00 PCI: 00:03.0 [1106/c238] enabled PCI: 00:0f.0 [1106/0591] ops PCI: 00:0f.0 [1106/0591] enabled PCI: 00:0f.1 [1106/0571] ops PCI: 00:0f.1 [1106/0571] enabled PCI: 00:10.0 [1106/3038] ops PCI: 00:10.0 [1106/3038] enabled PCI: 00:10.1 [1106/3038] ops PCI: 00:10.1 [1106/3038] enabled PCI: 00:10.2 [1106/3038] ops PCI: 00:10.2 [1106/3038] enabled PCI: 00:10.3 [1106/3038] ops PCI: 00:10.3 [1106/3038] enabled PCI: 00:10.4 [1106/3104] ops PCI: 00:10.4 [1106/3104] enabled PCI: 00:11.0 [1106/3337] bus ops PCI: 00:11.0 [1106/3337] enabled PCI: 00:11.7 [1106/287e] ops PCI: 00:11.7 [1106/287e] enabled Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.0 [1106/337b] enabled Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 Capability: type 0x08 @ 0x60 Capability: type 0x0d @ 0x70 PCI: 00:13.1 [1106/337a] enabled do_pci_scan_bridge for PCI: 00:01.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1106/3230] ops PCI: 01:00.0 [1106/3230] enabled PCI: pci_scan_bus returning with max=001 do_pci_scan_bridge returns max 1 do_pci_scan_bridge for PCI: 00:02.0 PCI: pci_scan_bus for bus 02 PCI: pci_scan_bus returning with max=002 do_pci_scan_bridge returns max 2 do_pci_scan_bridge for PCI: 00:03.0 PCI: pci_scan_bus for bus 03 PCI: 03:00.0 [197b/2363] enabled PCI: pci_scan_bus returning with max=003 Capability: type 0x01 @ 0x68 Capability: type 0x10 @ 0x50 do_pci_scan_bridge returns max 3 scan_static_bus for PCI: 00:11.0 smbus: PCI: 00:11.0[0]->I2C: 01:50 enabled smbus: PCI: 00:11.0[0]->I2C: 01:51 enabled smbus: PCI: 00:11.0[0]->I2C: 01:52 enabled smbus: PCI: 00:11.0[0]->I2C: 01:53 enabled PNP: 002e.0 enabled PNP: 002e.1 enabled PNP: 002e.2 disabled PNP: 002e.3 enabled PNP: 002e.4 enabled PNP: 002e.5 disabled PNP: 002e.6 disabled PNP: 002e.7 disabled PNP: 002e.8 disabled PNP: 002e.9 disabled PNP: 002e.a disabled scan_static_bus for PCI: 00:11.0 done do_pci_scan_bridge for PCI: 00:13.0 PCI: pci_scan_bus for bus 04 PCI: 04:01.0 [1106/3288] enabled PCI: pci_scan_bus returning with max=004 do_pci_scan_bridge returns max 4 do_pci_scan_bridge for PCI: 00:13.1 PCI: pci_scan_bus for bus 05 PCI: pci_scan_bus returning with max=005 do_pci_scan_bridge returns max 5 PCI: pci_scan_bus returning with max=005 PCI: pci_scan_bus returning with max=005 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Setting up VGA for PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 VGA: PCI: 00:18.0 (aka node 0) link 0 has VGA device PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done PCI: 00:02.0 read_resources bus 2 link: 0 PCI: 00:02.0 read_resources bus 2 link: 0 done PCI: 00:03.0 read_resources bus 3 link: 0 PCI: 00:03.0 read_resources bus 3 link: 0 done PCI: 00:11.0 read_resources bus 1 link: 0 I2C: 01:50 missing read_resources I2C: 01:51 missing read_resources I2C: 01:52 missing read_resources I2C: 01:53 missing read_resources PCI: 00:11.0 read_resources bus 1 link: 0 done PCI: 00:13.0 read_resources bus 4 link: 0 PCI: 00:13.0 read_resources bus 4 link: 0 done PCI: 00:13.1 read_resources bus 5 link: 0 PCI: 00:13.1 read_resources bus 5 link: 0 done PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base fc0003 size 0 align 0 gran 0 limit ffff00 flags 1 index 1b8 PCI: 00:18.0 resource base 3 size 0 align 0 gran 0 limit 1fff000 flags 1 index 1c0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 0 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80200 index 1 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags c0000200 index 4 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 10000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10 PCI: 01:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 14 PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 03:00.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 03:00.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 03:00.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 03:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:0f.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:0f.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags c0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:13.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 200 index 94 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 03:00.0 20 * [0x0 - 0xf] io PCI: 03:00.0 10 * [0x10 - 0x17] io PCI: 03:00.0 18 * [0x18 - 0x1f] io PCI: 03:00.0 14 * [0x20 - 0x23] io PCI: 03:00.0 1c * [0x24 - 0x27] io PCI: 00:03.0 compute_resources_io: base: 28 size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff PCI: 00:13.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:03.0 1c * [0x0 - 0xfff] io PCI: 00:0f.0 24 * [0x1000 - 0x10ff] io PCI: 00:10.0 20 * [0x1400 - 0x141f] io PCI: 00:10.1 20 * [0x1420 - 0x143f] io PCI: 00:10.2 20 * [0x1440 - 0x145f] io PCI: 00:10.3 20 * [0x1460 - 0x147f] io PCI: 00:0f.0 20 * [0x1480 - 0x148f] io PCI: 00:0f.1 20 * [0x1490 - 0x149f] io PCI: 00:0f.0 10 * [0x14a0 - 0x14a7] io PCI: 00:0f.0 18 * [0x14a8 - 0x14af] io PCI: 00:0f.0 14 * [0x14b0 - 0x14b3] io PCI: 00:0f.0 1c * [0x14b4 - 0x14b7] io PCI: 00:18.0 compute_resources_io: base: 14b8 size: 2000 align: 12 gran: 12 limit: ffff done PCI: 00:18.0 00 * [0x0 - 0x1fff] io PCI_DOMAIN: 0000 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff PCI: 00:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 compute_resources_prefmem: base: 10000000 size: 10000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:13.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:00.0 10 * [0x0 - 0xfffffff] prefmem PCI: 00:01.0 24 * [0x10000000 - 0x1fffffff] prefmem PCI: 00:18.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 14 * [0x0 - 0xffffff] mem PCI: 01:00.0 30 * [0x1000000 - 0x100ffff] mem PCI: 00:01.0 compute_resources_mem: base: 1010000 size: 1100000 align: 24 gran: 20 limit: ffffffff done PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 03:00.0 30 * [0x0 - 0xffff] mem PCI: 03:00.0 24 * [0x10000 - 0x11fff] mem PCI: 00:03.0 compute_resources_mem: base: 12000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 04:01.0 10 * [0x0 - 0x3fff] mem PCI: 00:13.0 compute_resources_mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 00:13.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done PCI: 00:00.5 61 * [0x0 - 0xfffffff] mem PCI: 00:01.0 20 * [0x10000000 - 0x110fffff] mem PCI: 00:03.0 20 * [0x11100000 - 0x111fffff] mem PCI: 00:13.0 20 * [0x11200000 - 0x112fffff] mem PCI: 00:10.4 10 * [0x11300000 - 0x113000ff] mem PCI: 00:18.0 compute_resources_mem: base: 11300100 size: 11400000 align: 28 gran: 20 limit: ffffffff done PCI: 00:18.0 02 * [0x0 - 0x1fffffff] prefmem PCI: 00:18.0 01 * [0x20000000 - 0x313fffff] mem PCI: 00:18.3 94 * [0x34000000 - 0x37ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 38000000 size: 38000000 align: 28 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:00.1 constrain_resources: PCI: 00:00.2 constrain_resources: PCI: 00:00.3 constrain_resources: PCI: 00:00.4 constrain_resources: PCI: 00:00.5 constrain_resources: PCI: 00:00.6 constrain_resources: PCI: 00:00.7 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 01:00.0 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 constrain_resources: PCI: 03:00.0 constrain_resources: PCI: 00:0f.0 constrain_resources: PCI: 00:0f.1 constrain_resources: PCI: 00:10.0 constrain_resources: PCI: 00:10.1 constrain_resources: PCI: 00:10.2 constrain_resources: PCI: 00:10.3 constrain_resources: PCI: 00:10.4 constrain_resources: PCI: 00:11.0 constrain_resources: I2C: 01:50 constrain_resources: I2C: 01:51 constrain_resources: I2C: 01:52 constrain_resources: I2C: 01:53 constrain_resources: PNP: 002e.0 constrain_resources: PNP: 002e.1 constrain_resources: PNP: 002e.3 constrain_resources: PNP: 002e.4 constrain_resources: PCI: 00:11.7 constrain_resources: PCI: 00:13.0 constrain_resources: PCI: 04:01.0 constrain_resources: PCI: 00:13.1 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 000c0000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2000 align:12 gran:0 limit:ffff Assigned: PCI: 00:18.0 00 * [0x1000 - 0x2fff] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3000 size: 2000 align: 12 gran: 0 done PCI: 00:18.0 allocate_resources_io: base:1000 size:2000 align:12 gran:12 limit:ffff Assigned: PCI: 00:03.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:0f.0 24 * [0x2000 - 0x20ff] io Assigned: PCI: 00:10.0 20 * [0x2400 - 0x241f] io Assigned: PCI: 00:10.1 20 * [0x2420 - 0x243f] io Assigned: PCI: 00:10.2 20 * [0x2440 - 0x245f] io Assigned: PCI: 00:10.3 20 * [0x2460 - 0x247f] io Assigned: PCI: 00:0f.0 20 * [0x2480 - 0x248f] io Assigned: PCI: 00:0f.1 20 * [0x2490 - 0x249f] io Assigned: PCI: 00:0f.0 10 * [0x24a0 - 0x24a7] io Assigned: PCI: 00:0f.0 18 * [0x24a8 - 0x24af] io Assigned: PCI: 00:0f.0 14 * [0x24b0 - 0x24b3] io Assigned: PCI: 00:0f.0 1c * [0x24b4 - 0x24b7] io PCI: 00:18.0 allocate_resources_io: next_base: 24b8 size: 2000 align: 12 gran: 12 done PCI: 00:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff Assigned: PCI: 03:00.0 20 * [0x1000 - 0x100f] io Assigned: PCI: 03:00.0 10 * [0x1010 - 0x1017] io Assigned: PCI: 03:00.0 18 * [0x1018 - 0x101f] io Assigned: PCI: 03:00.0 14 * [0x1020 - 0x1023] io Assigned: PCI: 03:00.0 1c * [0x1024 - 0x1027] io PCI: 00:03.0 allocate_resources_io: next_base: 1028 size: 1000 align: 12 gran: 12 done PCI: 00:13.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:13.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:13.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:38000000 align:28 gran:0 limit:febfffff Assigned: PCI: 00:18.0 02 * [0xc0000000 - 0xdfffffff] prefmem Assigned: PCI: 00:18.0 01 * [0xe0000000 - 0xf13fffff] mem Assigned: PCI: 00:18.3 94 * [0xf4000000 - 0xf7ffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f8000000 size: 38000000 align: 28 gran: 0 done PCI: 00:18.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.0 10 * [0xc0000000 - 0xcfffffff] prefmem Assigned: PCI: 00:01.0 24 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:18.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_prefmem: base:d0000000 size:10000000 align:28 gran:20 limit:febfffff Assigned: PCI: 01:00.0 10 * [0xd0000000 - 0xdfffffff] prefmem PCI: 00:01.0 allocate_resources_prefmem: next_base: e0000000 size: 10000000 align: 28 gran: 20 done PCI: 00:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:18.0 allocate_resources_mem: base:e0000000 size:11400000 align:28 gran:20 limit:febfffff Assigned: PCI: 00:00.5 61 * [0xe0000000 - 0xefffffff] mem Assigned: PCI: 00:01.0 20 * [0xf0000000 - 0xf10fffff] mem Assigned: PCI: 00:03.0 20 * [0xf1100000 - 0xf11fffff] mem Assigned: PCI: 00:13.0 20 * [0xf1200000 - 0xf12fffff] mem Assigned: PCI: 00:10.4 10 * [0xf1300000 - 0xf13000ff] mem PCI: 00:18.0 allocate_resources_mem: next_base: f1300100 size: 11400000 align: 28 gran: 20 done PCI: 00:01.0 allocate_resources_mem: base:f0000000 size:1100000 align:24 gran:20 limit:febfffff Assigned: PCI: 01:00.0 14 * [0xf0000000 - 0xf0ffffff] mem Assigned: PCI: 01:00.0 30 * [0xf1000000 - 0xf100ffff] mem PCI: 00:01.0 allocate_resources_mem: next_base: f1010000 size: 1100000 align: 24 gran: 20 done PCI: 00:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done PCI: 00:03.0 allocate_resources_mem: base:f1100000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 03:00.0 30 * [0xf1100000 - 0xf110ffff] mem Assigned: PCI: 03:00.0 24 * [0xf1110000 - 0xf1111fff] mem PCI: 00:03.0 allocate_resources_mem: next_base: f1112000 size: 100000 align: 20 gran: 20 done PCI: 00:13.0 allocate_resources_mem: base:f1200000 size:100000 align:20 gran:20 limit:febfffff Assigned: PCI: 04:01.0 10 * [0xf1200000 - 0xf1203fff] mem PCI: 00:13.0 allocate_resources_mem: next_base: f1204000 size: 100000 align: 20 gran: 20 done PCI: 00:13.1 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff PCI: 00:13.1 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 node 0 : uma_memory_base/1024=0x001f8000, mmio_basek=0x00300000, basek=0x00000300, limitk=0x00200000 node 0: UMA memory starts below mmio_basek 0: mmio_basek=00300000, basek=00000300, limitk=00200000 Adding UMA memory area PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 amdk8_set_resource, enabling legacy VGA IO forwarding for PCI: 00:18.0 link 0x0 PCI: 00:18.0 1c0 <- [0x0000001000 - 0x0000002fff] size 0x00002000 gran 0x0c io <node 0 link 0> PCI: 00:18.0 1b8 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 prefmem <node 0 link 0> PCI: 00:18.0 1b0 <- [0x00e0000000 - 0x00f13fffff] size 0x11400000 gran 0x14 mem <node 0 link 0> PCI: 00:18.0 1a8 <- [0x00000a0000 - 0x00000bffff] size 0x00020000 gran 0x00 mem <node 0 link 0> PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:00.0 10 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:01.0 24 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x14 bus 01 prefmem PCI: 00:01.0 20 <- [0x00f0000000 - 0x00f10fffff] size 0x01100000 gran 0x14 bus 01 mem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem PCI: 01:00.0 14 <- [0x00f0000000 - 0x00f0ffffff] size 0x01000000 gran 0x18 mem PCI: 01:00.0 30 <- [0x00f1000000 - 0x00f100ffff] size 0x00010000 gran 0x10 romem PCI: 00:01.0 assign_resources, bus 1 link: 0 PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 02 mem PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io PCI: 00:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 03 prefmem PCI: 00:03.0 20 <- [0x00f1100000 - 0x00f11fffff] size 0x00100000 gran 0x14 bus 03 mem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 03:00.0 10 <- [0x0000001010 - 0x0000001017] size 0x00000008 gran 0x03 io PCI: 03:00.0 14 <- [0x0000001020 - 0x0000001023] size 0x00000004 gran 0x02 io PCI: 03:00.0 18 <- [0x0000001018 - 0x000000101f] size 0x00000008 gran 0x03 io PCI: 03:00.0 1c <- [0x0000001024 - 0x0000001027] size 0x00000004 gran 0x02 io PCI: 03:00.0 20 <- [0x0000001000 - 0x000000100f] size 0x00000010 gran 0x04 io PCI: 03:00.0 24 <- [0x00f1110000 - 0x00f1111fff] size 0x00002000 gran 0x0d mem PCI: 03:00.0 30 <- [0x00f1100000 - 0x00f110ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 assign_resources, bus 3 link: 0 PCI: 00:0f.0 10 <- [0x00000024a0 - 0x00000024a7] size 0x00000008 gran 0x03 io PCI: 00:0f.0 14 <- [0x00000024b0 - 0x00000024b3] size 0x00000004 gran 0x02 io PCI: 00:0f.0 18 <- [0x00000024a8 - 0x00000024af] size 0x00000008 gran 0x03 io PCI: 00:0f.0 1c <- [0x00000024b4 - 0x00000024b7] size 0x00000004 gran 0x02 io PCI: 00:0f.0 20 <- [0x0000002480 - 0x000000248f] size 0x00000010 gran 0x04 io PCI: 00:0f.0 24 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 00:0f.1 20 <- [0x0000002490 - 0x000000249f] size 0x00000010 gran 0x04 io PCI: 00:10.0 20 <- [0x0000002400 - 0x000000241f] size 0x00000020 gran 0x05 io PCI: 00:10.1 20 <- [0x0000002420 - 0x000000243f] size 0x00000020 gran 0x05 io PCI: 00:10.2 20 <- [0x0000002440 - 0x000000245f] size 0x00000020 gran 0x05 io PCI: 00:10.3 20 <- [0x0000002460 - 0x000000247f] size 0x00000020 gran 0x05 io PCI: 00:10.4 10 <- [0x00f1300000 - 0x00f13000ff] size 0x00000100 gran 0x08 mem PCI: 00:11.0 assign_resources, bus 1 link: 0 PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq PNP: 002e.3 60 <- [0x0000000378 - 0x000000037f] size 0x00000008 gran 0x03 io PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq ERROR: PNP: 002e.3 74 drq size: 0x0000000001 not assigned PNP: 002e.4 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io PNP: 002e.4 62 <- [0x0000000230 - 0x0000000237] size 0x00000008 gran 0x03 io PNP: 002e.4 70 <- [0x0000000000 - 0x0000000000] size 0x00000001 gran 0x00 irq PCI: 00:11.0 assign_resources, bus 1 link: 0 PCI: 00:13.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io PCI: 00:13.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem PCI: 00:13.0 20 <- [0x00f1200000 - 0x00f12fffff] size 0x00100000 gran 0x14 bus 04 mem PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 04:01.0 10 <- [0x00f1200000 - 0x00f1203fff] size 0x00004000 gran 0x0e mem64 PCI: 00:13.0 assign_resources, bus 4 link: 0 PCI: 00:13.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io PCI: 00:13.1 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem PCI: 00:13.1 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00f4000000 - 0x00f7ffffff] size 0x04000000 gran 0x1a mem <gart> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 1000 size 2000 align 12 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base c0000000 size 38000000 align 28 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI_DOMAIN: 0000 resource base c0000 size 7df40000 align 0 gran 0 limit 0 flags e0004200 index 20 PCI_DOMAIN: 0000 resource base 7e000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 1000 size 2000 align 12 gran 12 limit ffff flags 60080100 index 1c0 PCI: 00:18.0 resource base c0000000 size 20000000 align 28 gran 20 limit febfffff flags 60081200 index 1b8 PCI: 00:18.0 resource base e0000000 size 11400000 align 28 gran 20 limit febfffff flags 60080200 index 1b0 PCI: 00:18.0 resource base a0000 size 20000 align 0 gran 0 limit ffffffff flags e0000200 index 1a8 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 00:00.1 PCI: 00:00.2 PCI: 00:00.3 PCI: 00:00.4 PCI: 00:00.5 PCI: 00:00.5 resource base fecc0000 size 100 align 8 gran 8 limit fecc00ff flags f0000200 index 40 PCI: 00:00.5 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 70000200 index 61 PCI: 00:00.6 PCI: 00:00.7 PCI: 00:01.0 child on link 0 PCI: 01:00.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base d0000000 size 10000000 align 28 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:01.0 resource base f0000000 size 1100000 align 24 gran 20 limit febfffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base d0000000 size 10000000 align 28 gran 28 limit febfffff flags 60001200 index 10 PCI: 01:00.0 resource base f0000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 14 PCI: 01:00.0 resource base f1000000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:02.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:03.0 child on link 0 PCI: 03:00.0 PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:03.0 resource base f1100000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 1010 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 03:00.0 resource base 1020 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 03:00.0 resource base 1018 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 03:00.0 resource base 1024 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 03:00.0 resource base 1000 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 03:00.0 resource base f1110000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 24 PCI: 03:00.0 resource base f1100000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:0f.0 PCI: 00:0f.0 resource base 24a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 PCI: 00:0f.0 resource base 24b0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 PCI: 00:0f.0 resource base 24a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 PCI: 00:0f.0 resource base 24b4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c PCI: 00:0f.0 resource base 2480 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:0f.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 24 PCI: 00:0f.1 PCI: 00:0f.1 resource base 2490 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:10.0 PCI: 00:10.0 resource base 2400 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.1 PCI: 00:10.1 resource base 2420 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.2 PCI: 00:10.2 resource base 2440 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.3 PCI: 00:10.3 resource base 2460 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 PCI: 00:10.4 PCI: 00:10.4 resource base f1300000 size 100 align 8 gran 8 limit febfffff flags 60000200 index 10 PCI: 00:11.0 child on link 0 I2C: 01:50 PCI: 00:11.0 resource base 500 size 80 align 0 gran 0 limit ffff flags f0000100 index 88 PCI: 00:11.0 resource base 4d0 size 2 align 0 gran 0 limit ffff flags f0000100 index 3 PCI: 00:11.0 resource base 400 size 10 align 0 gran 0 limit ffff flags f0000100 index d0 PCI: 00:11.0 resource base fec00000 size 100 align 8 gran 8 limit ffffffff flags f0000200 index 44 PCI: 00:11.0 resource base ff000000 size 1000000 align 0 gran 0 limit ffffffff flags f0000200 index 4 PCI: 00:11.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 I2C: 01:50 I2C: 01:51 I2C: 01:52 I2C: 01:53 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 PNP: 002e.1 PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.2 PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 PNP: 002e.3 PNP: 002e.3 resource base 378 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 PNP: 002e.4 PNP: 002e.4 resource base 290 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 PNP: 002e.4 resource base 230 size 8 align 3 gran 3 limit 7ff flags e0000100 index 62 PNP: 002e.4 resource base 0 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 PNP: 002e.5 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 62 PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.6 PNP: 002e.6 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.7 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 62 PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 64 PNP: 002e.8 PNP: 002e.8 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 60 PNP: 002e.8 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 PNP: 002e.9 PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 PNP: 002e.a PCI: 00:11.7 PCI: 00:12.0 PCI: 00:13.0 child on link 0 PCI: 04:01.0 PCI: 00:13.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.0 resource base f1200000 size 100000 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 04:01.0 PCI: 04:01.0 resource base f1200000 size 4000 align 14 gran 14 limit febfffff flags 60000201 index 10 PCI: 00:13.1 PCI: 00:13.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24 PCI: 00:13.1 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base f4000000 size 4000000 align 26 gran 26 limit febfffff flags 60000200 index 94 Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/0000 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/0000 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 PCI: 00:00.0 subsystem <- 1043/0000 PCI: 00:00.0 cmd <- 02 PCI: 00:00.1 cmd <- 06 PCI: 00:00.2 cmd <- 06 PCI: 00:00.3 cmd <- 06 PCI: 00:00.4 cmd <- 06 PCI: 00:00.5 cmd <- 06 PCI: 00:00.6 cmd <- 06 PCI: 00:00.7 cmd <- 06 PCI: 00:01.0 bridge ctrl <- 001f PCI: 00:01.0 cmd <- 07 PCI: 00:02.0 bridge ctrl <- 0003 PCI: 00:02.0 cmd <- 00 PCI: 00:03.0 bridge ctrl <- 0003 PCI: 00:03.0 cmd <- 07 PCI: 00:0f.0 cmd <- 01 PCI: 00:0f.1 cmd <- 01 PCI: 00:10.0 cmd <- 01 PCI: 00:10.1 cmd <- 01 PCI: 00:10.2 cmd <- 01 PCI: 00:10.3 cmd <- 01 PCI: 00:10.4 cmd <- 02 PCI: 00:11.0 subsystem <- 1043/0000 PCI: 00:11.0 cmd <- 01 PCI: 00:11.7 cmd <- 00 PCI: 00:13.0 bridge ctrl <- 0003 PCI: 00:13.0 cmd <- 07 PCI: 00:13.1 bridge ctrl <- 0003 PCI: 00:13.1 cmd <- 01 PCI: 01:00.0 cmd <- 03 PCI: 03:00.0 cmd <- 03 PCI: 04:01.0 cmd <- 02 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x00009000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 50ff3 CPU: family 0f, model 5f, stepping 03 Enabling cache CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Setting variable MTRR 1, base: 2016MB, range: 32MB, type UC ADDRESS_MASK_HIGH=0xff DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled CPU model AMD Athlon(tm) 64 Processor 4000+ Setting up local apic... apic_id: 0x00 done. Scrubbing Disabled ECC Disabled CPU #0 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:18.1 init Searching for pci1022,1101.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1101.rom'. PCI: 00:18.2 init Searching for pci1022,1102.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1022,1102.rom'. PCI: 00:18.3 init NB: Function 3 Misc Control.. done. PCI: 00:00.0 init PCI: 00:00.3 init K8M890: Using a 32MB framebuffer. PCI: 00:00.4 init Searching for pci1106,4336.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,4336.rom'. PCI: 00:00.6 init Searching for pci1106,6290.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,6290.rom'. PCI: 00:00.7 init K8x8xx: Initializing V-Link to VT8237R sb: VT8237R LPC not found ! PCI: 00:0f.0 init Configuring VIA SATA controller PCI: 00:0f.1 init Primary IDE interface enabled Secondary IDE interface enabled Enables in reg 0x40 read back as 0xb Enables in reg 0x42 read back as 0x9 PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:10.4 init PCI: 00:11.0 init SLP_TYP type was 800 0 RTC Init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: 23 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 00: 06 11 37 33 01 00 10 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 43 10 00 00 30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 40: 44 7f f8 0b 00 00 00 00 0c 20 00 00 44 00 00 08 50: c0 0d 09 00 00 00 00 00 43 80 00 0b 00 00 00 00 60: 00 00 00 00 00 00 00 04 80 00 d0 fe 80 00 00 00 70: 43 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 20 84 49 00 b2 30 00 00 01 05 00 00 05 18 00 00 90: 00 06 19 88 a0 cc 00 00 00 3a 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 04 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 08 00 24 69 10 80 00 00 00 00 04 00 00 00 f0: 00 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00 PCI: 00:11.7 init 00: 06 11 7e 28 00 00 10 22 00 00 00 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 06 11 7e 33 30: 00 00 00 00 58 00 00 00 00 00 00 00 00 00 00 00 40: f4 24 00 80 82 00 00 00 23 3b 88 80 82 44 00 43 50: 00 03 33 03 00 04 01 80 08 00 01 80 00 00 00 00 60: 00 ff ff 30 30 00 00 00 00 00 00 00 00 00 00 00 70: c2 c8 ee 01 3c 0f 50 48 01 00 00 00 77 00 00 12 80: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: fd 3f df 00 00 00 00 e0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 50 ee 88 8a 88 00 03 00 00 c0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 19 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 b0 00 00 00 PCI: 01:00.0 init Chrome: Using 32MB Framebuffer at 0xD0000000. Chrome VGA Textmode initialized. PCI: 03:00.0 init Searching for pci197b,2363.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci197b,2363.rom'. On card, ROM address for PCI: 03:00.0 = f1100000 PCI expansion ROM, signature 0x7f7f, INIT size 0xfe00, data ptr 0x7f7f Incorrect expansion ROM header signature 7f7f PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.3 init PNP: 002e.4 init FAN_CTL: reg = 0x02a9, read value = 0x50 FAN_CTL: reg = 0x02a9, writing value = 0xd7 PCI: 04:01.0 init Searching for pci1106,3288.rom Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Check config Check ERROR: No file header found at fffffc00, attempting to recover by searching for header Could not find file 'pci1106,3288.rom'. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:0f.1: enabled 1 PCI: 00:11.0: enabled 1 I2C: 01:50: enabled 1 I2C: 01:51: enabled 1 I2C: 01:52: enabled 1 I2C: 01:53: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 0 PNP: 002e.3: enabled 1 PNP: 002e.4: enabled 1 PNP: 002e.5: enabled 0 PNP: 002e.6: enabled 0 PNP: 002e.7: enabled 0 PNP: 002e.8: enabled 0 PNP: 002e.9: enabled 0 PNP: 002e.a: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:13.0: enabled 1 PCI: 00:13.1: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:00.1: enabled 1 PCI: 00:00.2: enabled 1 PCI: 00:00.3: enabled 1 PCI: 00:00.4: enabled 1 PCI: 00:00.5: enabled 1 PCI: 00:00.6: enabled 1 PCI: 00:00.7: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:0f.0: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:10.1: enabled 1 PCI: 00:10.2: enabled 1 PCI: 00:10.3: enabled 1 PCI: 00:10.4: enabled 1 PCI: 00:11.7: enabled 1 PCI: 01:00.0: enabled 1 PCI: 03:00.0: enabled 1 PCI: 04:01.0: enabled 1 cbmem_initialize: acpi_slp_type=0 Initializing CBMEM area to 0x7def0000 (1114112 bytes) Adding CBMEM entry as no. 1 Moving GDT to 7def0200...ok High Tables Base is 7def0000. Adding CBMEM entry as no. 2 ACPI: Writing ACPI tables at 7def0400... ACPI: * FACS ACPI: * DSDT @ 7def0540 Length ba5 ACPI: * FADT ACPI: added table 1/32, length now 40 ACPI: * HPET ACPI: added table 2/32, length now 44 ACPI: * MADT ACPI: added table 3/32, length now 48 ACPI: * MCFG ACPI: added table 4/32, length now 52 ACPI: * SRAT SRAT: lapic cpu_index=00, node_id=00, apic_id=00 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 set_srat_mem: dev PCI_DOMAIN: 0000, res->index=0020 startk=00000300, sizek=001f7d00 ACPI: added table 5/32, length now 56 ACPI: * SLIT ACPI: added table 6/32, length now 60 ACPI: * SSDT processor_brand=AMD Athlon(tm) 64 Processor 4000+ Pstates Algorithm ... Pstate_freq[0] = 2600MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw Pstate_freq[1] = 2400MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 566975mw Pstate_freq[2] = 2200MHz Pstate_vid[2] = 12 Pstate_volt[2] = 1250mv Pstate_power[2] = 480516mw Pstate_freq[3] = 2000MHz Pstate_vid[3] = 14 Pstate_volt[3] = 1200mv Pstate_power[3] = 402585mw Pstate_freq[4] = 1000MHz Pstate_vid[4] = 18 Pstate_volt[4] = 1100mv Pstate_power[4] = 169141mw ACPI: added table 7/32, length now 64 ACPI: done. ACPI tables: 4677 bytes. Adding CBMEM entry as no. 3 smbios_write_tables: 7defb800 Root Device (ASUS M2V-MX Mainboard) APIC_CLUSTER: 0 (AMD K8 Root Complex) APIC: 00 (Socket AM2 CPU) PCI_DOMAIN: 0000 (AMD K8 Root Complex) PCI: 00:18.0 (AMD K8 Northbridge) PCI: 00:00.0 (VIA VT8237R Southbridge) PCI: 00:0f.1 (VIA VT8237R Southbridge) PCI: 00:11.0 (VIA VT8237R Southbridge) I2C: 01:50 () I2C: 01:51 () I2C: 01:52 () I2C: 01:53 () PNP: 002e.0 (ITE IT8716F Super I/O) PNP: 002e.1 (ITE IT8716F Super I/O) PNP: 002e.2 (ITE IT8716F Super I/O) PNP: 002e.3 (ITE IT8716F Super I/O) PNP: 002e.4 (ITE IT8716F Super I/O) PNP: 002e.5 (ITE IT8716F Super I/O) PNP: 002e.6 (ITE IT8716F Super I/O) PNP: 002e.7 (ITE IT8716F Super I/O) PNP: 002e.8 (ITE IT8716F Super I/O) PNP: 002e.9 (ITE IT8716F Super I/O) PNP: 002e.a (ITE IT8716F Super I/O) PCI: 00:12.0 (VIA VT8237R Southbridge) PCI: 00:13.0 (VIA VT8237R Southbridge) PCI: 00:13.1 (VIA VT8237R Southbridge) PCI: 00:18.1 (AMD K8 Northbridge) PCI: 00:18.2 (AMD K8 Northbridge) PCI: 00:18.3 (AMD K8 Northbridge) PCI: 00:00.1 () PCI: 00:00.2 () PCI: 00:00.3 () PCI: 00:00.4 () PCI: 00:00.5 () PCI: 00:00.6 () PCI: 00:00.7 () PCI: 00:01.0 () PCI: 00:02.0 () PCI: 00:03.0 () PCI: 00:0f.0 () PCI: 00:10.0 () PCI: 00:10.1 () PCI: 00:10.2 () PCI: 00:10.3 () PCI: 00:10.4 () PCI: 00:11.7 () PCI: 01:00.0 () PCI: 03:00.0 () PCI: 04:01.0 () SMBIOS tables: 277 bytes. Adding CBMEM entry as no. 4 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum c1ee New low_table_end: 0x00000518 Now going to write high coreboot table at 0x7defc000 rom_table_end = 0x7defc000 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x7defc000 to 0x7df00000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-000000007deeffff: RAM 3. 000000007def0000-000000007dffffff: CONFIGURATION TABLES 4. 000000007e000000-000000007fffffff: RESERVED 5. 00000000e0000000-00000000efffffff: RESERVED 6. 00000000fec00000-00000000fec000ff: RESERVED 7. 00000000fecc0000-00000000fecc00ff: RESERVED 8. 00000000ff000000-00000000ffffffff: RESERVED Wrote coreboot table at: 7defc000 - 7defc214 checksum 336b coreboot table: 532 bytes. Adding CBMEM entry as no. 5 Multiboot Information structure has been written. 0. FREE SPACE 7dffe000 00002000 1. GDT 7def0200 00000200 2. ACPI 7def0400 0000b400 3. SMBIOS 7defb800 00000800 4. COREBOOT 7defc000 00002000 5. ACPI RESUME7defe000 00100000 Searching for fallback/payload Check cmos_layout.bin Check pci1106,3230.rom Check fallback/romstage Check fallback/coreboot_ram Check fallback/payload Got a payload Loading segment from rom address 0xfffad538 data (compression=1) New segment dstaddr 0xe6b54 memsize 0x194ac srcaddr 0xfffad570 filesize 0xc8aa (cleaned up) New segment addr 0xe6b54 size 0x194ac offset 0xfffad570 filesize 0xc8aa Loading segment from rom address 0xfffad554 Entry Point 0x00000000 Loading Segment: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: 0x000000000000c8aa lb: [0x0000000000100000, 0x0000000000198000) Post relocation: addr: 0x00000000000e6b54 memsz: 0x00000000000194ac filesz: 0x000000000000c8aa using LZMA [ 0x000e6b54, 00100000, 0x00100000) <- fffad570 dest 000e6b54, end 00100000, bouncebuffer 7ddc0000 Loaded segments Jumping to boot code at fc8e4 entry = 0x000fc8e4 lb_start = 0x00100000 lb_size = 0x00098000 adjust = 0x7dd58000 buffer = 0x7ddc0000 elf_boot_notes = 0x001270c8 adjusted_boot_notes = 0x7de7f0c8 Start bios (version 1.6.3-20120215_224505-debby) Found mainboard ASUS M2V-MX Found CBFS header at 0xfffffc00 Ram Size=0x7def0000 (0x0000000000000000 high) Relocating init from 0x000e7340 to 0x7ded5190 (size 44356) CPU Mhz=2603 Found 29 PCI devices (max PCI bus is 05) Found 1 cpu(s) max supported 1 cpu(s) Copying ACPI RSDP from 0x7def0400 to 0x000fdb40 Copying SMBIOS entry point from 0x7defb800 to 0x000fdb20 Scan for VGA option rom Running option rom at c000:0003 Turning on vga text mode console SeaBIOS (version 1.6.3-20120215_224505-debby) EHCI init on dev 00:10.4 (regs=0xf1300010) Found 1 lpt ports Found 1 serial ports ATA controller 1 at 24a0/24b0/0 (irq 0 dev 78) ATA controller 2 at 24a8/24b4/0 (irq 0 dev 78) ATA controller 3 at 1f0/3f4/0 (irq 14 dev 79) ATA controller 4 at 170/374/0 (irq 15 dev 79) ebda moved from 9fc00 to 9f400 AHCI controller at 60.0, iobase f1110000, irq 0 UHCI init on dev 00:10.0 (io=2400) UHCI init on dev 00:10.1 (io=2420) UHCI init on dev 00:10.2 (io=2440) UHCI init on dev 00:10.3 (io=2460) AHCI/0: link down AHCI/1: link down DVD/CD [ata1-0: PLDS DVD+/-RW DH-16AAS ATAPI-8 DVD/CD] Searching bootorder for: /pci@i0cf8/*@f/drive@1/disk@0 Got ps2 nak (status=d1) ebda moved from 9f400 to 9f000 USB keyboard initialized ata0-0: Hitachi HDT721010SLA360 ATA-8 Hard-Disk (931 GiBytes) Searching bootorder for: /pci@i0cf8/*@f/drive@0/disk@0 All threads complete. Scan for option roms Press F12 for boot menu. drive 0x000fda60: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168 Returned 53248 bytes of ZoneHigh e820 map has 9 items: 0: 0000000000000000 - 000000000009f000 = 1 RAM 1: 000000000009f000 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007deed000 = 1 RAM 4: 000000007deed000 - 0000000080000000 = 2 RESERVED 5: 00000000e0000000 - 00000000f0000000 = 2 RESERVED 6: 00000000fec00000 - 00000000fec00100 = 2 RESERVED 7: 00000000fecc0000 - 00000000fecc0100 = 2 RESERVED 8: 00000000ff000000 - 0000000100000000 = 2 RESERVED enter handle_19: NULL Booting from DVD/CD... 606MB medium detected Booting from 0000:7c00

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Patch set updated for coreboot: 15e268e Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
by Marc Jones 21 Feb '12

21 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670 -gerrit commit 15e268ee435d7d6f8d76997336efb38c4732042e Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); - print_t(" ECCInit 2 \n"); - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ /* Reset MC4_STS. */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -212,12 +208,22 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /*Node has Dram */ } /*if Node present */ } - print_t(" ECCInit 3 \n"); if(mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..d126a95 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6107e80 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + printk(BIOS_DEBUG, " ECC enabled on node: %02x\n", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + printk(BIOS_DEBUG, "ECCInit: Node %02x\n", Node); + printk(BIOS_DEBUG, "ECCInit: Status %x\n", pDCTstat->Status); + printk(BIOS_DEBUG, "ECCInit: ErrStatus %x\n", pDCTstat->ErrStatus); + printk(BIOS_DEBUG, "ECCInit: ErrCode %x\n", pDCTstat->ErrCode); + printk(BIOS_DEBUG, "ECCInit: Done\n"); + } + } return MemClrECC; }

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coreboot February 2012