coreboot February 2012

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348 discussions

Patch merged into coreboot/master: 95aad86 Fixes Fam10/SR5650 cpu not recognized message.
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 95aad867212c87fde722934a536e14ca78f0c9f9 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 15:08:22 2012 -0700 Fixes Fam10/SR5650 cpu not recognized message. Extend the Family10 revisions checked byt the printk message. Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 02:14:04 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 23:29:37 2012, giving +2 See http://review.coreboot.org/633 for details. -gerrit

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Patch merged into coreboot/master: 25ccaa5 IEI-Kino Fam10 MPtable fix.
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 25ccaa54982ced9c697f58dc978a0d252763e766 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 13:38:50 2012 -0700 IEI-Kino Fam10 MPtable fix. Make changes to MPtable to match the ACPI tables. Change-Id: Icc18c9a25695d01d88d6ee5367064d527cc42bc1 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 01:30:33 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 23:26:55 2012, giving +2 See http://review.coreboot.org/629 for details. -gerrit

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Patch merged into coreboot/master: 41897bc IEI Kino Fam10 ACPI table fixes.
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 41897bc521632641b9b9053a73caa9d828019bba Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 14:07:43 2012 -0700 IEI Kino Fam10 ACPI table fixes. Fix the ACPI IRQ routing. Also, fix the SSDT generations and TOM2 fixup. Change-Id: Ica4a992d11bab63a510238dcd468b9fe80136def Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 01:19:20 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 23:26:47 2012, giving +2 See http://review.coreboot.org/628 for details. -gerrit

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one of those please - reports...
by 3days 18 Feb '12

18 Feb '12

miro:~/sysinfo# msrtool > msrtool.log msrtool 4091 Detected target K8: AMD K8 Family Unable to detect the current operating system! On Linux, please do 'modprobe msr' and retry. Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help! miro:~/sysinfo# modprobe msr WARNING: All config files need .conf: /etc/modprobe.d/kqemu, it will be ignored in a future release. WARNING: All config files need .conf: /etc/modprobe.d/OLD_oss-compat, it will be ignored in a future release. WARNING: All config files need .conf: /etc/modprobe.d/OLD_linux-sound-base_noOSS, it will be ignored in a future release. miro:~/sysinfo# msrtool > msrtool.log msrtool 4091 Detected system linux: Linux with /dev/cpu/*/msr Detected target K8: AMD K8 Family Debian Linux OS: Linux miro 3.2.0-1-amd64 #1 SMP Sun Feb 5 15:17:15 UTC 2012 x86_64 GNU/Linux miro:~/sysinfo# cat msrtool.log syntax: msrtool [-hvqrkl] [-c cpu] [-m system] [-t target ...] [-i addr=hi[:]lo] | [-s file] | [-d [:]file] | addr... -h show this help text -v be verbose -q be quiet (overrides -v) -r include [Reserved] values -k list all known systems and targets -l list MSRs and bit fields for current target(s) (-kl for ALL targets!) -c access MSRs on the specified CPU, default=0 -m force a system, e.g: -m linux -t force a target, can be used multiple times, e.g: -t geodelx -t cs5536 -i immediate mode decode hex addr=hi:lo for the target without reading hw value e.g: -i 4c00000f=f2f100ff56960004 -s stream mode read one MSR address per line and append current hw value to the line use the filename - for stdin/stdout using -l -s ignores input and will output all MSRs with values -d diff mode read one address and value per line and compare with current hw value, printing differences to stdout. use the filename - to read from stdin use :file or :- to reverse diff, normally hw values are considered new addr.. direct mode, read and decode values for the given MSR address(es) No mode or address(es) specified!

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Patch set updated for coreboot: 09e71a9 Intel model_6ex: apply some good programming practices in CAR
by Kyösti Mälkki 18 Feb '12

18 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643 -gerrit commit 09e71a9782e7687ac0c769f141fd1ac1b05c3844 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Feb 18 14:35:03 2012 +0200 Intel model_6ex: apply some good programming practices in CAR Replace cryptic 32bit hex values with existing LAPIC definitions. Do not assume state of direction flag before "rep" instruction. Do not load immediate values on temporary registers when not needed. Parameter pushed on stack was not popped (or flushed) after returning from call. This is a sort-of memory leak if multiple call's are implemented the same way. Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_6ex/cache_as_ram.inc | 23 +++++++++++++---------- 1 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index cbfa4f8..5a29744 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -21,6 +21,10 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/lapic_def.h> + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) @@ -37,9 +41,9 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -91,11 +95,10 @@ clear_mtrrs: movl %eax, %cr0 /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ @@ -130,11 +133,10 @@ clear_mtrrs: /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -145,6 +147,7 @@ clear_mtrrs: /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f)

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Patchwork/Django anti-spam cleanup script
by Carl-Daniel Hailfinger 18 Feb '12

18 Feb '12

In case you ever want to clean a Patchwork instance of spam registrations and assuming that nothing on your site besides Patchwork uses Django, try the following script which should kill a majority of spam accounts. Disclaimer: This script is an absolutely gross 5-minute hack, and it should remove all inactive accounts with all associated data. If you deactivated real users, they will vanish as well. I wrote this killer script after I noticed that 99% of the spam accounts in coreboot patchwork were inactive. License of this script is WTFPL 2.0 # use w3m to log in to patchwork for ((i=0; i<1980; i++)); do w3m -cookie http://patchwork.yoursite.org/admin/auth/user/$i -dump|grep "Active\|Date\|Time" >$i.txt; echo -n .; done fgrep -l "[ ]Active" *txt|cut -f 1 -d.|while read a; do grep "Date:\|Time:" $a.txt|sort -u|wc -l|grep -q "^2$" && echo $a; done|while read b; do w3m -cookie http://patchwork.yoursite.org/admin/auth/user/$b/delete/ -dump -cols 200 >$b.del; done # inspect *.del and check if any .del file mentions data you want to keep # extract the cookie value from your w3m cookie cache ls *.del|cut -f 1 -d.|while read a; do curl --data post=yes --cookie sessionid=123456789abcdef http://patchwork.yoursite.org/admin/auth/user/$a/delete/ ; done Regards, Carl-Daniel -- http://www.hailfinger.org/

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Patch merged into coreboot/master: c5be342 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit c5be3428454dc29fb28b0d7a507fa4ef7e707fa3 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:44:28 2012 +0100 nvidia/mcp55: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ibfb7b294aa5007ac2f767d85e090572f85148bad Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 20:34:20 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:19:29 2012, giving +2 See http://review.coreboot.org/659 for details. -gerrit

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Patch merged into coreboot/master: 44b094e amd/sb700: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 44b094ea4156f4f368c4ee40b34b1afa7efc2f17 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:52:16 2012 +0100 amd/sb700: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 21:21:59 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:19:19 2012, giving +2 See http://review.coreboot.org/661 for details. -gerrit

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Patch merged into coreboot/master: 4163c03 intel/i82801cx: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 4163c03b2d713131a863fbf2ec636feb3a983d3e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:53:21 2012 +0100 intel/i82801cx: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Ifba0b65d81af60774f368d151e935ae1cc768336 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 21:36:16 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:07:51 2012, giving +2 See http://review.coreboot.org/662 for details. -gerrit

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Patch merged into coreboot/master: ce3ab07 sis/sis966: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit ce3ab07e387c24eddbd08ca5ac67ae7259bae8b8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:56:50 2012 +0100 sis/sis966: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I9762ef01fc10c453ef643599c1c5dc8ee78081c3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 21:49:48 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:07:43 2012, giving +2 See http://review.coreboot.org/663 for details. -gerrit

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coreboot February 2012