coreboot February 2012

coreboot@coreboot.org

34 participants
348 discussions

Patch merged into coreboot/master: 0d7d667 Force SB600 bootblock to use I/O for PCI config
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 0d7d6676e9c1def4d26432aa481752dbbabd3bec Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 14:50:02 2012 -0700 Force SB600 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the SB600 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is defined by the mainboards Kconfig. Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 02:03:05 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 20 18:52:11 2012, giving +2 See http://review.coreboot.org/632 for details. -gerrit

1 0

Patch merged into coreboot/master: 3a72344 Force SB700 bootblock code to use I/O for PCI config cycles.
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 3a7234421e81fa4a5b86be12de07c220ac0ccf5b Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Feb 1 16:15:08 2012 -0700 Force SB700 bootblock code to use I/O for PCI config cycles. If PCI config cycles use MMIO instead of I/O in the SB700 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is specified by the mainboards Kconfig. Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 01:52:19 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 20 18:51:59 2012, giving +2 See http://review.coreboot.org/631 for details. -gerrit

1 0

Patch merged into coreboot/master: 213eb80 Force SB800 bootblock to use I/O for PCI config
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 213eb80a8a071403ca9448dc08b8e00b95f31e67 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 14:56:23 2012 -0700 Force SB800 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O. Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 01:41:13 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Mon Feb 20 18:51:38 2012, giving +2 See http://review.coreboot.org/630 for details. -gerrit

1 0

Re: [coreboot] porting Coreboot to a new motherboard....
by ron minnich 20 Feb '12

20 Feb '12

you commented out a number of calls to critical functions. You can't just simply set a register and assume it all works. Maybe I misunderstood. I think stepan's i945 code is a great example of how to turn on dram. Or you can look at sdram_enable in the lx440 code for the basic sdram startup cycle. Don't look at the reset of that code, I am not sure it was ever tested on real hardware, there's a comment in there about qemu I don't understand. The lx440 was the second (or first) linuxbios mainboard, but that's not my code, so I'm just not sure about it. ron

1 0

Re: [coreboot] porting Coreboot to a new motherboard....
by Darmawan Salihun 20 Feb '12

20 Feb '12

Well, sorry about the noise. I forgot to mention that most of the RAM init I found was in the raminit.c of each of the northbridge. Is there any other important file(s) that I missed? Thanks, Darmawan On 2/20/12, Darmawan Salihun <darmawan.salihun(a)gmail.com> wrote: > Hi Ron, > > I've been looking for DDR-SDRAM start-up tutorial. Is there any on the > web outside of the JEDEC specs? Anyway, where are the codes located in > the Coreboot source ? is it on the motherboard-specific codes? > > TIA, > > Darmawan > > On 2/15/12, ron minnich <rminnich(a)gmail.com> wrote: >> reading your note leads me to believe you are not familiar with how >> sdram startup works. It's a lot more than just setting one register. >> >> ron >> >> -- >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > -- > -------------------------------------------------------------------- > -= Human knowledge belongs to the world =- > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

1 0

Re: [coreboot] porting Coreboot to a new motherboard....
by Darmawan Salihun 20 Feb '12

20 Feb '12

Hi Ron, I've been looking for DDR-SDRAM start-up tutorial. Is there any on the web outside of the JEDEC specs? Anyway, where are the codes located in the Coreboot source ? is it on the motherboard-specific codes? TIA, Darmawan On 2/15/12, ron minnich <rminnich(a)gmail.com> wrote: > reading your note leads me to believe you are not familiar with how > sdram startup works. It's a lot more than just setting one register. > > ron > > -- > coreboot mailing list: coreboot(a)coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

1 0

Trac reminder: list of new ticket(s)
by coreboot tracker 20 Feb '12

20 Feb '12

1 0

Patch set updated for coreboot: 2703285 libpayload: fix compile error with enabled USB_DEBUG
by Mathias Krause 20 Feb '12

20 Feb '12

Mathias Krause (mathias.krause(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/653 -gerrit commit 270328581ec7881676f9d808483953026e473ff1 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- payloads/libpayload/drivers/usb/ohci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 4095d69..3a1b51d 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -190,7 +190,7 @@ dump_td(td_t *cur, int level) const char *spc=spaces+(10-level); debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[(cur->config & TD_DIRECTION_MASK) >> TD_DIRECTION_SHIFT], completion_codes[(cur->config & TD_CC_MASK) >> TD_CC_SHIFT]); - debug("%s toggle: %x\n", spc, cur->toggle); + debug("%s toggle: %x\n", spc, !!(cur->config & TD_TOGGLE_DATA1)); #endif }

1 0

Patch merged into coreboot/master: ee068e8 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit ee068e84d951b1d198007371d767b920e82ba149 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 22:16:41 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 22:44:19 2012, giving +2 See http://review.coreboot.org/627 for details. -gerrit

1 0

Patch merged into coreboot/master: b1443cb Torpedo mainboard changes to fix warnings.
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit b1443cb4c25f6efa6d0ffc388dbfb8f36c8f15f4 Author: Martin Roth <Martin(a)se-eng.com> Date: Tue Feb 14 10:50:11 2012 -0700 Torpedo mainboard changes to fix warnings. Fixes the warnings generated in the torpedo mainboard build. Most of these changes are similar to fixes already implemented in the persimmon mainboard. Change-Id: Ib931be51c0e6448c00c8cfeb13073e1f392582a5 Signed-off-by: Martin L Roth <martin(a)se-eng.com> Signed-off-by: Marc Jones <marcj303(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 14 22:35:26 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 23:31:20 2012, giving +2 See http://review.coreboot.org/634 for details. -gerrit

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
35
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2012