coreboot February 2012

coreboot@coreboot.org

34 participants
348 discussions

Patch merged into coreboot/master: 89e5ccc intel/i82801ex: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 89e5ccc70f88e9391b12e3658c9bdfe28d590741 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:58:00 2012 +0100 intel/i82801ex: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I83105e92d1cc5d2d12aede564a1ab9c5d912ac56 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 22:02:41 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:07:36 2012, giving +2 See http://review.coreboot.org/664 for details. -gerrit

1 0

Patch merged into coreboot/master: 7a2d314 intel/sch: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 7a2d3142f8f4d7c606c1f7e46a7d1e478e77b5fb Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:58:51 2012 +0100 intel/sch: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: I521deecf58e5d5de303f1ef2f5ff7e965294de18 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 22:15:35 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:07:28 2012, giving +2 See http://review.coreboot.org/665 for details. -gerrit

1 0

Patch merged into coreboot/master: cd19125 amd/sb800: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit cd191255004e3701096e0f7fc810e3e29456f80d Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 20:03:28 2012 +0100 amd/sb800: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. (cimx/sb800 is a "different" chipset) Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 22:28:45 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:00:44 2012, giving +2 See http://review.coreboot.org/666 for details. -gerrit

1 0

New patch to review for coreboot: a47f09d AGESA family 12 changes to fix torpedo warnings
by Martin Roth 17 Feb '12

17 Feb '12

Martin Roth (martin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/667 -gerrit commit a47f09d8e723896eb63ae8437250c0ee7ce68da9 Author: Martin Roth <martin(a)se-eng.com> Date: Fri Feb 17 13:16:04 2012 -0700 AGESA family 12 changes to fix torpedo warnings Fixes the warnings generated in the torpedo mainboard build by AGESA. Removing broken tests. Change-Id: Ib444fa2bf4dd94cadb4ce33040eb5650d1c0325b Signed-off-by: Martin L Roth <martin(a)se-eng.com> --- .../amd/agesa/f12/Include/OptionMemoryInstall.h | 9 +++++ .../amd/agesa/f12/Include/PlatformInstall.h | 32 +++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h index 35825d8..cfb55cc 100755 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h @@ -44,6 +44,10 @@ #ifndef _OPTION_MEMORY_INSTALL_H_ #define _OPTION_MEMORY_INSTALL_H_ +#ifndef RUN_BROKEN_AGESA_TESTS + #define RUN_BROKEN_AGESA_TESTS 0 +#endif + /*------------------------------------------------------------------------------- * This option file is designed to be included into the platform solution install * file. The platform solution install file will define the options status. @@ -3395,9 +3399,14 @@ BOOLEAN MemFS3DefConstructorRet ( NULL }; CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*)); +/* SIZE_OF_PLATFORM is not defined when the preprocessor runs + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES #error Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES #endif +#endif /*--------------------------------------------------------------------------------------------------- * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h index 50275eb..ba8bc1f 100755 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h @@ -42,6 +42,10 @@ * ***************************************************************************/ +#ifndef RUN_BROKEN_AGESA_TESTS + #define RUN_BROKEN_AGESA_TESTS 0 +#endif + /***************************************************************************** * * Start processing the user options: First, set default settings @@ -76,7 +80,7 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , - '0000', + Int32FromChar ('0', '0', '0', '0'), //ModuleIdentifier[8] AGESA_ID, //ModuleVersion[12] @@ -2150,6 +2154,10 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #error No Dram init option has been selected #endif #endif +/* As an ENUM, DDRXXX_FREQUENCY is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS // Ensure the frequency limit is valid #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933) #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800) @@ -2168,6 +2176,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif + +#endif +/* As an ENUM, TIMING_MODE_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + // Ensure timing mode is valid #if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED @@ -2176,6 +2191,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif + +#endif // Ensure the scrub rate is valid #if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF)) #error BLDCFG: Unsupported dram scrub rate set @@ -2192,12 +2209,19 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #if CFG_SCRUB_DC_RATE > 0x16 #error BLDCFG: Unsupported Dcache scrub rate set #endif +/* As an ENUM, QUADRANK_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + // Ensure Quad rank dimm type is valid #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED #error BLDCFG: Invalid quad rank dimm type set #endif #endif + +#endif // Ensure ECC symbol size is valid #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4 @@ -2206,6 +2230,11 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif #endif +/* As an ENUM, POWER_DOWN_BY_XXX is not defined when the c preprocessor runs. + * Removing this test for coreboot. + */ +#if RUN_BROKEN_AGESA_TESTS + // Ensure power down mode is valid #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL @@ -2213,6 +2242,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #endif #endif +#endif /***************************************************************************** * * Process the option logic, setting local control variables

1 0

Patch merged into coreboot/master: c8753cb broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit c8753cbfe7448a3ccb76742a77e7d5fe8fb749da Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:42:48 2012 +0100 broadcom/bcm5785: Move HAVE_HARD_RESET to southbridge No in-tree board using that chipset has it not selected, so move selection from boards to southbridge. Change-Id: Id95660f088c8240606d45abf326cd5eefca30da3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 20:01:33 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:19:33 2012, giving +2 See http://review.coreboot.org/658 for details. -gerrit

1 0

Patch merged into coreboot/master: 70357f2 libpayload: enforce const correctness for CMOS getter/setter
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 70357f264a5f8a0472ea1fef7f6bc967fd674eb1 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Fri Feb 17 12:02:47 2012 +0100 libpayload: enforce const correctness for CMOS getter/setter Input only arguments to {get,set}_option*() should be const to catch programming errors early. Change-Id: I560001a8e9226dfd156a4e529fcad20549236ebd Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Feb 17 13:56:19 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:26:48 2012, giving +2 See http://review.coreboot.org/652 for details. -gerrit

1 0

Patch merged into coreboot/master: 87af06a Avoid ../../.. paths in ASL files
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 87af06a897dd92ae94e45f4b1d1f6d9719cf3edd Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:01:22 2012 +0100 Avoid ../../.. paths in ASL files The current directory is always part of the search path of cpp when using #include "..." Change-Id: I74fe39e0c79835e4b9a927afcbeab21040d8ae52 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 11:48:54 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:05:18 2012, giving +2 See http://review.coreboot.org/648 for details. -gerrit

1 0

Patch merged into coreboot/master: 23defd9 Rename i945 ACPI files to not carry an i945_ prefix
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 23defd9637fb9791dc5c7cdadc847f2bc7698c1f Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 18:58:46 2012 +0100 Rename i945 ACPI files to not carry an i945_ prefix In the spirit of the earlier renames. Change-Id: I458a42c79a164483120169d1822ffa6861cc3aff Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 11:37:42 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:04:56 2012, giving +2 See http://review.coreboot.org/647 for details. -gerrit

1 0

Patch merged into coreboot/master: 5ca7fab libpayload: fix compiler warning for first_cmos_entry()
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 5ca7fab6a2e741cddd4d86e2cf321378e807db1f Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Fri Feb 17 11:53:28 2012 +0100 libpayload: fix compiler warning for first_cmos_entry() The 'name' argument to lookup_cmos_entry() is declared to be 'char *' but we pass an empty string ("") which is 'const char[]' so the compiler legitimatly warns about discarded qualifiers here. Fix this by passing NULL as 'name'. Minor nitpick: The NULL test in lookup_cmos_entry() is superfluous as our implementation of strnlen() can handle NULL pointers gracefully. But for an average C hacker it just doesn't feel right not to do so. Change-Id: I592917d12d8fa840804c0d19e38b844427064fef Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Fri Feb 17 13:44:56 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:07:05 2012, giving +2 See http://review.coreboot.org/651 for details. -gerrit

1 0

Patch merged into coreboot/master: 99d2e99 nvidia/ck804: Move HAVE_HARD_RESET to southbridge
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 99d2e9999b9975e16b2aaadb4d1bba72ae74ef9e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Feb 16 19:39:39 2012 +0100 nvidia/ck804: Move HAVE_HARD_RESET to southbridge No in-tree ck804-using board has it not selected, so move selection from boards to southbridge. Change-Id: I3064b406cfd5ad18067c597bd5b5866a720f7e87 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Build-Tested: build bot (Jenkins) at Fri Feb 17 19:15:47 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Feb 17 19:19:37 2012, giving +2 See http://review.coreboot.org/657 for details. -gerrit

1 0

← Newer
1
...
8
9
10
11
12
13
14
...
35
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot February 2012