coreboot February 2012

coreboot@coreboot.org

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Patch merged into coreboot/master: 06edf50 SIO: Add smsc sio1036 superio
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 06edf5030bf5ad86db07a0922213d6d50d73553a Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc sio1036 superio Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Feb 17 09:45:47 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Feb 17 17:19:20 2012, giving +2 See http://review.coreboot.org/563 for details. -gerrit

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Patch merged into coreboot/master: 0295597 SIO: Add smsc/sch4037 superio support
by gerrit＠coreboot.org 17 Feb '12

17 Feb '12

the following patch was just integrated into master: commit 0295597c40c6069186d690651b91a85efefc7851 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 SIO: Add smsc/sch4037 superio support Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Fri Feb 17 10:02:42 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Fri Feb 17 17:18:16 2012, giving +2 See http://review.coreboot.org/562 for details. -gerrit

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Patch set updated for coreboot: 5141b7c Apply cache-as-ram conditionally on socket mPGA604
by Kyösti Mälkki 17 Feb '12

17 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/607 -gerrit commit 5141b7cd455d57027469cdc4f4ad8ea63dbd5b60 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 1 19:15:13 2012 +0200 Apply cache-as-ram conditionally on socket mPGA604 The socket mPGA604 is for P4 Xeon which to my knowledge is always HT-enabled. I assume the existing usage of car/cache_as_ram.inc on socket_mPGA604, namely the Tyan S2735, as broken. Existing car/cache_as_ram.inc has invalid SIPI vector and it does not initialise AP CPU's to activate L2 cache. Other mPGA604 boards are not affected, as they have not been converted to CAR. Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/Makefile.inc | 8 +------- src/cpu/intel/socket_mPGA604/Kconfig | 18 +++++++++++++++++- src/cpu/intel/socket_mPGA604/Makefile.inc | 2 ++ 3 files changed, 20 insertions(+), 8 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..eeb162d 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -190,13 +190,7 @@ crt0s += $(src)/cpu/x86/sse_enable.inc endif crt0s += $(cpu_incs) - -# -# FIXME move to CPU_INTEL_SOCKET_MPGA604 -# -ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/intel/car/cache_as_ram.inc -endif +crt0s += $(cpu_incs-y) ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/x86/llshell/llshell.inc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 2fc27cf..fb48968 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -1,11 +1,17 @@ config CPU_INTEL_SOCKET_MPGA604 bool + +if CPU_INTEL_SOCKET_MPGA604 + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y select CPU_INTEL_MODEL_F2X select CPU_INTEL_MODEL_F3X select CPU_INTEL_MODEL_F4X select MMX select SSE select UDELAY_TSC + select INTEL_NETBURST # mPGA604 are usually Intel Netburst CPUs which should have SSE2 # but the ramtest.c code on the Dell S1850 seems to choke on @@ -13,4 +19,14 @@ config CPU_INTEL_SOCKET_MPGA604 config SSE2 bool default n - depends on CPU_INTEL_SOCKET_MPGA604 + +config DCACHE_RAM_BASE + hex + default 0x0ffafc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +endif # CPU_INTEL_SOCKET_MPGA604 + diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 1404e84..fb1cacd 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -10,3 +10,5 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../hyperthreading +cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc +

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Patch set updated for coreboot: d678491 Add cache_as_ram_ht.inc with hyper-threading CPU support
by Kyösti Mälkki 17 Feb '12

17 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/604 -gerrit commit d678491fdb594b6a872c78465851a8656dfcd4da Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 21:23:33 2012 +0200 Add cache_as_ram_ht.inc with hyper-threading CPU support This variant of cache_as_ram.inc starts the sibling CPU processors and clears the cache disable bits (CR0.CD) in case a hyper-threading CPU is detected. The code was developed for model_f25 from model_6ex. Some of the cache enable-disable logic seems spurious to me. Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 147 ++++++++++++++++++++++++++++++--- 1 files changed, 134 insertions(+), 13 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 4505e0e..139f63a 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -2,7 +2,9 @@ * This file is part of the coreboot project. * * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan) * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,6 +27,7 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) +#define START_IPI_VECTOR ((CONFIG_AP_SIPI_VECTOR >> 12) & 0xff) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) @@ -40,12 +43,9 @@ cache_as_ram: post_code(0x20) - /* Send INIT IPI to all excluding ourself. */ - movl LAPIC(ICR), %edi - movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax - movl %eax, (%edi) - - /* Zero out all fixed range and variable range MTRRs. */ + /* Zero out all fixed range and variable range MTRRs. + * For hyper-threaded CPU MTRRs are shared so we actually + * clear them more than once, but we don't care. */ movl $mtrr_table, %esi movl $((mtrr_table_end - mtrr_table) / 2), %edi xorl %eax, %eax @@ -58,12 +58,127 @@ clear_mtrrs: dec %edi jnz clear_mtrrs + post_code(0x21) + /* Configure the default memory type to uncacheable. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr + post_code(0x22) + + /* Enable local apic. */ + movl $LAPIC_BASE_MSR, %ecx + rdmsr + andl $(~CPU_PHYSMASK_HI), %edx + andl $(~LAPIC_BASE_MSR_ADDR_MASK), %eax + orl $(LAPIC_DEFAULT_BASE | LAPIC_BASE_MSR_ENABLE), %eax + wrmsr + andl $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax + jz ap_init + +bsp_init: + + post_code(0x23) + + /* Send INIT IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + post_code(0x24) + + /* For a hyper-threading processor, cache must not be disabled + * on an AP on the same physical package with the BSP. + */ + movl $01, %eax + cpuid + btl $28, %edx + jnc sipi_complete + bswapl %ebx + cmpb $01, %bh + jbe sipi_complete + +hyper_threading_cpu: + + /* delay 10 ms */ + movl $10000, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x25) + + /* Send Start IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_DM_STARTUP | START_IPI_VECTOR), %eax +1: movl %eax, (%edi) + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + movl (%edi), %ecx + andl $LAPIC_ICR_BUSY, %ecx + jnz 1b + + /* delay 250 us */ + movl $250, %ecx +1: inb $0x80, %al + dec %ecx + jnz 1b + + post_code(0x26) + + /* Wait for sibling CPU to start. */ +1: movl $(MTRRphysBase_MSR(0)), %ecx + rdmsr + andl %eax, %eax + jnz sipi_complete + + movl $0x30, %ecx +2: pause + dec %ecx + jnz 2b + jmp 1b + + +ap_init: + post_code(0x27) + + /* Do not disable cache (so BSP can enable it). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + post_code(0x28) + + /* MTRR registers are shared between HT siblings. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(1<<12), %eax + xorl %edx, %edx + wrmsr + + post_code(0x29) + +ap_halt: + cli +1: hlt + jnz 1b + + + +sipi_complete: + + post_code(0x2a) + /* Set Cache-as-RAM base address. */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax @@ -82,6 +197,8 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr + post_code(0x2b) + #if !CONFIG_INTEL_NETBURST /* Enable L2 cache Write-Back (WBINVD and FLUSH#). * This MSR does not exist on NetBurst architecture. @@ -96,6 +213,8 @@ clear_mtrrs: wrmsr #endif + post_code(0x2c) + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax @@ -114,6 +233,8 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 + post_code(0x2d) + #if CONFIG_XIP_ROM_SIZE /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx @@ -138,6 +259,8 @@ clear_mtrrs: andl $(~((1 << 30) | (1 << 29))), %eax movl %eax, %cr0 + post_code(0x2e) + /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ @@ -151,14 +274,12 @@ clear_mtrrs: movl %esp, %ebp pushl %eax - post_code(0x23) + post_code(0x2f) /* Call romstage.c main function. */ call main addl $4, %esp - post_code(0x2f) - post_code(0x30) /* Disable cache. */ @@ -166,7 +287,7 @@ clear_mtrrs: orl $(1 << 30), %eax movl %eax, %cr0 - post_code(0x31) + post_code(0x34) /* Disable MTRR. */ movl $MTRRdefType_MSR, %ecx @@ -174,18 +295,18 @@ clear_mtrrs: andl $(~MTRRdefTypeEn), %eax wrmsr - post_code(0x31) + post_code(0x35) invd - post_code(0x33) + post_code(0x36) /* Enable cache. */ movl %cr0, %eax andl $~((1 << 30) | (1 << 29)), %eax movl %eax, %cr0 - post_code(0x36) + post_code(0x37) /* Disable cache. */ movl %cr0, %eax

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Patch set updated for coreboot: 42a0258 Add support for RAM-less multi-processor init
by Kyösti Mälkki 17 Feb '12

17 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 42a025844124f7dcb4d6de8eb1f99cd2fd8f71f4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index d576873..601f443 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -38,6 +38,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help

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Patch set updated for coreboot: 10daacf Exit building if romstage.bin is larger than size of XIP
by Zheng Bao 17 Feb '12

17 Feb '12

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/650 -gerrit commit 10daacf118096519aeac961c1814f790cbf66d0e Author: zbao <fishbaozi(a)gmail.com> Date: Fri Feb 17 21:44:09 2012 +0800 Exit building if romstage.bin is larger than size of XIP When the romstage.bin becomes bigger than the size of XIP, the cbfstool can not allocate the romstage in the CBFS. But it doesn't report an error. It will take quite a while to find out the root cause. Change-Id: I5be2a46a8b57934f14c5a0d4596f3bec4251e0aa Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: zbao <fishbaozi(a)gmail.com> --- src/arch/x86/Makefile.inc | 2 +- util/cbfstool/cbfstool.c | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c9cbb01..624b510 100755 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -346,7 +346,7 @@ $(obj)/coreboot.romstage: $(obj)/coreboot.pre1 $$(romstage-objs) $(obj)/romstage $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) $(OBJCOPY) -O binary $(obj)/romstage.elf $(obj)/romstage.bin printf "CONFIG_ROMBASE = 0x" > $(obj)/location.ld - $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt + $(CBFSTOOL) $(obj)/coreboot.pre1 locate $(obj)/romstage.bin $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_XIP_ROM_SIZE) > $(obj)/location.txt || { echo "The romstage is larger than XIP size. Please expand the CONFIG_XIP_ROM_SIZE" ; exit 1; } cat $(obj)/location.txt >> $(obj)/location.ld printf ';\n' >> $(obj)/location.ld $(CC) -nostdlib -nostartfiles -static -o $(obj)/romstage.elf -L$(obj) -T $(obj)/romstage/ldscript.ld $(romstage-objs) diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index b8abb51..939221e 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -232,9 +232,10 @@ static int cbfs_locate(int argc, char **argv) uint32_t filesize = getfilesize(file); const char *filename = argv[4]; int align = strtoul(argv[5], NULL, 0); + uint32_t location = cbfs_find_location(romname, filesize, filename, align); - printf("%x\n", cbfs_find_location(romname, filesize, filename, align)); - return 0; + printf("%x\n", location); + return location == 0 ? 1 : 0; } static int cbfs_print(int argc, char **argv)

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Patch set updated for coreboot: 97120f0 Intel cpus: copy model_6ex CAR code
by Kyösti Mälkki 17 Feb '12

17 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/606 -gerrit commit 97120f0397a34543b5300e68d0899efe4b63f3f0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 17 01:38:13 2012 +0200 Intel cpus: copy model_6ex CAR code Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended with hyper-threading CPU support. Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/car/cache_as_ram_ht.inc | 269 +++++++++++++++++++++++++++++++++ 1 files changed, 269 insertions(+), 0 deletions(-) diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc new file mode 100644 index 0000000..4505e0e --- /dev/null +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -0,0 +1,269 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/x86/stack.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> +#include <cpu/x86/lapic_def.h> + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) + +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) + +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + +#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE +#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ + movl %eax, %ebp + +cache_as_ram: + post_code(0x20) + + /* Send INIT IPI to all excluding ourself. */ + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) + + /* Zero out all fixed range and variable range MTRRs. */ + movl $mtrr_table, %esi + movl $((mtrr_table_end - mtrr_table) / 2), %edi + xorl %eax, %eax + xorl %edx, %edx +clear_mtrrs: + movw (%esi), %bx + movzx %bx, %ecx + wrmsr + add $2, %esi + dec %edi + jnz clear_mtrrs + + /* Configure the default memory type to uncacheable. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~0x00000cff), %eax + wrmsr + + /* Set Cache-as-RAM base address. */ + movl $(MTRRphysBase_MSR(0)), %ecx + movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + + /* Set Cache-as-RAM mask. */ + movl $(MTRRphysMask_MSR(0)), %ecx + movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + +#if !CONFIG_INTEL_NETBURST + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). + * This MSR does not exist on NetBurst architecture. + * + * Description says this bit enables use of WBINVD and FLUSH#. + * Should this be set only after the system bus and/or memory + * controller can successfully handle write cycles? + */ + movl $0x11e, %ecx + rdmsr + orl $(1 << 8), %eax + wrmsr +#endif + + /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + invd + movl %eax, %cr0 + + /* Clear the cache memory reagion. */ + cld + xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx + rep stosl + + /* Enable Cache-as-RAM mode by disabling cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + +#if CONFIG_XIP_ROM_SIZE + /* Enable cache for our code in Flash because we do XIP here */ + movl $MTRRphysBase_MSR(1), %ecx + xorl %edx, %edx + /* + * IMPORTANT: The following calculation _must_ be done at runtime. See + * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html + */ + movl $copy_and_run, %eax + andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax + orl $MTRR_TYPE_WRBACK, %eax + wrmsr + + movl $MTRRphysMask_MSR(1), %ecx + movl $CPU_PHYSMASK_HI, %edx + movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + wrmsr +#endif /* CONFIG_XIP_ROM_SIZE */ + + /* Enable cache. */ + movl %cr0, %eax + andl $(~((1 << 30) | (1 << 29))), %eax + movl %eax, %cr0 + + /* Set up the stack pointer. */ +#if CONFIG_USBDEBUG + /* Leave some space for the struct ehci_debug_info. */ + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp +#else + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp +#endif + + /* Restore the BIST result. */ + movl %ebp, %eax + movl %esp, %ebp + pushl %eax + + post_code(0x23) + + /* Call romstage.c main function. */ + call main + addl $4, %esp + + post_code(0x2f) + + post_code(0x30) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~MTRRdefTypeEn), %eax + wrmsr + + post_code(0x31) + + invd + + post_code(0x33) + + /* Enable cache. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x36) + + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for low RAM. */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + /* Enable caching and Speculative Reads for Flash ROM device. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $CPU_PHYSMASK_HI, %edx + wrmsr + + post_code(0x39) + + /* And enable cache again after setting MTRRs. */ + movl %cr0, %eax + andl $~((1 << 30) | (1 << 29)), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR. */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $MTRRdefTypeEn, %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again. */ + invd + + post_code(0x3c) + + /* Clear boot_complete flag. */ + xorl %ebp, %ebp +__main: + post_code(POST_PREPARE_RAMSTAGE) + cld /* Clear direction flag. */ + + movl %ebp, %esi + + movl $ROMSTAGE_STACK, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(POST_DEAD_CODE) + hlt + jmp .Lhlt + +mtrr_table: + /* Fixed MTRRs */ + .word 0x250, 0x258, 0x259 + .word 0x268, 0x269, 0x26A + .word 0x26B, 0x26C, 0x26D + .word 0x26E, 0x26F + /* Variable MTRRs */ + .word 0x200, 0x201, 0x202, 0x203 + .word 0x204, 0x205, 0x206, 0x207 + .word 0x208, 0x209, 0x20A, 0x20B + .word 0x20C, 0x20D, 0x20E, 0x20F +mtrr_table_end: +

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Patch set updated for coreboot: 773f2c2 Add support for RAM-less multi-processor init
by Kyösti Mälkki 17 Feb '12

17 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 773f2c2ae32a59f786aaecfbf1756f3d79c435e4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..0bdef34 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -31,6 +31,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help

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New patch to review for coreboot: 979a6a3 libpayload: fix compile error with enabled USB_DEBUG
by Mathias Krause 17 Feb '12

17 Feb '12

Mathias Krause (mathias.krause(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/653 -gerrit commit 979a6a3099ff7b4498e098c1ab9df6508b0e8087 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- payloads/libpayload/drivers/usb/ohci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 4095d69..92cbf1c 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -190,7 +190,7 @@ dump_td(td_t *cur, int level) const char *spc=spaces+(10-level); debug("%std at %x (%s), condition code: %s\n", spc, cur, direction[(cur->config & TD_DIRECTION_MASK) >> TD_DIRECTION_SHIFT], completion_codes[(cur->config & TD_CC_MASK) >> TD_CC_SHIFT]); - debug("%s toggle: %x\n", spc, cur->toggle); + debug("%s toggle: %x\n", spc, cur->config & TD_TOGGLE_DATA1 ? 1 : 0); #endif }

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New patch to review for coreboot: 70357f2 libpayload: enforce const correctness for CMOS getter/setter
by Mathias Krause 17 Feb '12

17 Feb '12

Mathias Krause (mathias.krause(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/652 -gerrit commit 70357f264a5f8a0472ea1fef7f6bc967fd674eb1 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Fri Feb 17 12:02:47 2012 +0100 libpayload: enforce const correctness for CMOS getter/setter Input only arguments to {get,set}_option*() should be const to catch programming errors early. Change-Id: I560001a8e9226dfd156a4e529fcad20549236ebd Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- payloads/libpayload/drivers/options.c | 28 ++++++++++++++-------------- payloads/libpayload/include/libpayload.h | 14 +++++++------- 2 files changed, 21 insertions(+), 21 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 73316c1..03b6d36 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -97,7 +97,7 @@ void fix_options_checksum(void) static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) { - u8 *value = (u8 *)valptr; + u8 *value = valptr; int offs = 0; u32 addr, bit; u8 reg8; @@ -123,9 +123,9 @@ static int get_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 le return 0; } -static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, void *valptr) +static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 len, const void *valptr) { - u8 *value = (u8 *)valptr; + const u8 *value = valptr; int offs = 0; u32 addr, bit; u8 reg8; @@ -152,7 +152,7 @@ static int set_cmos_value(const struct nvram_accessor *nvram, u32 bitnum, u32 le return 0; } -static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, char *name) +static struct cb_cmos_entries *lookup_cmos_entry(struct cb_cmos_option_table *option_table, const char *name) { struct cb_cmos_entries *cmos_entry; int len = name ? strnlen(name, CMOS_MAX_NAME_LENGTH) : 0; @@ -186,7 +186,7 @@ struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cmos_entry) } /* Either value or text must be NULL. Returns the field that matches "the other" for a given config_id */ -static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *option_table, int config_id, u8 *value, char *text) +static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table *option_table, int config_id, const u8 *value, const char *text) { struct cb_cmos_entries *cmos_entry; int len = strnlen(text, CMOS_MAX_TEXT_LENGTH); @@ -211,17 +211,17 @@ static struct cb_cmos_enums *lookup_cmos_enum_core(struct cb_cmos_option_table * return NULL; } -static struct cb_cmos_enums *lookup_cmos_enum_by_value(struct cb_cmos_option_table *option_table, int config_id, u8 *value) +static struct cb_cmos_enums *lookup_cmos_enum_by_value(struct cb_cmos_option_table *option_table, int config_id, const u8 *value) { return lookup_cmos_enum_core(option_table, config_id, value, NULL); } -static struct cb_cmos_enums *lookup_cmos_enum_by_label(struct cb_cmos_option_table *option_table, int config_id, char *label) +static struct cb_cmos_enums *lookup_cmos_enum_by_label(struct cb_cmos_option_table *option_table, int config_id, const char *label) { return lookup_cmos_enum_core(option_table, config_id, NULL, label); } -int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name) +int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, const char *name) { struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); if (cmos_entry) { @@ -236,17 +236,17 @@ int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_ta return 1; } -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name) +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, const char *name) { return get_option_with(use_nvram, option_table, dest, name); } -int get_option(void *dest, char *name) +int get_option(void *dest, const char *name) { return get_option_from(get_system_option_table(), dest, name); } -int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name) +int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const void *value, const char *name) { struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); if (cmos_entry) { @@ -257,12 +257,12 @@ int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_ta return 1; } -int set_option(void *value, char *name) +int set_option(const void *value, const char *name) { return set_option_with(use_nvram, get_system_option_table(), value, name); } -int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, char *name) +int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name) { void *raw; struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); @@ -298,7 +298,7 @@ int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_opti return ret; } -int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char *value, char *name) +int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const char *value, const char *name) { void *raw; struct cb_cmos_entries *cmos_entry = lookup_cmos_entry(option_table, name); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 53d6672..c67c659 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -208,13 +208,13 @@ void fix_options_checksum_with(const struct nvram_accessor *nvram); void fix_options_checksum(void); struct cb_cmos_entries *first_cmos_entry(struct cb_cmos_option_table *option_table); struct cb_cmos_entries *next_cmos_entry(struct cb_cmos_entries *cur); -int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, char *name); -int get_option_from(struct cb_cmos_option_table *option_table, void *dest, char *name); -int get_option(void *dest, char *name); -int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *value, char *name); -int set_option(void *value, char *name); -int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, char *name); -int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char *value, char *name); +int get_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, void *dest, const char *name); +int get_option_from(struct cb_cmos_option_table *option_table, void *dest, const char *name); +int get_option(void *dest, const char *name); +int set_option_with(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const void *value, const char *name); +int set_option(const void *value, const char *name); +int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, char **dest, const char *name); +int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_option_table *option_table, const char *value, const char *name); /** * @defgroup console Console functions

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coreboot February 2012