coreboot February 2012

coreboot@coreboot.org

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348 discussions

Patch merged into coreboot/master: b6bebf4 SIO: Winbond w83627dhg update
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit b6bebf4968019fd38a7086cbf350a9c26b4451a3 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:32:37 2012 +0800 SIO: Winbond w83627dhg update 1. Stop include c file. 2. W83627dhg Pin 89, Pin 90 are multi function pins, add support to select them to I2C function. Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 15:23:23 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 21:08:49 2012, giving +2 See http://review.coreboot.org/565 for details. -gerrit

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Patch merged into coreboot/master: c8657a8 RD890: AMD RD890/SR56X0 CIMX wrapper
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit c8657a8bf8e98a9e19db9f248fd44a72e747632d Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 RD890: AMD RD890/SR56X0 CIMX wrapper Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0, RD890 and 990FX chipsets. Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 14:52:04 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 19:33:45 2012, giving +2 See http://review.coreboot.org/559 for details. -gerrit

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Patch merged into coreboot/master: d59002f pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit d59002f19e9dc56bd94c61f055b26bef62943540 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 pci_ids: Add AMD F15h model 00-0f and F10h cpu HT device pci ids Change-Id: I13905f5730d08510c8f0f6e652f41a679d618d1b Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 13:29:49 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 19:27:28 2012, giving +2 See http://review.coreboot.org/609 for details. -gerrit

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Patch merged into coreboot/master: 3354884 AGESA F15: AGESA family15 model 00-0fh cpu wrapper
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit 33548842f15fb467b28a0a899b4ff84ceccf5116 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:35 2012 +0800 AGESA F15: AGESA family15 model 00-0fh cpu wrapper Change-Id: I7580bc063c09d99d3fca8b20cd39df2384a6ad44 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 13:16:42 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 19:26:31 2012, giving +2 See http://review.coreboot.org/555 for details. -gerrit

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New patch to review for coreboot: a56cd13 Intel cpus: delete dead CAR code and whitespace fixes
by Kyösti Mälkki 16 Feb '12

16 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/640 -gerrit commit a56cd135813643e54707900e25b55726546984f1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 13:08:31 2012 +0200 Intel cpus: delete dead CAR code and whitespace fixes A diff from model_6fx to model_106cx suggests there is little CORE2 specific code that was once considered useful to have. In its current status however, sockets supporting model_6fx use model_6ex CAR init, so that specific code is actually never used. Deletes file: model_6fx/cache_as_ram.inc Change-Id: I6c0204446fa98207e31f91895e1cf30fde42382c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_106cx/cache_as_ram.inc | 14 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 16 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 271 ---------------------------- 3 files changed, 3 insertions(+), 298 deletions(-) diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index 1e5ee64..605bd70 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -82,7 +82,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 @@ -163,18 +163,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index a603472..8f2b1bd 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -82,7 +82,7 @@ clear_mtrrs: wrmsr /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~((1 << 30) | (1 << 29))), %eax invd movl %eax, %cr0 @@ -163,18 +163,6 @@ clear_mtrrs: post_code(0x31) invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif post_code(0x33) @@ -192,7 +180,7 @@ clear_mtrrs: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first 1MB. */ + /* Enable Write Back and Speculative Reads for low RAM. */ movl $MTRRphysBase_MSR(0), %ecx movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc deleted file mode 100644 index 9e3942b..0000000 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ /dev/null @@ -1,271 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cpu/x86/stack.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Disable prefetchers */ - movl $0x01a0, %ecx - rdmsr - orl $((1 << 9) | (1 << 19)), %eax - orl $((1 << 5) | (1 << 7)), %edx - wrmsr - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd -#if 0 - xorl %eax, %eax - xorl %edx, %edx - movl $MTRRphysBase_MSR(0), %ecx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - wrmsr - movl $MTRRphysBase_MSR(1), %ecx - wrmsr - movl $MTRRphysMask_MSR(1), %ecx - wrmsr -#endif - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Enable prefetchers */ - movl $0x01a0, %ecx - rdmsr - andl $~((1 << 9) | (1 << 19)), %eax - andl $~((1 << 5) | (1 << 7)), %edx - wrmsr - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: -

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New patch to review for coreboot: 1e27bae Intel cpus: use MAXPHYADDR from Kconfig during CAR
by Kyösti Mälkki 16 Feb '12

16 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/639 -gerrit commit 1e27bae2f43c4ac137bc1b7cb4e9848f2981a45f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 11:05:55 2012 +0200 Intel cpus: use MAXPHYADDR from Kconfig during CAR This config determines the high 32 bits of MTRR mask registers as used during Cache-As-Ram. Run-time check in asm would be sort-of messy, but can be implemented at later time if found necessary. Default is MAXPHYADDR=36. For Atom (model_106cx) use 32. This model is known to fail execution-in-place (XIP) with the default 36. Pentium M should use 32, but doesn't even with this patch. Some Xeon and CORE(2) models should use 38 or 40. Change-Id: If604badcdc578c4f4bc7d30da2f61397ec0d754c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/Kconfig | 7 +++++++ src/cpu/intel/model_106cx/Kconfig | 11 +++++++++++ src/cpu/intel/model_106cx/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6ex/cache_as_ram.inc | 3 +-- src/cpu/intel/model_6fx/cache_as_ram.inc | 3 +-- 5 files changed, 21 insertions(+), 6 deletions(-) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..d576873 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -19,6 +19,13 @@ config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x0 +config CPU_MAXPHYADDR + int + default 36 + help + Static CPU MAXPHYADDR used for MTRR mask during Cache-As-Ram. + Later MTRR setup uses run-time check with CPUID. + config MAX_PHYSICAL_CPUS int default 1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index 09449cb..fa6ebfd 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -1,6 +1,17 @@ config CPU_INTEL_MODEL_106CX bool + +if CPU_INTEL_MODEL_106CX + +config CPU_SPECIFIC_OPTIONS # dummy + def_bool y select SMP select SSE2 select UDELAY_LAPIC select AP_IN_SIPI_WAIT + +config CPU_MAXPHYADDR + int + default 32 + +endif # CPU_INTEL_MODEL_106CX diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc index caf5d03..1e5ee64 100644 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ b/src/cpu/intel/model_106cx/cache_as_ram.inc @@ -22,8 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 32 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 08f5b11..a603472 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -22,8 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 25d8de2..9e3942b 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -22,8 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> -#define CPU_MAXPHYADDR 36 -#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYADDR - 32) - 1) +#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

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Patch merged into coreboot/master: f548d59 Intel cpus: use CPU_PHYSMASK_HI define in CAR
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit f548d593f020bd56c1bb7fa75ea8d6cb11cb0428 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 15 15:55:57 2012 +0200 Intel cpus: use CPU_PHYSMASK_HI define in CAR Unifies models 6ex, 6fx and 106cx. Change-Id: I2bb632c7148a7d937f24eb559f7f4e539d227470 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Wed Feb 15 16:00:27 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Feb 16 01:55:49 2012, giving +2 See http://review.coreboot.org/638 for details. -gerrit

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Re: [coreboot] "Fix multipleVGA cards resource conflict on Windows" broke my vga
by Denis 'GNUto' Carikli 15 Feb '12

15 Feb '12

On Tue, 2012-02-14 at 13:47 -0700, Marc Jones wrote: > Logs would help, but you could some analysis about what setting is > making the device work or not. Searching for pci1002,9710.rom Check cmos_layout.bin Check pci1002,9710.rom In CBFS, ROM address for PCI: 01:05.0 = fff00778 PCI expansion ROM, signature 0xaa55, INIT size 0xec00, data ptr 0x01b0 PCI ROM image, vendor ID 1002, device ID 9710, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from fff00778 to 0xc0000, 0xec00 bytes [hangs here] here are the logs. Denis.

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Re: [coreboot] Which MSR disables hyperthreading (all non-BSP/AP cores)?
by Kyösti Mälkki 15 Feb '12

15 Feb '12

On Wed, 2012-02-15 at 17:33 +0100, Idwer Vollering wrote: > Or: how to start a multicore (hyperthreading) processor as if it were > a singlecore (non-hyperthreading) processor. > To my knowledge, there is no such MSR for P4 Hyper-Threaded CPUs using the NetBurst Architecture. So SerialICE may need a patch for hyper-threaded CPUs to enable Cache-As-Ram, like coreboot does. You've seen my cache-as-ram code with SIPIs for model f25 (P4 Xeon on socket 604), to enable cache on HT-enabled CPU. >From your responses (on e-mail) so far, I cannot determine where (if) it stops with P4 models f29 and f49 on socket 478 (?). You have actual POST code PCI device, make wise use of it. Thanks, KM

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Re: [coreboot] [SerialICE] Which MSR disables hyperthreading (all non-BSP/AP cores)?
by Stefan Reinauer 15 Feb '12

15 Feb '12

* Idwer Vollering <vidwer(a)gmail.com> [120215 17:33]: > Or: how to start a multicore (hyperthreading) processor as if it were > a singlecore (non-hyperthreading) processor. > > Would it be necessary to configure APIC/IPI in serialice' mainboard > specific code? You probably need something like: /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax movl $0xFEE00300, %esi movl %eax, (%esi) (Taken from cache_as_ram.inc on model_6ex) Stefan

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coreboot February 2012