coreboot February 2012

coreboot@coreboot.org

34 participants
348 discussions

Re: [coreboot] porting Coreboot to a new motherboard....
by Stefan Reinauer 14 Feb '12

14 Feb '12

* ali hagigat <hagigatali(a)gmail.com> [120214 18:48]: > I have initialized Intel 82815 SDRAM controller but for a special type > of RAM without reading SPD registers. I know that DRP register is : > 0xCC. I added the code to Coreboot. > > I tested much and concluded that RAM has a problem in a way as you > guys told me before. When i change the hardwaremain() , even adding > some code which are bypassed, the results of the post code numbers > become different! > > I do not know what to do! c_start.S is OK and it is executed and the > program starts executing hardwaremain() but adding code to the > hardwaremain() any where seems to disorder printed post code values. > > Is there any interrupt or timer set immediately after hardwaremain()? > > I checked coreboot_ram in build/. The assembly code of hardwaremian() seems OK. > > > void sdram_enable(void) > { > asm("pushal"); > asm("push %eax"); > asm("push %ebx"); > asm("push %ecx"); > asm("push %edx"); > asm("push %esi"); > asm("push %edi"); > asm("push %esp"); > asm("push %ebp"); > asm("pushfl"); > asm("jmp firstlbl"); > asm("mov %ax, %ax"); > asm("nop"); [..] There's a number of things wrong with this approach: * if you don't use asm volatile instead of asm, gcc is free to reorder any of those statements as it sees fit. * you need to put all of the code in one asm volatile statement, or gcc will attempt to clean up after each of the statements or overwrite registers as it sees fit. But generally, I suggest you rewrite this in C, so it's a lot more readable... Stefan

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Patch set updated for coreboot: ee068e8 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
by Marc Jones 14 Feb '12

14 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/627 -gerrit commit ee068e84d951b1d198007371d767b920e82ba149 Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/mtrr/amd_mtrr.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index c5e01b1..54a70e2 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -114,12 +114,13 @@ void amd_setup_mtrrs(void) msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later const int cpu_id = cpuid_eax(0x80000001); + printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); const int has_tom2wb = - (((cpu_id>>8 )&0xf) > 0xf) || // Family > 0F + (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables if(has_tom2wb) - printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later, using TOM2WB instead of MTRR above 4GB\n"); + printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n"); /* Enable the access to AMD RdDram and WrDram extension bits */ disable_cache();

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"Fix multipleVGA cards resource conflict on Windows" broke my vga
by Denis 'GNUtoo' Carikli 14 Feb '12

14 Feb '12

hi, I've an M4A785T-M which contains one onboard graphic card, but it has 2 VGA extension roms. one seem to be for HDMI, and the other for VGA. reverting the commit makes VGA appear on my monitor. I've tried to add one option rom only, as usual, and nothing appeared on my monitor with that comit. Then I removed the VGA rom and with cbfstool I added both VGA rom. Nothing appeared on my monitor either... Should I give some logs(it's quite long to get since I've to reflash with an external programmer). Denis.

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recommend mini-itx motherboard
by green 14 Feb '12

14 Feb '12

I am looking for a fanless mini-pc for running Debian and would like, if possible, to run 100% free software on it. So I followed all the OK links in the v4 section of http://www.coreboot.org/Supported_Motherboards and read the support tables and only found 2: http://www.coreboot.org/Avalue_EAX_785E http://www.coreboot.org/GIGABYTE_GA-M57SLI-S4 that are actually close to being fully tested and supported. Now I am surprised about the claim on the main page that coreboot supports "over 230 different mainboards". That seems to be false...? I do not mean to insult, and acknowledge coreboot's accomplishments regardless. Anyway, is there any recommendation for a mini-itx for desktop use? I would like something fully supported by Linux, and perhaps which could run coreboot also; at least would like to put money on a supportive vendor. Thanks

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New patch to review for coreboot: f299de3 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF.
by Marc Jones 14 Feb '12

14 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/627 -gerrit commit f299de3e00821ddbbe8682c302497228eca968df Author: Marc Jones <marcj303(a)gmail.com> Date: Mon Jan 30 19:30:45 2012 -0700 Fix MTRR TOM2 WB cache setup for AMD CPUs > revF. The MTRR check for WB TOM2 setting was only checking revF, not extended family revisions. All families above revf indicate 0xf in the family field and have additional bits in the extended family field. Change-Id: I93d719789acda6b7c42de7fd6d4bad2da866a25f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/mtrr/amd_mtrr.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index c5e01b1..2348b22 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -114,8 +114,9 @@ void amd_setup_mtrrs(void) msr_t msr, sys_cfg; // Test if this CPU is a Fam 0Fh rev. F or later const int cpu_id = cpuid_eax(0x80000001); + printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id); const int has_tom2wb = - (((cpu_id>>8 )&0xf) > 0xf) || // Family > 0F + (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables if(has_tom2wb)

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porting Coreboot to a new motherboard....
by ali hagigat 14 Feb '12

14 Feb '12

I have initialized Intel 82815 SDRAM controller but for a special type of RAM without reading SPD registers. I know that DRP register is : 0xCC. I added the code to Coreboot. I tested much and concluded that RAM has a problem in a way as you guys told me before. When i change the hardwaremain() , even adding some code which are bypassed, the results of the post code numbers become different! I do not know what to do! c_start.S is OK and it is executed and the program starts executing hardwaremain() but adding code to the hardwaremain() any where seems to disorder printed post code values. Is there any interrupt or timer set immediately after hardwaremain()? I checked coreboot_ram in build/. The assembly code of hardwaremian() seems OK. void sdram_enable(void) { asm("pushal"); asm("push %eax"); asm("push %ebx"); asm("push %ecx"); asm("push %edx"); asm("push %esi"); asm("push %edi"); asm("push %esp"); asm("push %ebp"); asm("pushfl"); asm("jmp firstlbl"); asm("mov %ax, %ax"); asm("nop"); /* Cache disable */ asm("firstlbl:"); asm("mov %cr0, %eax"); asm("and $0x9fffffff, %eax"); asm("or $0x40000000, %eax"); asm("mov %eax, %cr0"); /* Configure the RAM command. */ asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("movw $0x0CFC, %dx"); asm("in %dx, %eax"); asm("and $0x1fffffff, %eax"); asm("or $0x05000000, %eax"); asm("movw $0x0CFC, %dx"); asm("out %eax, %dx"); //general initialization //50-53************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //Res mask asm("and $0x0000F823, %eax"); //Bios => cas 2clk asm("or $0x2fcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //70,72-73************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000070, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("movb $0xc0, %al"); asm("out %al, %dx"); asm("mov $0x0cfe, %dx"); asm("inw %dx, %ax"); //Res mask asm("and $0x7704, %ax"); //Bios asm("or $0x0012, %ax"); asm("mov $0x0cfe, %dx"); asm("out %ax, %dx"); //92-93**************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000090, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfe, %dx"); asm("movw $0xff5c, %ax"); asm("out %ax, %dx"); //#94-95***************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000094, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfe, %dx"); asm("inw %dx, %ax"); //#Res mask asm("and $0xffc0, %ax"); //#Bios asm("or $0x001c, %ax"); asm("mov $0x0cfe, %dx"); asm("out %ax, %dx"); //#98-9B***************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000098, %eax"); asm("out %eax, %dx"); asm("movw $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x7F887F88, %eax"); //#Bios asm("or $0x80238023, %eax"); asm("movw $0x0cfc, %dx"); asm("out %eax, %dx"); //#9c-9f*************************** asm("mov $0x0cf8, %dx"); asm("mov $0x8000009c, %eax"); asm("out %eax, %dx"); asm(" movw $0x0CFC, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0xFFFF7FFF, %eax"); //#Bios asm("or $0x00008000, %eax"); asm("movw $0x0CFC, %dx"); asm("out %eax, %dx"); //#2c-2f*************************** asm("mov $0x0cf8, %dx"); asm("mov $0x8000002c, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("mov $0x80271043, %eax"); asm("out %eax, %dx"); //58-5b************************** asm("mov $0x0cf8, %dx"); asm("mov $0x80000058, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); asm("and $0xcccccf7f, %eax"); asm("or $0x33333000, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //5c-5f************************** asm("mov $0x0cf8, %dx"); asm("mov $0x8000005c, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); asm("and $0xcccccccc, %eax"); asm("or $0x33333333, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#;-------------------------------------------------- //#NOP /* 1. Apply NOP. */ //#display 1 asm("mov $1, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0x8fcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov (%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov (%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov (%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov (%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%% asm("mov $1, %di"); asm("delay11:"); asm("mov $200000, %ecx"); asm("delay1:"); asm("dec %ecx"); asm("jnz delay1"); asm("dec %di"); asm("jnz delay11"); //#;-------------------------------------------------- //#precharge /* 2. Precharge all. Wait tRP. */ //#display 2 asm("mov $2, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0xafcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay21:"); asm("mov $1000, %ecx"); asm("delay2:"); asm("dec %ecx"); asm("jnz delay2"); asm("dec %di"); asm("jnz delay21 "); //#;-------------------------------------------------- //#CBR cycle /* 3. Perform 8 refresh cycles. Wait tRC each time. */ //#display 3 asm("mov $3, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%% asm("mov $8, %esi"); asm("refreshcycle:"); asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0xefcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay31:"); asm("mov $1000, %ecx"); asm("delay3:"); asm("dec %ecx"); asm("jnz delay3"); asm("dec %di"); asm("jnz delay31"); asm("dec %esi"); asm("jnz refreshcycle"); //#;-------------------------------------------------- //#mode register set /* 4. Mode register set. Wait two memory cycles. */ //#display 4 asm("mov $4, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0xcfcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%%%% //#1d0 =>150 => 03a //#650 => 650 => 0ca asm("mov $0x0000003a, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x0800003a, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x100000ca, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x180000ca, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay41:"); asm("mov $1000, %ecx"); asm("delay4:"); asm("dec %ecx"); asm("jnz delay4"); asm("dec %di"); asm("jnz delay41"); //#;-------------------------------------------------- //#normal operation /* 5. Normal operation (enables refresh at 15.6usec). */ //#display 5 asm("mov $5, %al"); asm("out %al, $0x80"); //#%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x0cf8, %dx"); asm("mov $0x80000050, %eax"); asm("out %eax, %dx"); asm("mov $0x0cfc, %dx"); asm("in %dx, %eax"); //#Res mask asm("and $0x0000F823, %eax"); //#Bios => cas 2clk asm("or $0x2fcc0140, %eax"); asm("mov $0x0cfc, %dx"); asm("out %eax, %dx"); //#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $0x00000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x08000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x10000000, %ebx"); asm("mov %ds:(%ebx), %eax"); asm("mov $0x18000000, %ebx"); asm("mov %ds:(%ebx), %eax"); //#%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% asm("mov $10, %di"); asm("delay51:"); asm("mov $1000, %ecx"); asm("delay5:"); asm("dec %ecx"); asm("jnz delay5"); asm("dec %di"); asm("jnz delay51"); //#;-------------------------------------------------- asm("mov $10, %al"); asm("out %al, $0x80"); //#;-------------------------------------------------- asm("mov $0xffff, %cx"); asm("delayea1:"); asm("dec %cx"); asm("jnz delayea1"); //asm("mov %cr0, %eax"); //asm("and $0x9fffffff, %eax"); //asm("mov %eax, %cr0"); asm("popfl"); asm("pop %ebp"); asm("pop %esp"); asm("pop %edi"); asm("pop %esi"); asm("pop %edx"); asm("pop %ecx"); asm("pop %ebx"); asm("pop %eax"); asm("popal"); }

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Re: [coreboot] Asus M2V-MX problems
by Rudolf Marek 14 Feb '12

14 Feb '12

Hi, > I was hoping to use the board above to experiment with Coreboot. The board has > the same northbridge as the Asus M2V-MX SE (VIA K8M890) and the same southbridge > as the Asus M2V (VIA 8237A). Both of those chipsets are fully supported. > Thinking that maybe I can at least get the board to boot ASAP, I built Coreboot > for the Asus M2V board to get the southbridge functionality. I also didn't use > the M2V-MX SE profile because it has the SPI chip, while the M2V-MX board has a > PLCC-32 chip. OK > The board booted fine, except I have no video, serial port or ability to write > to the BIOS chip. No video -> you need to include the extracted VGA bios from original BIOS. No serial port looks like wrong superio setup. No ability to write to the chip sounds interesting ? What do you mean by that. Flashrom cannot no-long overwrite the chip content? Maybe just some GPIO needs to be raised. Do you have more PLCC chips or other boards so you can hotswap them? > I know the board booted fine because I was able to SSH into > the box using a PCI network card. Considering that both the M2V and M2V-MX have > the same southbridge chip, I don't understand why there was not serial port or > write access to the BIOS chip. Can someone shed some light on that for me, please. Yep see above. I would suggest to run the superiotool (see utils dir) and check what kind of superio is really there. Or even better provide ./superiotool -d dump best with original bios running if possible. Then you just need to change few lines and you should get serial back. I can even help with that but we need to know not only the chip there but also how the chip is configured. For the VGA you need to use bios_extract and extract the VGA bios from orig bios image and tell coreboot via menu to include that (you need just pci ID lspci -n will tell) > My other problem is I would like to create a build profile for the M2V-MX using > the code from the M2V for the southbridge and the code from the M2V-MX SE for > the northbridge. Is that a good idea or would I have to do some other things? > I learned C programming in 1993 and used it only until 1998; I am a little > rusty. Well C is simple you will got it back soon. > My ability to make sense of low-level chipset stuff is also very > narrow. If you ask good questions you will get answers. > However, I am a fast learner and I am desperate to get something > accomplished for a homebrew thin client project that I have spent way too much > time working on. > > My goal is to extend the life of boards that people send in for recycling by > turning them into more reliable diskless information terminals. A nice coreboot use! Thanks Rudolf

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Patch set updated for coreboot: 7a8a868 Add support for RAM-less multi-processor init
by Kyösti Mälkki 14 Feb '12

14 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/454 -gerrit commit 7a8a868d369166d2f9821c1d61bfe54bfc28b92b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 14 10:39:17 2012 +0200 Add support for RAM-less multi-processor init For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/init/ldscript_failover.lb | 13 +++++++++---- src/cpu/Kconfig | 6 ++++++ 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb index 83e5eb3..61c3d2a 100644 --- a/src/arch/x86/init/ldscript_failover.lb +++ b/src/arch/x86/init/ldscript_failover.lb @@ -29,17 +29,18 @@ MEMORY { TARGET(binary) SECTIONS { - /* Align .rom to next 4 byte boundary so no pad byte appears - * between _rom and _start. + /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. */ .bogus ROMLOC_MIN : { - . = ALIGN(4); + . = ALIGN(4096); ROMLOC = .; } >rom = 0xff /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; + ap_sipi_vector = .; *(.rom.text); *(.rom.data); *(.rom.data.*); @@ -51,7 +52,11 @@ SECTIONS * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096; + + /* Post-check proper SIPI vector. */ + _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment"); + _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR"); /DISCARD/ : { *(.comment) diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 6e65186..0bdef34 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -31,6 +31,12 @@ config SMP This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems. +config AP_SIPI_VECTOR + hex + default 0xfffff000 + help + This must equal address of ap_sipi_vector from bootblock build. + config MMX bool help

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New patch to review for coreboot: 95aad86 Fixes Fam10/SR5650 cpu not recognized message.
by Marc Jones 14 Feb '12

14 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/633 -gerrit commit 95aad867212c87fde722934a536e14ca78f0c9f9 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 15:08:22 2012 -0700 Fixes Fam10/SR5650 cpu not recognized message. Extend the Family10 revisions checked byt the printk message. Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/sr5650/early_setup.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 50f836e..32bdd7f 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -91,7 +91,7 @@ static void get_cpu_rev(void) printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); - else if (eax <= 0x100f00) + else if (eax <= 0x100fa0) printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); else printk(BIOS_INFO, "CPU Rev is not recognized.\n");

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New patch to review for coreboot: 0d7d667 Force SB600 bootblock to use I/O for PCI config
by Marc Jones 14 Feb '12

14 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/632 -gerrit commit 0d7d6676e9c1def4d26432aa481752dbbabd3bec Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Feb 2 14:50:02 2012 -0700 Force SB600 bootblock to use I/O for PCI config If PCI config cycles use MMIO instead of I/O in the SB600 bootblock code the cycles will go nowhere since the MMIO feature hasn't been configured yet. This change forces the cycles to use I/O and configures the southbridge decode range to what is defined by the mainboards Kconfig. Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/sb600/bootblock.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb600/bootblock.c b/src/southbridge/amd/sb600/bootblock.c index 7007622..45991ee 100644 --- a/src/southbridge/amd/sb600/bootblock.c +++ b/src/southbridge/amd/sb600/bootblock.c @@ -37,19 +37,19 @@ static void sb600_enable_rom(void) u8 reg8; device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, - PCI_DEVICE_ID_ATI_SB600_LPC), 0); + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB600_LPC), 0); /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_read_config8(dev, 0x48); + reg8 = pci_io_read_config8(dev, 0x48); reg8 |= (1 << 3) | (1 << 4); - pci_write_config8(dev, 0x48, reg8); + pci_io_write_config8(dev, 0x48, reg8); /* LPC ROM address range 1: */ /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_write_config16(dev, 0x68, 0x000e); + pci_io_write_config16(dev, 0x68, 0x000e); /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_write_config16(dev, 0x6a, 0x000f); + pci_io_write_config16(dev, 0x6a, 0x000f); /* LPC ROM address range 2: */ /* @@ -59,9 +59,9 @@ static void sb600_enable_rom(void) * 0xffe0(0000): 2MB * 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); /* 4 MB */ /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_write_config16(dev, 0x6e, 0xffff); + pci_io_write_config16(dev, 0x6e, 0xffff); } static void bootblock_southbridge_init(void)

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coreboot February 2012