coreboot February 2012

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Patch set updated for coreboot: 929b6ee Intel cpus: apply un-written naming rules
by Kyösti Mälkki 10 Feb '12

10 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/618 -gerrit commit 929b6ee50329b5850f4f0b9a1bc8010cc682f534 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 10 13:32:13 2012 +0200 Intel cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x. Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/Kconfig | 2 +- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/bga956/Kconfig | 3 --- src/cpu/intel/bga956/Makefile.inc | 12 ------------ src/cpu/intel/bga956/bga956.c | 7 ------- src/cpu/intel/bga956/chip.h | 4 ---- src/cpu/intel/model_1067x/Kconfig | 2 +- src/cpu/intel/model_6ex/Kconfig | 2 +- src/cpu/intel/model_6fx/Kconfig | 2 +- src/cpu/intel/socket_BGA956/Kconfig | 3 +++ src/cpu/intel/socket_BGA956/Makefile.inc | 12 ++++++++++++ src/cpu/intel/socket_BGA956/chip.h | 4 ++++ src/cpu/intel/socket_BGA956/socket_BGA956.c | 6 ++++++ src/cpu/intel/socket_LGA771/Kconfig | 1 - src/cpu/intel/socket_mFCPGA478/Kconfig | 4 ++-- src/mainboard/intel/eagleheights/devicetree.cb | 2 +- 16 files changed, 33 insertions(+), 35 deletions(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 31c701c..81a834c 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -16,9 +16,9 @@ source src/cpu/intel/model_f3x/Kconfig source src/cpu/intel/model_f4x/Kconfig source src/cpu/intel/ep80579/Kconfig # Sockets/Slots -source src/cpu/intel/bga956/Kconfig source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/slot_1/Kconfig +source src/cpu/intel/socket_BGA956/Kconfig source src/cpu/intel/socket_FC_PGA370/Kconfig source src/cpu/intel/socket_mFCBGA479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 274c101..05f947d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -4,7 +4,7 @@ # Therefore: ONLY include Makefile.inc from socket directories! subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 -subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 diff --git a/src/cpu/intel/bga956/Kconfig b/src/cpu/intel/bga956/Kconfig deleted file mode 100644 index e70c48b..0000000 --- a/src/cpu/intel/bga956/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config CPU_INTEL_SOCKET_BGA956 - bool - select CPU_INTEL_CORE2 diff --git a/src/cpu/intel/bga956/Makefile.inc b/src/cpu/intel/bga956/Makefile.inc deleted file mode 100644 index a0ace12..0000000 --- a/src/cpu/intel/bga956/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -ramstage-y += bga956.c -subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading - -# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/bga956/bga956.c b/src/cpu/intel/bga956/bga956.c deleted file mode 100644 index 3469215..0000000 --- a/src/cpu/intel/bga956/bga956.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - - -struct chip_operations cpu_intel_bga956_ops = { - CHIP_NAME("BGA956 CPU") -}; diff --git a/src/cpu/intel/bga956/chip.h b/src/cpu/intel/bga956/chip.h deleted file mode 100644 index 0f32d33..0000000 --- a/src/cpu/intel/bga956/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -extern struct chip_operations cpu_intel_bga956_ops; - -struct cpu_intel_bga956_config { -}; diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 4ddba39..b079922 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_1067X bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 89005b8..31d24bd 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE +config CPU_INTEL_MODEL_6EX bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 2551057..851685c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_6FX bool select SMP select SSE2 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig new file mode 100644 index 0000000..a764348 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -0,0 +1,3 @@ +config CPU_INTEL_SOCKET_BGA956 + bool + select CPU_INTEL_MODEL_1067X diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc new file mode 100644 index 0000000..a290e69 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -0,0 +1,12 @@ +ramstage-y += socket_BGA956.c +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_BGA956/chip.h b/src/cpu/intel/socket_BGA956/chip.h new file mode 100644 index 0000000..68ec1d2 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_BGA956_ops; + +struct cpu_intel_socket_BGA956_config { +}; diff --git a/src/cpu/intel/socket_BGA956/socket_BGA956.c b/src/cpu/intel/socket_BGA956/socket_BGA956.c new file mode 100644 index 0000000..53667c1 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/socket_BGA956.c @@ -0,0 +1,6 @@ +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_socket_BGA956_ops = { + CHIP_NAME("Socket BGA956 CPU") +}; diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 0821c3e..62bd17b 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,7 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool select CPU_INTEL_MODEL_6FX - select CPU_INTEL_CORE2 select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 3f39303..2d241cf 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -5,8 +5,8 @@ if CPU_INTEL_SOCKET_MFCPGA478 config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_CORE - select CPU_INTEL_CORE2 + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX select MMX select SSE select CACHE_AS_RAM diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index e628dda..9971264 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -65,7 +65,7 @@ chip northbridge/intel/i3100 end end device lapic_cluster 0 on - chip cpu/intel/bga956 + chip cpu/intel/socket_BGA956 device lapic 0 on end end end

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New patch to review for coreboot: b8948df Intel cpus: apply un-written naming rules
by Kyösti Mälkki 10 Feb '12

10 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/618 -gerrit commit b8948dffe9dc658a915399f80a0e06d78bf983f4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 10 12:42:49 2012 +0200 Intel cpus: apply un-written naming rules Kconfig directives to select chip drivers for compile literally match the chip directory names capitalized and underscored. Note: CPU_INTEL_CORE2 was used on both model_6fx and model_1067x. Change-Id: I8fa5ba71b14dcce79ab2a2c1c69b3bc36edbdea0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/bga956/Kconfig | 3 --- src/cpu/intel/bga956/Makefile.inc | 12 ------------ src/cpu/intel/bga956/bga956.c | 7 ------- src/cpu/intel/bga956/chip.h | 4 ---- src/cpu/intel/model_1067x/Kconfig | 2 +- src/cpu/intel/model_6ex/Kconfig | 2 +- src/cpu/intel/model_6fx/Kconfig | 2 +- src/cpu/intel/socket_BGA956/Kconfig | 3 +++ src/cpu/intel/socket_BGA956/Makefile.inc | 12 ++++++++++++ src/cpu/intel/socket_BGA956/chip.h | 4 ++++ src/cpu/intel/socket_BGA956/socket_BGA956.c | 7 +++++++ src/cpu/intel/socket_LGA771/Kconfig | 1 - src/cpu/intel/socket_mFCPGA478/Kconfig | 4 ++-- src/mainboard/intel/eagleheights/devicetree.cb | 2 +- 15 files changed, 33 insertions(+), 34 deletions(-) diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 274c101..05f947d 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -4,7 +4,7 @@ # Therefore: ONLY include Makefile.inc from socket directories! subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 -subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += socket_BGA956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 diff --git a/src/cpu/intel/bga956/Kconfig b/src/cpu/intel/bga956/Kconfig deleted file mode 100644 index e70c48b..0000000 --- a/src/cpu/intel/bga956/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -config CPU_INTEL_SOCKET_BGA956 - bool - select CPU_INTEL_CORE2 diff --git a/src/cpu/intel/bga956/Makefile.inc b/src/cpu/intel/bga956/Makefile.inc deleted file mode 100644 index a0ace12..0000000 --- a/src/cpu/intel/bga956/Makefile.inc +++ /dev/null @@ -1,12 +0,0 @@ -ramstage-y += bga956.c -subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading - -# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. -cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/bga956/bga956.c b/src/cpu/intel/bga956/bga956.c deleted file mode 100644 index 3469215..0000000 --- a/src/cpu/intel/bga956/bga956.c +++ /dev/null @@ -1,7 +0,0 @@ -#include <device/device.h> -#include "chip.h" - - -struct chip_operations cpu_intel_bga956_ops = { - CHIP_NAME("BGA956 CPU") -}; diff --git a/src/cpu/intel/bga956/chip.h b/src/cpu/intel/bga956/chip.h deleted file mode 100644 index 0f32d33..0000000 --- a/src/cpu/intel/bga956/chip.h +++ /dev/null @@ -1,4 +0,0 @@ -extern struct chip_operations cpu_intel_bga956_ops; - -struct cpu_intel_bga956_config { -}; diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig index 4ddba39..b079922 100644 --- a/src/cpu/intel/model_1067x/Kconfig +++ b/src/cpu/intel/model_1067x/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_1067X bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig index 89005b8..31d24bd 100644 --- a/src/cpu/intel/model_6ex/Kconfig +++ b/src/cpu/intel/model_6ex/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE +config CPU_INTEL_MODEL_6EX bool select SMP select SSE2 diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig index 2551057..851685c 100644 --- a/src/cpu/intel/model_6fx/Kconfig +++ b/src/cpu/intel/model_6fx/Kconfig @@ -1,4 +1,4 @@ -config CPU_INTEL_CORE2 +config CPU_INTEL_MODEL_6FX bool select SMP select SSE2 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig new file mode 100644 index 0000000..a764348 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -0,0 +1,3 @@ +config CPU_INTEL_SOCKET_BGA956 + bool + select CPU_INTEL_MODEL_1067X diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc new file mode 100644 index 0000000..a290e69 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -0,0 +1,12 @@ +ramstage-y += socket_BGA956.c +subdirs-y += ../model_1067x +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../hyperthreading + +# Use Intel Core (not Core 2) code for CAR init, any CPU might be used. +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/socket_BGA956/chip.h b/src/cpu/intel/socket_BGA956/chip.h new file mode 100644 index 0000000..29b220d --- /dev/null +++ b/src/cpu/intel/socket_BGA956/chip.h @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_bga956_ops; + +struct cpu_intel_socket_bga956_config { +}; diff --git a/src/cpu/intel/socket_BGA956/socket_BGA956.c b/src/cpu/intel/socket_BGA956/socket_BGA956.c new file mode 100644 index 0000000..4609a91 --- /dev/null +++ b/src/cpu/intel/socket_BGA956/socket_BGA956.c @@ -0,0 +1,7 @@ +#include <device/device.h> +#include "chip.h" + + +struct chip_operations cpu_intel_socket_bga956_ops = { + CHIP_NAME("Socket BGA956 CPU") +}; diff --git a/src/cpu/intel/socket_LGA771/Kconfig b/src/cpu/intel/socket_LGA771/Kconfig index 0821c3e..62bd17b 100644 --- a/src/cpu/intel/socket_LGA771/Kconfig +++ b/src/cpu/intel/socket_LGA771/Kconfig @@ -1,7 +1,6 @@ config CPU_INTEL_SOCKET_LGA771 bool select CPU_INTEL_MODEL_6FX - select CPU_INTEL_CORE2 select SSE2 select MMX select AP_IN_SIPI_WAIT diff --git a/src/cpu/intel/socket_mFCPGA478/Kconfig b/src/cpu/intel/socket_mFCPGA478/Kconfig index 3f39303..2d241cf 100644 --- a/src/cpu/intel/socket_mFCPGA478/Kconfig +++ b/src/cpu/intel/socket_mFCPGA478/Kconfig @@ -5,8 +5,8 @@ if CPU_INTEL_SOCKET_MFCPGA478 config SOCKET_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_CORE - select CPU_INTEL_CORE2 + select CPU_INTEL_MODEL_6EX + select CPU_INTEL_MODEL_6FX select MMX select SSE select CACHE_AS_RAM diff --git a/src/mainboard/intel/eagleheights/devicetree.cb b/src/mainboard/intel/eagleheights/devicetree.cb index e628dda..9971264 100644 --- a/src/mainboard/intel/eagleheights/devicetree.cb +++ b/src/mainboard/intel/eagleheights/devicetree.cb @@ -65,7 +65,7 @@ chip northbridge/intel/i3100 end end device lapic_cluster 0 on - chip cpu/intel/bga956 + chip cpu/intel/socket_BGA956 device lapic 0 on end end end

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New patch to review for coreboot: 26ddf1e libpayload: code cosmetics
by Mathias Krause 10 Feb '12

10 Feb '12

Mathias Krause (mathias.krause(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/617 -gerrit commit 26ddf1e0580b4b31a4576760bdbe6f640eb8fd72 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Feb 8 10:32:57 2012 +0100 libpayload: code cosmetics Be consistend with coding style at least within a function -- don't mix sizeof with plain values. Change-Id: Iefb5b7fe4f54977f5505fc9cea65c9c4af3e7f3a Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- payloads/libpayload/drivers/options.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 8161c22..7c76251 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -309,7 +309,7 @@ int set_option_from_string(const struct nvram_accessor *nvram, struct cb_cmos_op switch (cmos_entry->config) { case 'h': /* only works on little endian */ - raw = malloc(8); + raw = malloc(sizeof(u64)); *(u64*)raw = strtoull(value, NULL, 0); break; case 's':

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New patch to review for coreboot: ec43d38 libpayload: fix possible mem leak in get_option_as_string()
by Mathias Krause 10 Feb '12

10 Feb '12

Mathias Krause (mathias.krause(a)secunet.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/616 -gerrit commit ec43d3821cc94bc7d600ed8e63d903196160d1c7 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Wed Feb 8 10:31:42 2012 +0100 libpayload: fix possible mem leak in get_option_as_string() Change-Id: I7c3adbd1b72be81585bbaabb42532fc4cad57f58 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> --- payloads/libpayload/drivers/options.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/payloads/libpayload/drivers/options.c b/payloads/libpayload/drivers/options.c index 10d165e..8161c22 100644 --- a/payloads/libpayload/drivers/options.c +++ b/payloads/libpayload/drivers/options.c @@ -292,7 +292,7 @@ int get_option_as_string(const struct nvram_accessor *nvram, struct cb_cmos_opti *dest = strdup((const char*)cmos_enum->text); break; default: /* fail */ - return 1; + ret = 1; } free(raw); return ret;

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Patch merged into coreboot/master: 74c0819 i5000: halt second BSP
by gerrit＠coreboot.org 10 Feb '12

10 Feb '12

the following patch was just integrated into master: commit 74c0819a95be57196d9f25aebbf9f61aa8114749 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Thu Feb 9 22:30:52 2012, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Fri Feb 10 10:28:17 2012, giving +2 See http://review.coreboot.org/615 for details. -gerrit

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Patch set updated for coreboot: 74c0819 i5000: halt second BSP
by Sven Schnelle 09 Feb '12

09 Feb '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit 74c0819a95be57196d9f25aebbf9f61aa8114749 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/Makefile.inc | 1 + src/northbridge/intel/i5000/halt_second_bsp.S | 29 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..5e75159 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..a1a1b15 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli +loop: hlt + jmp loop + +1: /* Restore BIST */ + mov %ebp, %eax

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Patch set updated for coreboot: 8c64567 i5000: halt second BSP
by Sven Schnelle 09 Feb '12

09 Feb '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit 8c64567a2309229fba3a891fe15b0d55da2ff0b0 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/Makefile.inc | 1 + src/northbridge/intel/i5000/halt_second_bsp.S | 29 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..5e75159 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..4d52224 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,29 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + /* degrade BSP to AP */ + mov $0x1b, %ecx + rdmsr + andl $(~0x100), %eax + wrmsr + + cli + hlt +tloop: jmp tloop + +1: /* Restore BIST */ + mov %ebp, %eax

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Patch merged into coreboot/master: 3220062 Add Intel Socket LGA771
by gerrit＠coreboot.org 09 Feb '12

09 Feb '12

the following patch was just integrated into master: commit 3220062a8c6312889c98688c6cee0ced13e31dbf Author: Sven Schnelle <svens(a)stackframe.org> Date: Fri Dec 2 16:21:35 2011 +0100 Add Intel Socket LGA771 Change-Id: Iee7d3ff2884d8c43ff1af498160589e551bc9cc8 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> Build-Tested: build bot (Jenkins) at Sat Dec 17 20:02:48 2011, giving +1 Reviewed-By: Sven Schnelle <svens(a)stackframe.org> at Thu Feb 9 21:12:32 2012, giving +2 See http://review.coreboot.org/492 for details. -gerrit

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New patch to review for coreboot: e5ce5d2 i5000: halt second BSP
by Sven Schnelle 09 Feb '12

09 Feb '12

Sven Schnelle (svens(a)stackframe.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/615 -gerrit commit e5ce5d2160acc69fae296c1fcf89f2c12dadd1e3 Author: Sven Schnelle <svens(a)stackframe.org> Date: Thu Feb 9 21:05:20 2012 +0100 i5000: halt second BSP If both FSBs on i5000 are equipped with CPU packages, one CPU from each package is elected as BSP. To prevent races between both BSPs, hlt the second BSP. Change-Id: I6bfcb17d34e9f028280acff1694309e37307ec21 Signed-off-by: Sven Schnelle <svens(a)stackframe.org> --- src/northbridge/intel/i5000/Makefile.inc | 1 + src/northbridge/intel/i5000/halt_second_bsp.S | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+), 0 deletions(-) diff --git a/src/northbridge/intel/i5000/Makefile.inc b/src/northbridge/intel/i5000/Makefile.inc index a5623c0..0c3ce0d 100644 --- a/src/northbridge/intel/i5000/Makefile.inc +++ b/src/northbridge/intel/i5000/Makefile.inc @@ -19,3 +19,4 @@ driver-y += northbridge.c romstage-y += raminit.c udelay.c +cpu_incs += src/northbridge/intel/i5000/halt_second_bsp.S \ No newline at end of file diff --git a/src/northbridge/intel/i5000/halt_second_bsp.S b/src/northbridge/intel/i5000/halt_second_bsp.S new file mode 100644 index 0000000..da13178 --- /dev/null +++ b/src/northbridge/intel/i5000/halt_second_bsp.S @@ -0,0 +1,23 @@ + /* Save BIST result */ + + movl %eax, %ebp + + /* Read the semaphore register of i5000 (BOFL0). + If it returns zero, it means there was already + another read by another CPU */ + + movl $0x800080c0, %eax + movw $0xcf8, %dx + outl %eax, %dx + + addw $4, %dx + inl %dx, %eax + cmp $0, %eax + jne 1f + + cli + hlt +tloop: jmp tloop + +1: /* Restore BIST */ + mov %ebp, %eax

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Patch merged into coreboot/master: ede2da9 VIA cpus: apply un-written naming rules
by gerrit＠coreboot.org 09 Feb '12

09 Feb '12

the following patch was just integrated into master: commit ede2da9d2d9fffcf8a57d19958bedf595cc46f01 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 9 16:51:38 2012 +0200 VIA cpus: apply un-written naming rules Rename files and directories: model_c3 -> c3 model_c7 -> c7 Change-Id: If144fc501e8ae44b347ac44fa90c689c33a8e126 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Build-Tested: build bot (Jenkins) at Thu Feb 9 16:08:30 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Thu Feb 9 19:45:49 2012, giving +2 See http://review.coreboot.org/614 for details. -gerrit

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coreboot February 2012