coreboot February 2012

coreboot@coreboot.org

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348 discussions

New patch to review for coreboot: 2e3c13a Intel cpus: add NetBurst compatibility to model_6ex CAR
by Kyösti Mälkki 16 Feb '12

16 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/644 -gerrit commit 2e3c13a0b9ee6dde5a2db7b25ba3019107790f51 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 23:12:04 2012 +0200 Intel cpus: add NetBurst compatibility to model_6ex CAR P4 CPUs with NetBurst architecture have no MSR 0x11e. I have previously tested that a HT-enabled P4 (model f25) can execute this but will not have cache-as-ram enabled. Should work for non-HT P4. Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/Kconfig | 8 ++++++++ src/cpu/intel/model_6ex/cache_as_ram.inc | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletions(-) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index 81a834c..4e4e2ee 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -1,3 +1,11 @@ + +config INTEL_NETBURST + bool + default n + help + Select Y to bypass MSR 0x11e during CAR. + FIXME: Runtime CPUID check instead. + # CPU models source src/cpu/intel/model_6xx/Kconfig source src/cpu/intel/model_67x/Kconfig diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 5a29744..4505e0e 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -82,11 +82,19 @@ clear_mtrrs: orl $MTRRdefTypeEn, %eax wrmsr - /* Enable L2 cache. */ +#if !CONFIG_INTEL_NETBURST + /* Enable L2 cache Write-Back (WBINVD and FLUSH#). + * This MSR does not exist on NetBurst architecture. + * + * Description says this bit enables use of WBINVD and FLUSH#. + * Should this be set only after the system bus and/or memory + * controller can successfully handle write cycles? + */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr +#endif /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax

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New patch to review for coreboot: 69dcef7 Intel model_6ex: minor CAR fixes
by Kyösti Mälkki 16 Feb '12

16 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/643 -gerrit commit 69dcef76380deb90f2dca58a086393c00b15e6c3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 22:38:16 2012 +0200 Intel model_6ex: minor CAR fixes Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_6ex/cache_as_ram.inc | 23 +++++++++++++---------- 1 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index cbfa4f8..5a29744 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -21,6 +21,10 @@ #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/post_code.h> +#include <cpu/x86/lapic_def.h> + +/* Macro to access Local APIC registers at default base. */ +#define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) @@ -37,9 +41,9 @@ cache_as_ram: post_code(0x20) /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) + movl LAPIC(ICR), %edi + movl $(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT), %eax + movl %eax, (%edi) /* Zero out all fixed range and variable range MTRRs. */ movl $mtrr_table, %esi @@ -91,11 +95,10 @@ clear_mtrrs: movl %eax, %cr0 /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax + cld xorl %eax, %eax + movl $CACHE_AS_RAM_BASE, %edi + movl $(CACHE_AS_RAM_SIZE / 4), %ecx rep stosl /* Enable Cache-as-RAM mode by disabling cache. */ @@ -130,11 +133,10 @@ clear_mtrrs: /* Set up the stack pointer. */ #if CONFIG_USBDEBUG /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp #else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax + movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp #endif - movl %eax, %esp /* Restore the BIST result. */ movl %ebp, %eax @@ -145,6 +147,7 @@ clear_mtrrs: /* Call romstage.c main function. */ call main + addl $4, %esp post_code(0x2f)

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New patch to review for coreboot: 1a339d8 Intel model_106cx: change CAR to model_6ex
by Kyösti Mälkki 16 Feb '12

16 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/642 -gerrit commit 1a339d88a24946a8ca238f739b0f652e932dd382 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 20:28:30 2012 +0200 Intel model_106cx: change CAR to model_6ex Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_106cx/Makefile.inc | 2 +- src/cpu/intel/model_106cx/cache_as_ram.inc | 245 ---------------------------- 2 files changed, 1 insertions(+), 246 deletions(-) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index edcd01c..018febc 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc deleted file mode 100644 index 605bd70..0000000 --- a/src/cpu/intel/model_106cx/cache_as_ram.inc +++ /dev/null @@ -1,245 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <cpu/x86/stack.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/post_code.h> - -#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) - -#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE -#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE - - /* Save the BIST result. */ - movl %eax, %ebp - -cache_as_ram: - post_code(0x20) - - /* Send INIT IPI to all excluding ourself. */ - movl $0x000C4500, %eax - movl $0xFEE00300, %esi - movl %eax, (%esi) - - /* Zero out all fixed range and variable range MTRRs. */ - movl $mtrr_table, %esi - movl $((mtrr_table_end - mtrr_table) / 2), %edi - xorl %eax, %eax - xorl %edx, %edx -clear_mtrrs: - movw (%esi), %bx - movzx %bx, %ecx - wrmsr - add $2, %esi - dec %edi - jnz clear_mtrrs - - /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~0x00000cff), %eax - wrmsr - - /* Set Cache-as-RAM base address. */ - movl $(MTRRphysBase_MSR(0)), %ecx - movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - - /* Set Cache-as-RAM mask. */ - movl $(MTRRphysMask_MSR(0)), %ecx - movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - /* Enable L2 cache. */ - movl $0x11e, %ecx - rdmsr - orl $(1 << 8), %eax - wrmsr - - /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - invd - movl %eax, %cr0 - - /* Clear the cache memory reagion. */ - movl $CACHE_AS_RAM_BASE, %esi - movl %esi, %edi - movl $(CACHE_AS_RAM_SIZE / 4), %ecx - // movl $0x23322332, %eax - xorl %eax, %eax - rep stosl - - /* Enable Cache-as-RAM mode by disabling cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - -#if CONFIG_XIP_ROM_SIZE - /* Enable cache for our code in Flash because we do XIP here */ - movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html - */ - movl $copy_and_run, %eax - andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax - orl $MTRR_TYPE_WRBACK, %eax - wrmsr - - movl $MTRRphysMask_MSR(1), %ecx - movl $CPU_PHYSMASK_HI, %edx - movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax - wrmsr -#endif /* CONFIG_XIP_ROM_SIZE */ - - /* Enable cache. */ - movl %cr0, %eax - andl $(~((1 << 30) | (1 << 29))), %eax - movl %eax, %cr0 - - /* Set up the stack pointer. */ -#if CONFIG_USBDEBUG - /* Leave some space for the struct ehci_debug_info. */ - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax -#else - movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax -#endif - movl %eax, %esp - - /* Restore the BIST result. */ - movl %ebp, %eax - movl %esp, %ebp - pushl %eax - - post_code(0x23) - - /* Call romstage.c main function. */ - call main - - post_code(0x2f) - - post_code(0x30) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x31) - - /* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - andl $(~MTRRdefTypeEn), %eax - wrmsr - - post_code(0x31) - - invd - - post_code(0x33) - - /* Enable cache. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x36) - - /* Disable cache. */ - movl %cr0, %eax - orl $(1 << 30), %eax - movl %eax, %cr0 - - post_code(0x38) - - /* Enable Write Back and Speculative Reads for the first 1MB. */ - movl $MTRRphysBase_MSR(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr - - post_code(0x39) - - /* And enable cache again after setting MTRRs. */ - movl %cr0, %eax - andl $~((1 << 30) | (1 << 29)), %eax - movl %eax, %cr0 - - post_code(0x3a) - - /* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx - rdmsr - orl $MTRRdefTypeEn, %eax - wrmsr - - post_code(0x3b) - - /* Invalidate the cache again. */ - invd - - post_code(0x3c) - - /* Clear boot_complete flag. */ - xorl %ebp, %ebp -__main: - post_code(POST_PREPARE_RAMSTAGE) - cld /* Clear direction flag. */ - - movl %ebp, %esi - - movl $ROMSTAGE_STACK, %esp - movl %esp, %ebp - pushl %esi - call copy_and_run - -.Lhlt: - post_code(POST_DEAD_CODE) - hlt - jmp .Lhlt - -mtrr_table: - /* Fixed MTRRs */ - .word 0x250, 0x258, 0x259 - .word 0x268, 0x269, 0x26A - .word 0x26B, 0x26C, 0x26D - .word 0x26E, 0x26F - /* Variable MTRRs */ - .word 0x200, 0x201, 0x202, 0x203 - .word 0x204, 0x205, 0x206, 0x207 - .word 0x208, 0x209, 0x20A, 0x20B - .word 0x20C, 0x20D, 0x20E, 0x20F -mtrr_table_end: -

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New patch to review for coreboot: 3eb82eb Intel cpus: cache actual size of the Flash ROM device
by Kyösti Mälkki 16 Feb '12

16 Feb '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/641 -gerrit commit 3eb82ebe06369ad6f278319989c3c574a3c9264a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 16 20:11:31 2012 +0200 Intel cpus: cache actual size of the Flash ROM device Cache was enabled for the last 4 MB below 4 GB when ramstage is loaded using model_6ex CAR implementation. This does not cover the case of a 8 MB Flash and could overlap with some system device placed at high memory. Use the actual device size for the cache region. Mainboard may override this with Kconfig CACHE_ROM_SIZE if necessary. Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_6ex/cache_as_ram.inc | 9 ++++++--- src/mainboard/Kconfig | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 8f2b1bd..cbfa4f8 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -24,6 +24,9 @@ #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_MAXPHYADDR - 32) - 1) +/* Base address to cache all of Flash ROM, just below 4GB. */ +#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10) + #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE @@ -190,13 +193,13 @@ clear_mtrrs: movl $CPU_PHYSMASK_HI, %edx wrmsr - /* Enable caching and Speculative Reads for the last 4MB. */ + /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx - movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(1), %ecx - movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax movl $CPU_PHYSMASK_HI, %edx wrmsr diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig index cc4e14f..a34bd85 100644 --- a/src/mainboard/Kconfig +++ b/src/mainboard/Kconfig @@ -285,6 +285,10 @@ config ROM_SIZE default 0x800000 if COREBOOT_ROMSIZE_KB_8192 default 0x1000000 if COREBOOT_ROMSIZE_KB_16384 +config CACHE_ROM_SIZE + hex + default ROM_SIZE + config ENABLE_POWER_BUTTON bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL default y if POWER_BUTTON_DEFAULT_ENABLE

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Patch merged into coreboot/master: be7d415 M4A785-M, M4A785T-M: fix SSDT tables
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit be7d4152144497b7318564ef92ae96c16b522305 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Feb 14 22:38:01 2012 +0100 M4A785-M,M4A785T-M: fix SSDT tables This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) Change-Id: I9a9bf955de0a2a7accdbce8561b23596a8641af4 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Build-Tested: build bot (Jenkins) at Wed Feb 15 00:27:00 2012, giving +1 Reviewed-By: Kerry Sheh <shekairui(a)gmail.com> at Thu Feb 16 01:38:38 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 22:41:24 2012, giving +2 See http://review.coreboot.org/636 for details. -gerrit

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Patch merged into coreboot/master: 3887beb M4A785T-M: fix TOM2.
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit 3887beb6955df88880b1a6d359b2f2bbc69117e0 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Feb 14 22:11:23 2012 +0100 M4A785T-M: fix TOM2. This commit is based on the commit 94fa3db36688e8db133aebe14d480b0c4722e4c9 (AMD Mahogany Fam10 ACPI table fixes.) With commit permit to boot without pci=nocrs on the M4A785T-M board. Before the fix dmesg contained the following: [ 0.452071] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.480085] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) [ 0.788222] ACPI Error: [TOM2] Namespace lookup failure, AE_NOT_FOUND (20110112/psargs-359) Now it only contains: [ 0.312102] TOM: 0000000080000000 aka 2048M Change-Id: I5d517604abe938af19b70d57d92c1f973114c1cd Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Build-Tested: build bot (Jenkins) at Wed Feb 15 00:16:43 2012, giving +1 Reviewed-By: Kerry Sheh <shekairui(a)gmail.com> at Thu Feb 16 01:37:04 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 22:35:39 2012, giving +2 See http://review.coreboot.org/635 for details. -gerrit

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Patch merged into coreboot/master: 3904286 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit 3904286e9ec165e90eab5466ef6f1fe6482ce4ef Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 14:37:16 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 19:41:55 2012, giving +2 See http://review.coreboot.org/561 for details. -gerrit

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Patch merged into coreboot/master: 9bf1cc6 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit 9bf1cc623520b43d95ff7e55770fa30590f3b953 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:31:40 2012 +0800 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 13:47:44 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 19:31:09 2012, giving +2 See http://review.coreboot.org/556 for details. -gerrit

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Patch merged into coreboot/master: b0eef97 HWM: Nuvoton W83795G/ADG HWM support
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit b0eef97a218291d9efa44891b67f7ab74e434e51 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:33:21 2012 +0800 HWM: Nuvoton W83795G/ADG HWM support Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 15:52:01 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 21:22:30 2012, giving +2 See http://review.coreboot.org/569 for details. -gerrit

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Patch merged into coreboot/master: 7078147 Mainboard: Supermicro/h8qgi mainboard update
by gerrit＠coreboot.org 16 Feb '12

16 Feb '12

the following patch was just integrated into master: commit 70781479459d047979d698685b7f1393e9178e95 Author: Kerry Sheh <shekairui(a)gmail.com> Date: Tue Feb 7 20:32:38 2012 +0800 Mainboard: Supermicro/h8qgi mainboard update 1. Supermicro H8QGI mainboard update to support both family10 Revison D processor and family15 model 00-0fh processor in one binary image. 2. RD890/SR56X0 IO hub CIMX wrapper support. 3. SP5100/SB700 southbridge CIMX wrapper support. Both 8 cores and 16 Cores InterLagos Opteron Processor are tested on this platform. Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested. Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d Signed-off-by: Kerry Sheh <kerry.she(a)amd.com> Signed-off-by: Kerry Sheh <shekairui(a)gmail.com> Build-Tested: build bot (Jenkins) at Tue Feb 7 15:09:08 2012, giving +1 Reviewed-By: Marc Jones <marcj303(a)gmail.com> at Thu Feb 16 21:16:49 2012, giving +2 See http://review.coreboot.org/567 for details. -gerrit

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coreboot February 2012