coreboot February 2012

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New patch to review for coreboot: 3d3abb2 Remove old AMD fam10 fixme comment
by Marc Jones 21 Feb '12

21 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/672 -gerrit commit 3d3abb2e9ce3a175c9182b6bc3ad17bc3487735b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 21 17:53:13 2012 -0700 Remove old AMD fam10 fixme comment The family10 code had a very slow decompress before the cache settings were fixed. This has been fixed for some time. Remove all the old messages from the serial stream. Change-Id: I476efe1a430f702af394734f354ff69bd053f1d2 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/mainboard/amd/mahogany_fam10/romstage.c | 1 - .../amd/serengeti_cheetah_fam10/romstage.c | 1 - src/mainboard/amd/tilapia_fam10/romstage.c | 1 - src/mainboard/asus/m4a78-em/romstage.c | 1 - src/mainboard/asus/m4a785-m/romstage.c | 1 - src/mainboard/gigabyte/ma785gmt/romstage.c | 1 - src/mainboard/gigabyte/ma78gm/romstage.c | 1 - src/mainboard/iei/kino-780am2-fam10/romstage.c | 1 - src/mainboard/jetway/pa78vm5/romstage.c | 1 - src/mainboard/msi/ms9652_fam10/romstage.c | 1 - src/mainboard/supermicro/h8dmr_fam10/romstage.c | 1 - src/mainboard/supermicro/h8qme_fam10/romstage.c | 1 - src/mainboard/tyan/s2912_fam10/romstage.c | 1 - 13 files changed, 0 insertions(+), 13 deletions(-) diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 04a9e45..dce9baa 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index b41230d..29b00b2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -331,7 +331,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 52cab42..f316395 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -220,7 +220,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 76449cb..a96592d 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 76449cb..a96592d 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -221,7 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 4572169..68f3dcc 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bd81e67..6c25a9e 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -219,7 +219,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 54b364a..f51b3ec 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -222,7 +222,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index b2d4ecb..ba3b208 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -227,7 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_before_pci_init(); post_code(0x42); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index fc8120b..0bf6d11 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -241,7 +241,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index c9fb928..4e243c2 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -240,7 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 870125d..d9d5218 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -290,7 +290,6 @@ post_code(0x40); raminit_amdmct(sysinfo); post_code(0x41); -// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. } diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 97c03b5..df571a0 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -238,7 +238,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }

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New patch to review for coreboot: 617edf7 Revert "Fix multipleVGA cards resource conflict on Windows"
by Marc Jones 21 Feb '12

21 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/671 -gerrit commit 617edf7e746df87616e4ada8a40decabe1231341 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Feb 21 17:44:35 2012 +0100 Revert "Fix multipleVGA cards resource conflict on Windows" This reverts commit 8660a1aa56caeb31bfaf15464285ca650638515e This commit has been found to cause problems with vbios and option rom init in seabios. It has been found by several people and requires more analysis before being recommitted. Change-Id: Ie5f54e417e7a0d8bd8ca4c0a573976afeaa9e230 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/devices/device.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 8ad9787..a2619bf 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -932,6 +932,10 @@ void dev_configure(void) struct device *root; struct device *child; +#if CONFIG_VGA_BRIDGE_SETUP == 1 + set_vga_bridge_bits(); +#endif + printk(BIOS_INFO, "Allocating resources...\n"); root = &dev_root; @@ -1024,10 +1028,6 @@ void dev_configure(void) printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); -#if CONFIG_VGA_BRIDGE_SETUP == 1 - set_vga_bridge_bits(); -#endif - printk(BIOS_INFO, "Done allocating resources.\n"); }

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Patch set updated for coreboot: 2724d28 Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
by Marc Jones 21 Feb '12

21 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670 -gerrit commit 2724d286cbad4ae8a3a6f63719bc1098cc94360f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); - print_t(" ECCInit 2 \n"); - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ /* Reset MC4_STS. */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -212,12 +208,22 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /*Node has Dram */ } /*if Node present */ } - print_t(" ECCInit 3 \n"); if(mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..d126a95 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + printk(BIOS_DEBUG, "mctAutoInitMCT_D Done: Global Status: %x\n", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6f6767a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + print_tx(" ECC enabled on node: ", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; }

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New patch to review for coreboot: 90fc6a1 Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
by Marc Jones 21 Feb '12

21 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/670 -gerrit commit 90fc6a1bb7ca57a24e6d0456cb6323fb384b55e2 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Tue Feb 21 17:06:40 2012 -0700 Fix ECC disable option for AMD Fam10 DDR2 and DDR3. The logic was backwards on the ECC enable/disable option. Also added better debug output when the debug RAM init feature is enabled. Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- src/northbridge/amd/amdmct/mct/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct/mctecc_d.c | 18 ++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 2 +- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 14 +++++++++++++- 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 5abe6d0..36b473a 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -300,7 +300,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0 - print_t("All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c index 87ac3ac..58e61ae 100644 --- a/src/northbridge/amd/amdmct/mct/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c @@ -115,7 +115,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) AllECC = 1; MemClrECC = 0; - print_t(" ECCInit 0 \n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + Node; @@ -133,7 +132,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -164,15 +163,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } /* if Node present */ } - print_t(" ECCInit 1 \n"); if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs); - print_t(" ECCInit 2 \n"); - /* Program the Dram BKScrub CTL to the proper (user selected) value.*/ /* Reset MC4_STS. */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -212,12 +208,22 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /*Node has Dram */ } /*if Node present */ } - print_t(" ECCInit 3 \n"); if(mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 1faed5a..582a1f2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -343,7 +343,7 @@ restartinit: } mct_FinalMCT_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "All Done\n"); + print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus); return; fatalexit: diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index ca03f4b..6f6767a 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -127,7 +127,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) LDramECC = isDramECCEn_D(pDCTstat); if(pDCTstat->ErrCode != SC_RunningOK) { pDCTstat->Status &= ~(1 << SB_ECCDIMMs); - if (OB_NBECC) { + if (!OB_NBECC) { pDCTstat->ErrStatus |= (1 << SB_DramECCDis); } AllECC = 0; @@ -146,6 +146,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) Set_NB32(dev, reg, val); DCTMemClr_Init_D(pMCTstat, pDCTstat); MemClrECC = 1; + print_tx(" ECC enabled on node: ", Node); } } /* this node has ECC enabled dram */ } else { @@ -207,6 +208,17 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); mctHookAfterECC(); + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + if (NodePresent_D(Node)) { + print_tx("ECCInit: Node ", Node); + print_tx("ECCInit: Status ", pDCTstat->Status); + print_tx("ECCInit: ErrStatus ", pDCTstat->ErrStatus); + print_tx("ECCInit: ErrCode ", pDCTstat->ErrCode); + print_t("ECCInit: Done\n"); + } + } return MemClrECC; }

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Patch set updated for coreboot: 6bfce95 asus/m4a785t-m: correct the CPU microcode patch selection
by Denis Carikli 21 Feb '12

21 Feb '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/669 -gerrit commit 6bfce95ce462ea42f08b20a846e07b4c37681b2c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Feb 21 22:29:30 2012 +0100 asus/m4a785t-m: correct the CPU microcode patch selection Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 <ruik> ruik@ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 <ruik> 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 <ruik> the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explained(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 633b994..727ae0c 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -68,7 +68,7 @@ config IRQ_SLOT_COUNT config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000c4.h" + default "mc_patch_0100009f.h" config RAMTOP hex

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New patch to review for coreboot: d8759cd asus/m4a785t-m: correct the CPU microcode patch selection
by Denis Carikli 21 Feb '12

21 Feb '12

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/669 -gerrit commit d8759cd8725469489ac9cc0b83bb53c0d51e54ed Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Tue Feb 21 22:29:30 2012 +0100 asus/m4a785t-m: correct the CPU microcode patch selection Thanks to ruik on #coreboot Freenode IRC channel for explaining to me how to get the cpu revision: Feb 21 22:07:32 <ruik> ruik@ruik:~/coreboot$ cpuid | grep ^00000001 Feb 21 22:07:32 <ruik> 00000001 00020f32 00020800 00000001 178bfbff [..] Feb 21 22:07:44 <ruik> the 20f32 is mine CPUID The rest was just looking at the correspondance in src/cpu/amd/model_10xxx/update_microcode.c like Marc Jones explaned(thanks Marc Jones) in the mailing list here: http://www.coreboot.org/pipermail/coreboot/2012-February/068332.html Change-Id: Ie0f004990e6b65456de009a4dcc306498bdb47e9 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/mainboard/asus/m4a785t-m/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mainboard/asus/m4a785t-m/Kconfig b/src/mainboard/asus/m4a785t-m/Kconfig index 633b994..727ae0c 100644 --- a/src/mainboard/asus/m4a785t-m/Kconfig +++ b/src/mainboard/asus/m4a785t-m/Kconfig @@ -68,7 +68,7 @@ config IRQ_SLOT_COUNT config AMD_UCODE_PATCH_FILE string - default "mc_patch_010000c4.h" + default "mc_patch_0100009f.h" config RAMTOP hex

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New patch to review for coreboot: ee18b94 Revert "Fix multipleVGA cards resource conflict on Windows"
by Marc Jones 21 Feb '12

21 Feb '12

Marc Jones (marcj303(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/668 -gerrit commit ee18b943ef7de736dfa103d66ec1fb1820a49a98 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Feb 21 17:44:35 2012 +0100 Revert "Fix multipleVGA cards resource conflict on Windows" This reverts commit b7929add7bf1b40795e0a16ab08fc47858971ccc This commit has been found to cause problems with vbios and option rom init in seabios. It has been found by several people and requires more analysis before being recommitted. --- src/devices/device.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/devices/device.c b/src/devices/device.c index 8ad9787..a2619bf 100644 --- a/src/devices/device.c +++ b/src/devices/device.c @@ -932,6 +932,10 @@ void dev_configure(void) struct device *root; struct device *child; +#if CONFIG_VGA_BRIDGE_SETUP == 1 + set_vga_bridge_bits(); +#endif + printk(BIOS_INFO, "Allocating resources...\n"); root = &dev_root; @@ -1024,10 +1028,6 @@ void dev_configure(void) printk(BIOS_INFO, "Done setting resources.\n"); print_resource_tree(root, BIOS_SPEW, "After assigning values."); -#if CONFIG_VGA_BRIDGE_SETUP == 1 - set_vga_bridge_bits(); -#endif - printk(BIOS_INFO, "Done allocating resources.\n"); }

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Real-mode trouble with hyper-threaded CPU
by Kyösti Mälkki 21 Feb '12

21 Feb '12

So I have been working with hyper-threaded P4 NetBurst CPUs. Currently I have a dual-socket 604 with model f25 P4 Xeon CPUs that boots with the CAR code I have made available in git [1]. I have received a report of a non-HT f27 booting with my code [1] on a different mainboard and socket 478. On that mainboard, hyper-threaded non-Xeon P4 CPU models f29 and f49 fail before console. Using POST codes, we have traced the issue this far: 1. BSP CPU has successfully sent Start-Up IPI to AP CPU. 2. AP CPU has successfully received Start-Up IPI and has entered ap_sipi_vector and executes code from src/cpu/x86/16bit/entry16.inc At the time AP CPU executes "lidt", it seems both BSP and AP CPUs halt. a) Any reference to this null-limit method in Intel literature? b) Both limit of 0 and base of 0x00 for IDT seem incorrect to me. That would mean IDT is one byte at non-existing RAM adress 0x00. c) There is a longish explanation of LGDT parameter calculation. Why is this not applied to LIDT? Thanks, KM [1] http://review.coreboot.org/607

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Re: [coreboot] porting Coreboot to a new motherboard....
by Darmawan Salihun 20 Feb '12

20 Feb '12

Thanks Ron. I'm looking into it. On 2/20/12, ron minnich <rminnich(a)gmail.com> wrote: > you commented out a number of calls to critical functions. You can't > just simply set a register and assume it all works. Maybe I > misunderstood. > > I think stepan's i945 code is a great example of how to turn on dram. > Or you can look at sdram_enable in the lx440 code for the basic sdram > startup cycle. Don't look at the reset of that code, I am not sure it > was ever tested on real hardware, there's a comment in there about > qemu I don't understand. The lx440 was the second (or first) linuxbios > mainboard, but that's not my code, so I'm just not sure about it. > > ron > -- -------------------------------------------------------------------- -= Human knowledge belongs to the world =-

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Patch merged into coreboot/master: 2703285 libpayload: fix compile error with enabled USB_DEBUG
by gerrit＠coreboot.org 20 Feb '12

20 Feb '12

the following patch was just integrated into master: commit 270328581ec7881676f9d808483953026e473ff1 Author: Mathias Krause <mathias.krause(a)secunet.com> Date: Fri Feb 17 12:23:26 2012 +0100 libpayload: fix compile error with enabled USB_DEBUG Commit c4348d0 ("libpayload: Remove bitfield use from OHCI data structures") missed to adapt a debug message. This patch fixes this. Change-Id: I5f6a4be9c7f6f99cb103926772717e15a3cbca70 Signed-off-by: Mathias Krause <mathias.krause(a)secunet.com> Build-Tested: build bot (Jenkins) at Mon Feb 20 10:57:47 2012, giving +1 Reviewed-By: Peter Stuge <peter(a)stuge.se> at Mon Feb 20 21:46:32 2012, giving +2 See http://review.coreboot.org/653 for details. -gerrit

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coreboot February 2012