coreboot October 2012

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Patch merged into coreboot/master: 5498b3b Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot
by gerrit＠coreboot.org 29 Oct '12

29 Oct '12

the following patch was just integrated into master: commit 5498b3b93e8107a71692b41a7dc49c65fd878a9e Author: Peter Stuge <peter(a)stuge.se> Date: Sat Oct 27 13:45:51 2012 +0200 Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/1636 for details. -gerrit

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New patch to review for coreboot: 0420ca8 tyan s8226: change lapic of lapic_cluster 0 to 0x30
by Siyuan Wang 29 Oct '12

29 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1652 -gerrit commit 0420ca8bac447417e11ec766dc65ad85ede0c47a Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Mon Oct 29 12:08:39 2012 +0800 tyan s8226: change lapic of lapic_cluster 0 to 0x30 amd family15 cpu has a lapic_cluster which is the same level with pci domain. Now, the lapic is 0x20 which is already taken by CPU. there are two CPUs on s8226 and each CPU has 8 cores. CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27. Now, the dmesg complains as follow: do_IRQ: 1.55 No irq handler for vector (irq -1) so I change lapic of lapic_cluster to 0x30. although I am not sure what's the exactly meaning of lapic_cluster, this is a workaround to solve this issue. Change-Id: Ie17820e0f11d11c35e7e2351a454fa8e823bbf2c Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/tyan/s8226/devicetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index 4459019..c7bd8c3 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -19,8 +19,7 @@ chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on chip cpu/amd/agesa/family15 - device lapic 0x20 on end #f15 - #device lapic 0x10 on end #f10 + device lapic 0x30 on end end end device pci_domain 0 on

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Patch merged into coreboot/master: 91b69c6 IEI PM-LX2-800-R10: Added preliminary mainboard support
by gerrit＠coreboot.org 28 Oct '12

28 Oct '12

the following patch was just integrated into master: commit 91b69c6ccd6d56368a7f6212a8c40a13662058ed Author: Ricardo Martins <rasmartins(a)gmail.com> Date: Mon Aug 6 05:40:07 2012 +0100 IEI PM-LX2-800-R10: Added preliminary mainboard support Details for this board are available at http://usa.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000… Support for the IT8888 PCI to ISA bridge will be added in a later patch. Change-Id: Iaefe47f5ad405a56d230c929e5850156eb0f60ae Signed-off-by: Ricardo Martins <rasmartins(a)gmail.com> Build-Tested: build bot (Jenkins) at Mon Aug 6 07:25:52 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Wed Aug 8 20:28:21 2012, giving +2 See http://review.coreboot.org/1152 for details. -gerrit

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Patch set updated for coreboot: 61cf6f6 supermicro h8scm: add agesa version of supermicro
by Siyuan Wang 28 Oct '12

28 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1510 -gerrit commit 61cf6f6f4b7d69336a480e161079c5d6c67b811c Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Sun Oct 28 18:19:38 2012 +0800 supermicro h8scm: add agesa version of supermicro supermicro h8scm has a C32 CPU socket, the details of this board is: http://www.supermicro.com/Aplus/motherboard/Opteron4100/SR56x0/H8SCM-F.cfm we are planning to replace legacy C32 code with agesa and the h8scm_fam10 do not support family 15 CPU, so we update this mainboard with this patch. this code supports memory at 800M Hz of f10 CPU, bu f15 CPU does not has this limitation. Change-Id: I9ca9e70d7f3e82c07e7d36695bf31008db152afb Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/supermicro/Kconfig | 3 + src/mainboard/supermicro/h8scm/BiosCallOuts.c | 516 +++++++ src/mainboard/supermicro/h8scm/BiosCallOuts.h | 78 + src/mainboard/supermicro/h8scm/Kconfig | 128 ++ src/mainboard/supermicro/h8scm/Makefile.inc | 45 + src/mainboard/supermicro/h8scm/OptionsIds.h | 67 + src/mainboard/supermicro/h8scm/acpi/cpstate.asl | 75 + src/mainboard/supermicro/h8scm/acpi/ide.asl | 244 +++ src/mainboard/supermicro/h8scm/acpi/routing.asl | 242 +++ src/mainboard/supermicro/h8scm/acpi/sata.asl | 149 ++ src/mainboard/supermicro/h8scm/acpi/usb.asl | 161 ++ src/mainboard/supermicro/h8scm/acpi_tables.c | 319 ++++ src/mainboard/supermicro/h8scm/agesawrapper.c | 1194 +++++++++++++++ src/mainboard/supermicro/h8scm/agesawrapper.h | 87 ++ src/mainboard/supermicro/h8scm/buildOpts.c | 616 ++++++++ src/mainboard/supermicro/h8scm/chip.h | 23 + src/mainboard/supermicro/h8scm/cmos.layout | 118 ++ src/mainboard/supermicro/h8scm/devicetree.cb | 128 ++ src/mainboard/supermicro/h8scm/dimmSpd.c | 229 +++ src/mainboard/supermicro/h8scm/dsdt.asl | 1804 +++++++++++++++++++++++ src/mainboard/supermicro/h8scm/fadt.c | 174 +++ src/mainboard/supermicro/h8scm/get_bus_conf.c | 144 ++ src/mainboard/supermicro/h8scm/irq_tables.c | 122 ++ src/mainboard/supermicro/h8scm/mainboard.c | 85 ++ src/mainboard/supermicro/h8scm/mptable.c | 196 +++ src/mainboard/supermicro/h8scm/platform_cfg.h | 54 + src/mainboard/supermicro/h8scm/platform_oem.c | 50 + src/mainboard/supermicro/h8scm/rd890_cfg.c | 274 ++++ src/mainboard/supermicro/h8scm/rd890_cfg.h | 174 +++ src/mainboard/supermicro/h8scm/reset.c | 66 + src/mainboard/supermicro/h8scm/romstage.c | 148 ++ src/mainboard/supermicro/h8scm/sb700_cfg.c | 142 ++ src/mainboard/supermicro/h8scm/sb700_cfg.h | 237 +++ 33 files changed, 8092 insertions(+) diff --git a/src/mainboard/supermicro/Kconfig b/src/mainboard/supermicro/Kconfig index 1fe9b1b..ef4d3bc 100644 --- a/src/mainboard/supermicro/Kconfig +++ b/src/mainboard/supermicro/Kconfig @@ -13,6 +13,8 @@ config BOARD_SUPERMICRO_H8QME_FAM10 bool "H8QME-2+ (Fam10)" config BOARD_SUPERMICRO_H8SCM_FAM10 bool "H8SCM (Fam10)" +config BOARD_SUPERMICRO_H8SCM + bool "H8SCM" config BOARD_SUPERMICRO_H8QGI bool "H8QGI" config BOARD_SUPERMICRO_X6DAI_G @@ -35,6 +37,7 @@ source "src/mainboard/supermicro/h8dmr/Kconfig" source "src/mainboard/supermicro/h8dmr_fam10/Kconfig" source "src/mainboard/supermicro/h8qme_fam10/Kconfig" source "src/mainboard/supermicro/h8scm_fam10/Kconfig" +source "src/mainboard/supermicro/h8scm/Kconfig" source "src/mainboard/supermicro/h8qgi/Kconfig" source "src/mainboard/supermicro/x6dai_g/Kconfig" source "src/mainboard/supermicro/x6dhe_g2/Kconfig" diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c new file mode 100644 index 0000000..b7f0124 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -0,0 +1,516 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "agesawrapper.h" +#include "amdlib.h" +#include "BiosCallOuts.h" +#include "Ids.h" +#include "OptionsIds.h" +#include "heapManager.h" + +STATIC BIOS_CALLOUT_STRUCT BiosCallouts[REQUIRED_CALLOUTS] = +{ + { + AGESA_ALLOCATE_BUFFER, + BiosAllocateBuffer + }, + + { + AGESA_DEALLOCATE_BUFFER, + BiosDeallocateBuffer + }, + + { + AGESA_DO_RESET, + BiosReset + }, + + { + AGESA_LOCATE_BUFFER, + BiosLocateBuffer + }, + + { + AGESA_READ_SPD, + BiosReadSpd + }, + + { + AGESA_READ_SPD_RECOVERY, + BiosDefaultRet + }, + + { + AGESA_RUNFUNC_ONAP, + BiosRunFuncOnAp + }, + + { + AGESA_GET_IDS_INIT_DATA, + BiosGetIdsInitData + }, + + { + AGESA_HOOKBEFORE_DQS_TRAINING, + BiosHookBeforeDQSTraining + }, + + { + AGESA_HOOKBEFORE_DRAM_INIT, + BiosHookBeforeDramInit + }, + { + AGESA_HOOKBEFORE_EXIT_SELF_REF, + BiosHookBeforeExitSelfRefresh + }, +}; + +extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); + +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + AGESA_STATUS CalloutStatus; + + for (i = 0; i < REQUIRED_CALLOUTS; i++) { + if (BiosCallouts[i].CalloutName == Func) { + break; + } + } + + if(i >= REQUIRED_CALLOUTS) { + return AGESA_UNSUPPORTED; + } + + CalloutStatus = BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); + + return CalloutStatus; +} + + +CONST IDS_NV_ITEM IdsData[] = +{ + /*{ + AGESA_IDS_NV_MAIN_PLL_CON, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID_EN, + 0x1 + }, + { + AGESA_IDS_NV_MAIN_PLL_FID, + 0x8 + }, + + { + AGESA_IDS_NV_CUSTOM_NB_PSTATE, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P0_DIV_CTRL, + }, + { + AGESA_IDS_NV_CUSTOM_NB_P1_DIV_CTRL, + }, + { + AGESA_IDS_NV_FORCE_NB_PSTATE, + }, + */ + { + 0xFFFF, + 0xFFFF + } +}; + +#define NUM_IDS_ENTRIES (sizeof (IdsData) / sizeof (IDS_NV_ITEM)) + +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINTN i; + IDS_NV_ITEM *IdsPtr; + + IdsPtr = ((IDS_CALLOUT_STRUCT *) ConfigPtr)->IdsNvPtr; + + if (Data == IDS_CALLOUT_INIT) { + for (i = 0; i < NUM_IDS_ENTRIES; i++) { + IdsPtr[i].IdsNvValue = IdsData[i].IdsNvValue; + IdsPtr[i].IdsNvId = IdsData[i].IdsNvId; + } + } + return AGESA_SUCCESS; +} + + +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AvailableHeapSize; + UINT8 *BiosHeapBaseAddr; + UINT32 CurrNodeOffset; + UINT32 PrevNodeOffset; + UINT32 FreedNodeOffset; + UINT32 BestFitNodeOffset; + UINT32 BestFitPrevNodeOffset; + UINT32 NextFreeOffset; + BIOS_BUFFER_NODE *CurrNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *BestFitNodePtr; + BIOS_BUFFER_NODE *BestFitPrevNodePtr; + BIOS_BUFFER_NODE *NextFreePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); + AllocParams->BufferPointer = NULL; + + AvailableHeapSize = BIOS_HEAP_SIZE - sizeof (BIOS_HEAP_MANAGER); + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + if (BiosHeapBasePtr->StartOfAllocatedNodes == 0) { + /* First allocation */ + CurrNodeOffset = sizeof (BIOS_HEAP_MANAGER); + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + CurrNodePtr->BufferHandle = AllocParams->BufferHandle; + CurrNodePtr->BufferSize = AllocParams->BufferLength; + CurrNodePtr->NextNodeOffset = 0; + AllocParams->BufferPointer = (UINT8 *) CurrNodePtr + sizeof (BIOS_BUFFER_NODE); + + /* Update the remaining free space */ + FreedNodeOffset = CurrNodeOffset + CurrNodePtr->BufferSize + sizeof (BIOS_BUFFER_NODE); + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + FreedNodePtr->BufferSize = AvailableHeapSize - sizeof (BIOS_BUFFER_NODE) - CurrNodePtr->BufferSize; + FreedNodePtr->NextNodeOffset = 0; + + /* Update the offsets for Allocated and Freed nodes */ + BiosHeapBasePtr->StartOfAllocatedNodes = CurrNodeOffset; + BiosHeapBasePtr->StartOfFreedNodes = FreedNodeOffset; + } else { + /* Find out whether BufferHandle has been allocated on the heap. */ + /* If it has, return AGESA_BOUNDS_CHK */ + CurrNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + + while (CurrNodeOffset != 0) { + CurrNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + CurrNodeOffset); + if (CurrNodePtr->BufferHandle == AllocParams->BufferHandle) { + return AGESA_BOUNDS_CHK; + } + CurrNodeOffset = CurrNodePtr->NextNodeOffset; + /* If BufferHandle has not been allocated on the heap, CurrNodePtr here points + to the end of the allocated nodes list. + */ + + } + /* Find the node that best fits the requested buffer size */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + PrevNodeOffset = FreedNodeOffset; + BestFitNodeOffset = 0; + BestFitPrevNodeOffset = 0; + while (FreedNodeOffset != 0) { + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + if (FreedNodePtr->BufferSize >= (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + if (BestFitNodeOffset == 0) { + /* First node that fits the requested buffer size */ + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } else { + /* Find out whether current node is a better fit than the previous nodes */ + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + if (BestFitNodePtr->BufferSize > FreedNodePtr->BufferSize) { + BestFitNodeOffset = FreedNodeOffset; + BestFitPrevNodeOffset = PrevNodeOffset; + } + } + } + PrevNodeOffset = FreedNodeOffset; + FreedNodeOffset = FreedNodePtr->NextNodeOffset; + } /* end of while loop */ + + + if (BestFitNodeOffset == 0) { + /* If we could not find a node that fits the requested buffer */ + /* size, return AGESA_BOUNDS_CHK */ + return AGESA_BOUNDS_CHK; + } else { + BestFitNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitNodeOffset); + BestFitPrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + BestFitPrevNodeOffset); + + /* If BestFitNode is larger than the requested buffer, fragment the node further */ + if (BestFitNodePtr->BufferSize > (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE))) { + NextFreeOffset = BestFitNodeOffset + AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE); + + NextFreePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextFreeOffset); + NextFreePtr->BufferSize = BestFitNodePtr->BufferSize - (AllocParams->BufferLength + sizeof (BIOS_BUFFER_NODE)); + NextFreePtr->NextNodeOffset = BestFitNodePtr->NextNodeOffset; + } else { + /* Otherwise, next free node is NextNodeOffset of BestFitNode */ + NextFreeOffset = BestFitNodePtr->NextNodeOffset; + } + + /* If BestFitNode is the first buffer in the list, then update + StartOfFreedNodes to reflect the new free node + */ + if (BestFitNodeOffset == BiosHeapBasePtr->StartOfFreedNodes) { + BiosHeapBasePtr->StartOfFreedNodes = NextFreeOffset; + } else { + BestFitPrevNodePtr->NextNodeOffset = NextFreeOffset; + } + + /* Add BestFitNode to the list of Allocated nodes */ + CurrNodePtr->NextNodeOffset = BestFitNodeOffset; + BestFitNodePtr->BufferSize = AllocParams->BufferLength; + BestFitNodePtr->BufferHandle = AllocParams->BufferHandle; + BestFitNodePtr->NextNodeOffset = 0; + + /* Remove BestFitNode from list of Freed nodes */ + AllocParams->BufferPointer = (UINT8 *) BestFitNodePtr + sizeof (BIOS_BUFFER_NODE); + } + } + + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + + UINT8 *BiosHeapBaseAddr; + UINT32 AllocNodeOffset; + UINT32 PrevNodeOffset; + UINT32 NextNodeOffset; + UINT32 FreedNodeOffset; + UINT32 EndNodeOffset; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_BUFFER_NODE *PrevNodePtr; + BIOS_BUFFER_NODE *FreedNodePtr; + BIOS_BUFFER_NODE *NextNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + /* Find target node to deallocate in list of allocated nodes. + Return AGESA_BOUNDS_CHK if the BufferHandle is not found + */ + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + PrevNodeOffset = AllocNodeOffset; + + while (AllocNodePtr->BufferHandle != AllocParams->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + return AGESA_BOUNDS_CHK; + } + PrevNodeOffset = AllocNodeOffset; + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + + /* Remove target node from list of allocated nodes */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + + /* Zero out the buffer, and clear the BufferHandle */ + LibAmdMemFill ((UINT8 *)AllocNodePtr + sizeof (BIOS_BUFFER_NODE), 0, AllocNodePtr->BufferSize, &(AllocParams->StdHeader)); + AllocNodePtr->BufferHandle = 0; + AllocNodePtr->BufferSize += sizeof (BIOS_BUFFER_NODE); + + /* Add deallocated node in order to the list of freed nodes */ + FreedNodeOffset = BiosHeapBasePtr->StartOfFreedNodes; + FreedNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + FreedNodeOffset); + + EndNodeOffset = AllocNodeOffset + AllocNodePtr->BufferSize; + + if (AllocNodeOffset < FreedNodeOffset) { + /* Add to the start of the freed list */ + if (EndNodeOffset == FreedNodeOffset) { + /* If the freed node is adjacent to the first node in the list, concatenate both nodes */ + AllocNodePtr->BufferSize += FreedNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; + + /* Clear the BufferSize and NextNodeOffset of the previous first node */ + FreedNodePtr->BufferSize = 0; + FreedNodePtr->NextNodeOffset = 0; + + } else { + /* Otherwise, add freed node to the start of the list + Update NextNodeOffset and BufferSize to include the + size of BIOS_BUFFER_NODE + */ + AllocNodePtr->NextNodeOffset = FreedNodeOffset; + } + /* Update StartOfFreedNodes to the new first node */ + BiosHeapBasePtr->StartOfFreedNodes = AllocNodeOffset; + } else { + /* Traverse list of freed nodes to find where the deallocated node + should be place + */ + NextNodeOffset = FreedNodeOffset; + NextNodePtr = FreedNodePtr; + while (AllocNodeOffset > NextNodeOffset) { + PrevNodeOffset = NextNodeOffset; + if (NextNodePtr->NextNodeOffset == 0) { + break; + } + NextNodeOffset = NextNodePtr->NextNodeOffset; + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + } + + /* If deallocated node is adjacent to the next node, + concatenate both nodes + */ + if (NextNodeOffset == EndNodeOffset) { + NextNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + NextNodeOffset); + AllocNodePtr->BufferSize += NextNodePtr->BufferSize; + AllocNodePtr->NextNodeOffset = NextNodePtr->NextNodeOffset; + + NextNodePtr->BufferSize = 0; + NextNodePtr->NextNodeOffset = 0; + } else { + /*AllocNodePtr->NextNodeOffset = FreedNodePtr->NextNodeOffset; */ + AllocNodePtr->NextNodeOffset = NextNodeOffset; + } + /* If deallocated node is adjacent to the previous node, + concatenate both nodes + */ + PrevNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + PrevNodeOffset); + EndNodeOffset = PrevNodeOffset + PrevNodePtr->BufferSize; + if (AllocNodeOffset == EndNodeOffset) { + PrevNodePtr->NextNodeOffset = AllocNodePtr->NextNodeOffset; + PrevNodePtr->BufferSize += AllocNodePtr->BufferSize; + + AllocNodePtr->BufferSize = 0; + AllocNodePtr->NextNodeOffset = 0; + } else { + PrevNodePtr->NextNodeOffset = AllocNodeOffset; + } + } + return AGESA_SUCCESS; +} + +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + UINT32 AllocNodeOffset; + UINT8 *BiosHeapBaseAddr; + BIOS_BUFFER_NODE *AllocNodePtr; + BIOS_HEAP_MANAGER *BiosHeapBasePtr; + AGESA_BUFFER_PARAMS *AllocParams; + + AllocParams = (AGESA_BUFFER_PARAMS *) ConfigPtr; + + BiosHeapBaseAddr = (UINT8 *) BIOS_HEAP_START_ADDRESS; + BiosHeapBasePtr = (BIOS_HEAP_MANAGER *) BIOS_HEAP_START_ADDRESS; + + AllocNodeOffset = BiosHeapBasePtr->StartOfAllocatedNodes; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + + while (AllocParams->BufferHandle != AllocNodePtr->BufferHandle) { + if (AllocNodePtr->NextNodeOffset == 0) { + AllocParams->BufferPointer = NULL; + AllocParams->BufferLength = 0; + return AGESA_BOUNDS_CHK; + } else { + AllocNodeOffset = AllocNodePtr->NextNodeOffset; + AllocNodePtr = (BIOS_BUFFER_NODE *) (BiosHeapBaseAddr + AllocNodeOffset); + } + } + + AllocParams->BufferPointer = (UINT8 *) ((UINT8 *) AllocNodePtr + sizeof (BIOS_BUFFER_NODE)); + AllocParams->BufferLength = AllocNodePtr->BufferSize; + + return AGESA_SUCCESS; + +} + +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Data, ConfigPtr); + return Status; +} + +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + UINT8 Value; + UINTN ResetType; + AMD_CONFIG_PARAMS *StdHeader; + + ResetType = Data; + StdHeader = ConfigPtr; + + // + // Perform the RESET based upon the ResetType. In case of + // WARM_RESET_WHENVER and COLD_RESET_WHENEVER, the request will go to + // AmdResetManager. During the critical condition, where reset is required + // immediately, the reset will be invoked directly by writing 0x04 to port + // 0xCF9 (Reset Port). + // + switch (ResetType) { + case WARM_RESET_WHENEVER: + case COLD_RESET_WHENEVER: + break; + + case WARM_RESET_IMMEDIATELY: + case COLD_RESET_IMMEDIATELY: + Value = 0x06; + LibAmdIoWrite (AccessWidth8, 0xCf9, &Value, StdHeader); + break; + + default: + break; + } + + Status = 0; + return Status; +} + +AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); + + return Status; +} + +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_UNSUPPORTED; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + return AGESA_SUCCESS; +} + diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.h b/src/mainboard/supermicro/h8scm/BiosCallOuts.h new file mode 100644 index 0000000..24a05fb --- /dev/null +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.h @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BIOS_CALLOUT_H_ +#define _BIOS_CALLOUT_H_ + +#include "Porting.h" +#include "AGESA.h" + +#define REQUIRED_CALLOUTS 12 +#define BIOS_HEAP_START_ADDRESS 0x00010000 +#define BIOS_HEAP_SIZE 0x20000 /* 64MB */ + +typedef struct _BIOS_HEAP_MANAGER { + //UINT32 AvailableSize; + UINT32 StartOfAllocatedNodes; + UINT32 StartOfFreedNodes; +} BIOS_HEAP_MANAGER; + +typedef struct _BIOS_BUFFER_NODE { + UINT32 BufferHandle; + UINT32 BufferSize; + UINT32 NextNodeOffset; +} BIOS_BUFFER_NODE; + +/* + * CALLOUTS + */ +AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* REQUIRED CALLOUTS + * AGESA ADVANCED CALLOUTS - CPU + */ +AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS BiosGetIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* AGESA ADVANCED CALLOUTS - MEMORY */ +AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + +/* BIOS DEFAULT RET */ +AGESA_STATUS BiosDefaultRet (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDQSTraining (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +/* Call the host environment interface to provide a user hook opportunity. */ +AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG09 9 +#define SB_GPIO_REG10 10 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG17 17 +#define SB_GPIO_REG21 21 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG28 28 +#endif //_BIOS_CALLOUT_H_ + diff --git a/src/mainboard/supermicro/h8scm/Kconfig b/src/mainboard/supermicro/h8scm/Kconfig new file mode 100644 index 0000000..289ab16 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/Kconfig @@ -0,0 +1,128 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +if BOARD_SUPERMICRO_H8SCM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_AMD_AGESA_FAMILY15 + select CPU_AMD_SOCKET_C32 + select NORTHBRIDGE_AMD_AGESA_FAMILY15_ROOT_COMPLEX + select NORTHBRIDGE_AMD_AGESA_FAMILY15 + select NORTHBRIDGE_AMD_CIMX_RD890 + select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_WINBOND_W83627DHG + select SUPERIO_NUVOTON_WPCM450 + select DRIVERS_I2C_W83795 + select UDELAY_TSC + select BOARD_HAS_FADT + select HAVE_BUS_CONFIG + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_HARD_RESET + select SERIAL_CPU_INIT + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_4096 + select TINY_BOOTBLOCK + #select MMCONF_SUPPORT_DEFAULT #TODO enable it to resolve Multicore IO conflict + +config MAINBOARD_DIR + string + default supermicro/h8scm + +config MAINBOARD_PART_NUMBER + string + default "H8SCM" + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 64 + +config MAX_PHYSICAL_CPUS + int + default 16 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + +config MEM_TRAIN_SEQ + int + default 2 + +config IRQ_SLOT_COUNT + int + default 11 + +config RAMTOP + hex + default 0x1000000 + +config HEAP_SIZE + hex + default 0xc0000 + +config STACK_SIZE + hex + default 0x10000 + +config ACPI_SSDTX_NUM + int + default 0 + +config RAMBASE + hex + default 0x200000 + +config SIO_PORT + hex + default 0x164E + help + though UARTs are on the NUVOTON BMC, port 0x164E + PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E + +config DRIVERS_PS2_KEYBOARD + bool + default y + +config WARNINGS_ARE_ERRORS + bool + default n + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS + bool + default n + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "102b,0532" + +endif # BOARD_SUPERMICRO_H8SCM_FAM15 + diff --git a/src/mainboard/supermicro/h8scm/Makefile.inc b/src/mainboard/supermicro/h8scm/Makefile.inc new file mode 100644 index 0000000..d49289b --- /dev/null +++ b/src/mainboard/supermicro/h8scm/Makefile.inc @@ -0,0 +1,45 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +romstage-y += buildOpts.c +romstage-y += agesawrapper.c +romstage-y += dimmSpd.c +romstage-y += BiosCallOuts.c +romstage-y += platform_oem.c + +ramstage-$(CONFIG_NORTHBRIDGE_AMD_CIMX_RD890) += rd890_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700_cfg.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += reset.c +ramstage-y += buildOpts.c +ramstage-y += agesawrapper.c +ramstage-y += dimmSpd.c +ramstage-y += BiosCallOuts.c +ramstage-y += platform_oem.c + +AGESA_PREFIX ?= $(src)/vendorcode/amd/agesa +CIMX_PREFIX ?= $(src)/vendorcode/amd/cimx +AGESA_ROOT ?= $(AGESA_PREFIX)/f15 +NB_CIMX_ROOT ?= $(CIMX_PREFIX)/rd890 +SB_CIMX_ROOT ?= $(CIMX_PREFIX)/sb700 + +subdirs-y += ../../../../$(AGESA_ROOT) + diff --git a/src/mainboard/supermicro/h8scm/OptionsIds.h b/src/mainboard/supermicro/h8scm/OptionsIds.h new file mode 100644 index 0000000..dd9281e --- /dev/null +++ b/src/mainboard/supermicro/h8scm/OptionsIds.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/** + * @file + * + * IDS Option File + * + * This file is used to switch on/off IDS features. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: Core + * @e \$Revision: 12067 $ @e \$Date: 2009-04-11 04:34:13 +0800 (Sat, 11 Apr 2009) $ + */ +#ifndef _OPTION_IDS_H_ +#define _OPTION_IDS_H_ + +/** + * + * This file generates the defaults tables for the Integrated Debug Support + * Module. The documented build options are imported from a user controlled + * file for processing. The build options for the Integrated Debug Support + * Module are listed below: + * + * IDSOPT_IDS_ENABLED + * IDSOPT_ERROR_TRAP_ENABLED + * IDSOPT_CONTROL_ENABLED + * IDSOPT_TRACING_ENABLED + * IDSOPT_PERF_ANALYSIS + * IDSOPT_ASSERT_ENABLED + * IDS_DEBUG_PORT + * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED + * + **/ + +#define IDSOPT_IDS_ENABLED TRUE +//#define IDSOPT_CONTROL_ENABLED TRUE +#define IDSOPT_TRACING_ENABLED TRUE +//#define IDSOPT_PERF_ANALYSIS TRUE +#define IDSOPT_ASSERT_ENABLED TRUE +//#define CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL TRUE +//#undef IDSOPT_DEBUG_ENABLED +//#define IDSOPT_DEBUG_ENABLED FALSE +//#undef IDSOPT_HOST_SIMNOW +//#define IDSOPT_HOST_SIMNOW FALSE +//#undef IDSOPT_HOST_HDT +//#define IDSOPT_HOST_HDT FALSE +//#define IDS_DEBUG_PORT 0x80 + +#endif diff --git a/src/mainboard/supermicro/h8scm/acpi/cpstate.asl b/src/mainboard/supermicro/h8scm/acpi/cpstate.asl new file mode 100644 index 0000000..5eca9cc --- /dev/null +++ b/src/mainboard/supermicro/h8scm/acpi/cpstate.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package () + { + 0x00000AF0, + 0x0000BF81, + 0x00000002, + 0x00000002, + 0x00000000, + 0x00000000 + }, + + Package () + { + 0x00000578, + 0x000076F2, + 0x00000002, + 0x00000002, + 0x00000001, + 0x00000001 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/supermicro/h8scm/acpi/ide.asl b/src/mainboard/supermicro/h8scm/acpi/ide.asl new file mode 100644 index 0000000..c79c18c --- /dev/null +++ b/src/mainboard/supermicro/h8scm/acpi/ide.asl @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} diff --git a/src/mainboard/supermicro/h8scm/acpi/routing.asl b/src/mainboard/supermicro/h8scm/acpi/routing.asl new file mode 100644 index 0000000..6264f38 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/acpi/routing.asl @@ -0,0 +1,242 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - SR5650 HT */ + Package() { 0xFFFF, Zero, INTA, Zero }, + + /* Bus 0, Dev 1 - CLKCONFIG */ + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package() {0x0002FFFF, 0, INTE, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package() {0x0003FFFF, 0, INTE, 0 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package() {0x0004FFFF, 0, INTE, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package() {0x0005FFFF, 0, INTE, 0 }, + + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package() {0x0006FFFF, 0, INTF, 0 }, + + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package() {0x0007FFFF, 0, INTF, 0 }, + + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 9 - PCIe Bridge */ + Package() {0x0009FFFF, 0, INTF, 0 }, + + /* Bus 0, Dev a - PCIe Bridge */ + Package() {0x000AFFFF, 0, INTG, 0 }, + + /* Bus 0, Dev b - PCIe Bridge */ + Package() {0x000BFFFF, 0, INTG, 0 }, + + /* Bus 0, Dev c - PCIe Bridge */ + Package() {0x000CFFFF, 0, INTG, 0 }, + + /* Bus 0, Dev d - PCIe Bridge for Intel 82576 Giga NIC*/ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller */ + Package() {0x0011FFFF, 0, INTG, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package() {0x0012FFFF, 0, INTA, 0 }, + Package() {0x0012FFFF, 1, INTB, 0 }, + Package() {0x0012FFFF, 2, INTC, 0 }, + Package() {0x0012FFFF, 3, INTD, 0 }, + + Package() {0x0013FFFF, 0, INTC, 0 }, + Package() {0x0013FFFF, 1, INTD, 0 }, + Package() {0x0013FFFF, 2, INTA, 0 }, + Package() {0x0013FFFF, 2, INTB, 0 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - SR5650 HT */ + Package() { 0xFFFF, Zero, Zero, 0x37 }, + + /* Bus 0, Dev 1 - CLKCONFIG */ + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot (GFX0) */ + Package() {0x0002FFFF, 0, 0, 0x34 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package() {0x0003FFFF, 0, 0, 0x34 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package() {0x0004FFFF, 0, 0, 0x34 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + Package() {0x0005FFFF, 0, 0, 0x34 }, + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + Package() {0x0006FFFF, 0, 0, 0x35 }, + + /* Bus 0, Dev 7 - PCIe Bridge */ + Package() {0x0007FFFF, 0, 0, 0x35 }, + + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 9 - PCIe Bridge */ + Package() {0x0009FFFF, 0, 0, 0x35 }, + + /* Bus 0, Dev A - PCIe Bridge */ + Package() {0x000AFFFF, 0, 0, 0x36 }, + + /* Bus 0, Dev B - PCIe Bridge */ + Package() {0x000BFFFF, 0, 0, 0x36 }, + + /* Bus 0, Dev C - PCIe Bridge */ + Package() {0x000CFFFF, 0, 0, 0x36 }, + + /* Bus 0, Dev D - PCIe Bridge For Intel 82576 Giga NIC*/ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller */ + Package() {0x0011FFFF, 0, 0, 0x16 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package( ){0x0012FFFF, 0, 0, 16 }, + Package() {0x0012FFFF, 1, 0, 17 }, + Package() {0x0012FFFF, 2, 0, 18 }, + Package() {0x0012FFFF, 3, 0, 19 }, + + Package() {0x0013FFFF, 0, 0, 18 }, + Package() {0x0013FFFF, 1, 0, 19 }, + Package() {0x0013FFFF, 2, 0, 16 }, + Package() {0x0013FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package() {0x0014FFFF, 0, 0, 16 }, + Package() {0x0014FFFF, 1, 0, 17 }, + Package() {0x0014FFFF, 2, 0, 18 }, + Package() {0x0014FFFF, 3, 0, 19 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 4 */ + Package() {0x0000FFFF, 0, INTC, 0 }, + Package() {0x0000FFFF, 1, INTD, 0 }, + Package() {0x0000FFFF, 2, INTA, 0 }, + Package() {0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 0x18 }, + Package(){0x0000FFFF, 1, 0, 0x19 }, + Package(){0x0000FFFF, 2, 0, 0x1A }, + Package(){0x0000FFFF, 3, 0, 0x1B }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 0x2C }, + Package(){0x0000FFFF, 1, 0, 0x2D }, + Package(){0x0000FFFF, 2, 0, 0x2E }, + Package(){0x0000FFFF, 3, 0, 0x2F }, + }) + + Name(PSb, Package(){ + /* PCIe slot - Hooked to PCIe slot 11 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APSb, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 0x20 }, + Package(){0x0000FFFF, 1, 0, 0x21 }, + Package(){0x0000FFFF, 2, 0, 0x22 }, + Package(){0x0000FFFF, 3, 0, 0x23 }, + }) + + Name(PSc, Package(){ + /* PCIe slot - Hooked to PCIe slot 12 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APSc, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 0x24 }, + Package(){0x0000FFFF, 1, 0, 0x25 }, + Package(){0x0000FFFF, 2, 0, 0x26 }, + Package(){0x0000FFFF, 3, 0, 0x27 }, + }) + + Name(PSd, Package(){ + /* PCIe slot - Hooked to PCIe slot 13 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APSd, Package(){ + /* PCIe slot - Hooked to PCIe */ + Package(){0x0000FFFF, 0, 0, 0x28 }, + Package(){0x0000FFFF, 1, 0, 0x29 }, + Package(){0x0000FFFF, 2, 0, 0x2A }, + Package(){0x0000FFFF, 3, 0, 0x2B }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ + Package(){0x0004FFFF, 0, 0, 0x14 }, + Package(){0x0003FFFF, 0, 0, 0x15 }, + Package(){0x0003FFFF, 1, 0, 0x16 }, + Package(){0x0003FFFF, 2, 0, 0x17 }, + Package(){0x0003FFFF, 3, 0, 0x14 }, + }) +} diff --git a/src/mainboard/supermicro/h8scm/acpi/sata.asl b/src/mainboard/supermicro/h8scm/acpi/sata.asl new file mode 100644 index 0000000..bd4acf0 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/acpi/sata.asl @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00110000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} diff --git a/src/mainboard/supermicro/h8scm/acpi/usb.asl b/src/mainboard/supermicro/h8scm/acpi/usb.asl new file mode 100644 index 0000000..81ea9a2 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/acpi/usb.asl @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} diff --git a/src/mainboard/supermicro/h8scm/acpi_tables.c b/src/mainboard/supermicro/h8scm/acpi_tables.c new file mode 100644 index 0000000..6f10a00 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/acpi_tables.c @@ -0,0 +1,319 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/io.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdfam10_sysconf.h> +#include "agesawrapper.h" + +#define DUMP_ACPI_TABLES 0 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const unsigned char AmlCode[]; + + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + device_t dev; + u32 dword; + u32 gsi_base = 0; + u32 apicid_sp5100; + u32 apicid_sr5650; + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sp5100 = 0x0; +#else + apicid_sp5100 = CONFIG_MAX_CPUS + 1 +#endif + apicid_sr5650 = apicid_sp5100 + 1; + + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write sp5100 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_sp5100, + IO_APIC_ADDR, + 0 + ); + + /* IOAPIC on rs5690 */ + gsi_base += IO_APIC_INTERRUPTS; /* SP5100 has 24 IOAPIC entries. */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + apicid_sr5650, + dword, + gsi_base + ); + } + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, + 0, //BUS + 0, //SOURCE + 2, //gsirq + 0 //flags + ); + + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + int lens; + msr_t msr; + char pscope[] = "\\_SB.PCI0"; + + lens = acpigen_write_scope(pscope); + msr = rdmsr(TOP_MEM); + lens += acpigen_write_name_dword("TOM1", msr.lo); + msr = rdmsr(TOP_MEM2); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); + acpigen_patch_len(lens - 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + //acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_srat_t *srat; + acpi_slit_t *slit; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; + acpi_header_t *ssdt2; + acpi_header_t *alib; + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *)current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ +#ifdef UNUSED_CODE // Don't need HPET table. we have one in dsdt + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * HPET at %lx\n", current); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); +#endif + + /* If we want to use HPET Timers Linux wants an MADT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * MADT at %lx\n",current); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SRAT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); + srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); + if (srat != NULL) { + memcpy((void *)current, srat, srat->header.length); + srat = (acpi_srat_t *) current; + //acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + } + + /* SLIT */ + current = ( current + 0x07) & -0x08; + printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); + slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); + if (slit != NULL) { + memcpy((void *)current, slit, slit->header.length); + slit = (acpi_slit_t *) current; + //acpi_create_slit(slit); + current += slit->header.length; + acpi_add_table(rsdp, slit); + } + + /* SSDT */ + current = (current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); + alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + if (alib != NULL) { + memcpy((void *)current, alib, alib->length); + ssdt = (acpi_header_t *) current; + current += alib->length; + acpi_add_table(rsdp,alib); + } else { + printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); + } + + /* The DSDT needs additional work for the AGESA SSDT Pstate table */ + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * AGESA SSDT Pstate at %lx\n", current); + ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); + if (ssdt != NULL) { + memcpy((void *)current, ssdt, ssdt->length); + ssdt = (acpi_header_t *) current; + current += ssdt->length; + } else { + printk(BIOS_DEBUG, " AGESA SSDT table NULL. Skipping.\n"); + } + acpi_add_table(rsdp,ssdt); + + current = ( current + 0x0f) & -0x10; + printk(BIOS_DEBUG, "ACPI: * coreboot TOM SSDT2 at %lx\n", current); + ssdt2 = (acpi_header_t *) current; + acpi_create_ssdt_generator(ssdt2, ACPI_TABLE_CREATOR); + current += ssdt2->length; + acpi_add_table(rsdp,ssdt2); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "srat\n"); + dump_mem(srat, ((void *)srat) + srat->header.length); + + printk(BIOS_DEBUG, "slit\n"); + dump_mem(slit, ((void *)slit) + slit->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c new file mode 100644 index 0000000..aeeab11 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -0,0 +1,1194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include <stdint.h> +#include <string.h> +#include "agesawrapper.h" +#include "BiosCallOuts.h" +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include <cpuFamilyTranslation.h> /* CPU_SPECIFIC_SERVICES */ + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); + +static UINT32 agesawrapper_amdinitcpuio(VOID) +{ + AGESA_STATUS Status; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + UINT32 nodes; + UINT32 node; + UINT32 sblink; + UINT32 i; + UINT32 TOM; + + /* get the number of coherent nodes in the system */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + nodes = ((PciData >> 4) & 7) + 1; //NodeCnt[2:0] + + /* Find out the Link ID of Node0 that connects to the + * Southbridge (system IO hub). e.g. family10 MCM Processor, + * sbLink is Processor0 Link2, internal Node0 Link3 + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibAmdPciRead(AccessWidth32, PciAddress, &PciData, &StdHeader); + sblink = (PciData >> 8) & 3; //assume ganged + + /* Enable MMIO on AMD CPU Address Map Controller for all nodes */ + for (node = 0; node < nodes; node++) { + /* clear all MMIO Mapped Base/Limit Registers */ + for (i = 0; i < 8; i++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80 + i*8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84 + i*8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* clear all IO Space Base/Limit Registers */ + for (i = 0; i < 4; i++) { + PciData = 0x00000000; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4 + i*8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0 + i*8); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + /* Set VGA Ram MMIO 0000A0000-0000BFFFF to Node0 sbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x84); + PciData = 0x00000B00; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x80); + PciData = 0x00000A03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set TOM1-FFFFFFFF to Node0 sbLink. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x8C); + PciData = 0x00FFFF00; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + TOM = (UINT32)MsrRead(TOP_MEM); + PciData = (TOM >> 8) | 0x03; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0x88); + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Set MMCONF space to Node0 sbLink with NP set. + * default E0000000-EFFFFFFF + * Just have all mmio set to non-posted, + * coreboot not implemente the range by range setting yet. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC); + PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus + PciData = (PciData >> 8) & 0xFFFFFF00; + PciData |= 0x80; //NP + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xB8); + PciData = (PCIE_BASE_ADDRESS >> 8) | 0x03; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + + /* Set PCIO: 0x0 - 0xFFF000 to Node0 sbLink and enabled VGA IO*/ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC4); + PciData = 0x00FFF000; + PciData |= sblink << 4; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xC0); + PciData = 0x00000033; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + } + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 agesawrapper_amdinitmmio(VOID) +{ + AGESA_STATUS Status; + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + * Set the MMIO Configuration Base Address and Bus Range onto + * MMIO configuration base Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + * Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | (1ULL << 46); + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000 - CONFIG_ROM_SIZE) | 5; + LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + MsrReg = (0x1000000000 - CONFIG_ROM_SIZE) | 0x800; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + Status = AGESA_SUCCESS; + return (UINT32)Status; +} + +UINT32 agesawrapper_amdinitreset(VOID) +{ + AGESA_STATUS status = AGESA_SUCCESS; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof(AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, + 0, + sizeof(AMD_RESET_PARAMS), + &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = NULL; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + AmdResetParams.HtConfig.Depth = 0; + + //MARG34PI disabled AGESA_ENTRY_INIT_RESET by default + //but we need to call AmdCreateStruct to call HeapManagerInit, or the event log not work +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) + status = AmdInitReset((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); +#endif + if (status != AGESA_SUCCESS) + agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 agesawrapper_amdinitearly(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + UINT32 TscRateInMhz; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof(AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly(AmdEarlyParamsPtr); + if (status != AGESA_SUCCESS) + agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + + GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); + FamilySpecificServices->GetTscRate(FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); + printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); + + AmdReleaseStruct(&AmdParamStruct); + return (UINT32)status; +} + +UINT32 agesawrapper_amdinitpost(VOID) +{ + AGESA_STATUS status; + UINT16 i; + UINT32 *HeadPtr; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + BIOS_HEAP_MANAGER *BiosManagerPtr; + UINT32 TscRateInMhz; + CPU_SPECIFIC_SERVICES *FamilySpecificServices; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof(AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + if (status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(PostParams->StdHeader.HeapStatus); + } + AmdReleaseStruct(&AmdParamStruct); + + /* Initialize heap space */ + BiosManagerPtr = (BIOS_HEAP_MANAGER *)BIOS_HEAP_START_ADDRESS; + + HeadPtr = (UINT32 *) ((UINT8 *) BiosManagerPtr + sizeof(BIOS_HEAP_MANAGER)); + for (i = 0; i < ((BIOS_HEAP_SIZE/4) - (sizeof(BIOS_HEAP_MANAGER)/4)); i++) { + *HeadPtr = 0x00000000; + HeadPtr++; + } + BiosManagerPtr->StartOfAllocatedNodes = 0; + BiosManagerPtr->StartOfFreedNodes = 0; + + GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, &AmdParamStruct.StdHeader); + FamilySpecificServices->GetTscRate (FamilySpecificServices, &TscRateInMhz, &AmdParamStruct.StdHeader); + printk(BIOS_DEBUG, "BSP Frequency: %luMHz\n", TscRateInMhz); + + return (UINT32)status; +} + +UINT32 agesawrapper_amdinitenv(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParams; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof(AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + EnvParams = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; + status = AmdInitEnv(EnvParams); + if (status != AGESA_SUCCESS) + agesawrapper_amdreadeventlog(EnvParams->StdHeader.HeapStatus); + + AmdReleaseStruct(&AmdParamStruct); + return (UINT32)status; +} + +VOID * agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + + case PICK_PSTATE: + return AcpiPstate; + + case PICK_SRAT: + return AcpiSrat; + + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + default: + return NULL; + } + + return NULL; +} + +UINT32 agesawrapper_amdinitmid(VOID) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof(AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + status = AmdCreateStruct(&AmdParamStruct); + if (status != AGESA_SUCCESS) { + return (UINT32)status; + } + status = AmdInitMid((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); + if (status != AGESA_SUCCESS) + agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return (UINT32)status; +} + +UINT32 agesawrapper_amdinitlate(VOID) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParamsPtr; + + LibAmdMemFill(&AmdParamStruct, + 0, + sizeof (AMD_INTERFACE_PARAMS), + &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct (&AmdParamStruct); + AmdLateParamsPtr = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + + printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32)AmdLateParamsPtr); + + Status = AmdInitLate(AmdLateParamsPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParamsPtr->StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + } + DmiTable = AmdLateParamsPtr->DmiTable; + AcpiPstate = AmdLateParamsPtr->AcpiPState; + AcpiSrat = AmdLateParamsPtr->AcpiSrat; + AcpiSlit = AmdLateParamsPtr->AcpiSlit; + AcpiWheaMce = AmdLateParamsPtr->AcpiWheaMce; + AcpiWheaCmc = AmdLateParamsPtr->AcpiWheaCmc; + AcpiAlib = AmdLateParamsPtr->AcpiAlib; + + printk(BIOS_DEBUG, "In %s, AGESA generated ACPI tables:\n" + " DmiTable:%p\n AcpiPstate: %p\n AcpiSrat:%p\n AcpiSlit:%p\n" + " Mce:%p\n Cmc:%p\n Alib:%p\n", + __func__, DmiTable, AcpiPstate, AcpiSrat, AcpiSlit, + AcpiWheaMce, AcpiWheaCmc, AcpiAlib); + + /* Don't release the structure until coreboot has copied the ACPI tables. + * AmdReleaseStruct (&AmdLateParams); + */ + + return (UINT32)Status; +} + +/** + * @param[in] UINTN ApicIdOfCore, + * @param[in] AP_EXE_PARAMS *LaunchApParams + */ +UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + AMD_LATE_PARAMS AmdLateParams; + + LibAmdMemFill(&AmdLateParams, + 0, + sizeof(AMD_LATE_PARAMS), + &(AmdLateParams.StdHeader)); + + AmdLateParams.StdHeader.AltImageBasePtr = 0; + AmdLateParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + AmdLateParams.StdHeader.Func = 0; + AmdLateParams.StdHeader.ImageBasePtr = 0; + AmdLateParams.StdHeader.HeapStatus = HEAP_TEMP_MEM; + + printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t)Data); + Status = AmdLateRunApTask((AP_EXE_PARAMS *)ConfigPtr); + if (Status != AGESA_SUCCESS) { + agesawrapper_amdreadeventlog(AmdLateParams.StdHeader.HeapStatus); + ASSERT(Status <= AGESA_UNSUPPORTED); + } + + return (UINT32)Status; +} + +/** + * + */ +static void agesa_bound_check(EVENT_PARAMS *event) +{ + switch (event->EventInfo) { + case CPU_ERROR_HEAP_IS_FULL: + printk(BIOS_DEBUG, "Heap allocation for specified buffer handle failed as heap is full\n"); + break; + + case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED: + printk(BIOS_DEBUG, "Allocation incomplete as buffer has previously been allocated\n"); + break; + + case CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT: + printk(BIOS_DEBUG, "Unable to locate buffer handle or deallocate heap as buffer handle cannot be located\n"); + break; + + case CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT: + printk(BIOS_DEBUG, "Unable to locate pointer to the heap buffer\n"); + break; + + default: + break; + } +} + +/** + * + */ +static void agesa_alert(EVENT_PARAMS *event) +{ + switch (event->EventInfo) { + case MEM_ALERT_USER_TMG_MODE_OVERRULED: + printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx " + "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case MEM_ALERT_ORG_MISMATCH_DIMM: + printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx " + "DIMM organization miss-match\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case MEM_ALERT_BK_INT_DIS: + printk(BIOS_DEBUG, "Socket %lx Dct %lx Channel %lx " + "Bank interleaving disable for internal issue\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case CPU_EVENT_BIST_ERROR: + printk(BIOS_DEBUG, "BIST error: %lx reported on Socket %lx Core %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_HW_SYNCFLOOD: + printk(BIOS_DEBUG, "HT_EVENT_DATA_HW_SYNCFLOOD error on Socket %lx Link %lx\n", + event->DataParam1, + event->DataParam2); + break; + + case HT_EVENT_HW_HTCRC: + printk(BIOS_DEBUG, "HT_EVENT_HW_HTCRC error on Socket %lx Link %lx Lanemask:%lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + default: + break; + } +} + +/** + * + */ +static void agesa_warning(EVENT_PARAMS *event) +{ +/* + if (event->EventInfo == CPU_EVENT_STACK_REENTRY) { + printk(BIOS_DEBUG, + "The stack has already been enabled and this is a + redundant invocation of AMD_ENABLE_STACK. There is no event logged and + no data values. The event sub-class is returned along with the status code\n"); + return; + } +*/ + + switch (event->EventInfo >> 24) { + case 0x04: + printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case 0x08: + printk(BIOS_DEBUG, "Processor: "); + break; + + case 0x10: + printk(BIOS_DEBUG, "Hyper Transport: "); + break; + + default: + break; + } + + switch (event->EventInfo) { + case MEM_WARNING_UNSUPPORTED_QRDIMM: + printk(BIOS_DEBUG, "QR DIMMs detected but not supported\n"); + break; + + case MEM_WARNING_UNSUPPORTED_UDIMM: + printk(BIOS_DEBUG, "Unbuffered DIMMs detected but not supported\n"); + break; + + case MEM_WARNING_UNSUPPORTED_SODIMM: + printk(BIOS_DEBUG, "SO-DIMMs detected but not supported"); + break; + + case MEM_WARNING_UNSUPPORTED_X4DIMM: + printk(BIOS_DEBUG, "x4 DIMMs detected but not supported"); + break; + + case MEM_WARNING_UNSUPPORTED_RDIMM: + printk(BIOS_DEBUG, "Registered DIMMs detected but not supported"); + break; + +/* + case MEM_WARNING_UNSUPPORTED_LRDIMM: + printk(BIOS_DEBUG, "Load Reduced DIMMs detected but not supported"); + break; +*/ + + case MEM_WARNING_NO_SPDTRC_FOUND: + printk(BIOS_DEBUG, "NO_SPDTRC_FOUND"); + break; + + case MEM_WARNING_EMP_NOT_SUPPORTED: + printk(BIOS_DEBUG, "Processor is not capable for EMP");// + break; + + case MEM_WARNING_EMP_CONFLICT: + printk(BIOS_DEBUG, "EMP cannot be enabled if channel interleaving bank interleaving, or bank swizzle is enabled\n");// + break; + + case MEM_WARNING_EMP_NOT_ENABLED: + printk(BIOS_DEBUG, "Memory size is not power of two\n");// + break; + + case MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED: + printk(BIOS_DEBUG, "MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED\n"); + break; + + case MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED: + printk(BIOS_DEBUG, "MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED\n"); + break; + + case MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED: + printk(BIOS_DEBUG, "MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED\n"); + break; + + case MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED: + printk(BIOS_DEBUG, "MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED\n"); + break; + + case MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED: + printk(BIOS_DEBUG, "MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED\n"); + break; + +/* + case MEM_WARNING_INITIAL_DDR3VOLT_NONZERO: + printk(BIOS_DEBUG, "MEM_WARNING_INITIAL_DDR3VOLT_NONZERO\n"); + break; + + case MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO: + printk(BIOS_DEBUG, "MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO\n"); + break; +*/ + + case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: + printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); + if ((event->EventInfo & 0x000000FF) == 0x01) { + printk(BIOS_DEBUG, "AGESA_CACHE_SIZE_REDUCED\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x02) { + printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_1MB\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x03) { + printk(BIOS_DEBUG, "AGESA_CACHE_REGIONS_ACROSS_4GB\n"); + } + printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case CPU_WARNING_ADJUSTED_LEVELING_MODE: + printk(BIOS_DEBUG, "CPU_WARNING_ADJUSTED_LEVELING_MODE " + "requested: %lx, actual level:%lx\n", + event->DataParam1, + event->DataParam2); + break; + + case CPU_EVENT_PM_PSTATE_OVERCURRENT: + printk(BIOS_DEBUG, "CPU_EVENT_PM_PSTATE_OVERCURRENT " + "Socket: %lx, Pstate:%lx\n", + event->DataParam1, + event->DataParam2); + break; + + case CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG: + printk(BIOS_DEBUG, "CPU_WARNING_NONOPTIMAL_HT_ASSIST_CFG\n"); + break; + +/* + case CPU_EVENT_UNKNOWN_PROCESSOR_REVISION: + printk(BIOS_DEBUG, "CPU_EVENT_UNKNOWN_PROCESSOR_REVISION, socket: %lx, cpuid:%lx\n", + event->DataParam1, + event->DataParam2); + break; +*/ + + case HT_EVENT_OPT_REQUIRED_CAP_RETRY: + printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_RETRY, Socket %lx Link %lx Depth %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_OPT_REQUIRED_CAP_GEN3: + printk(BIOS_DEBUG, "HT_EVENT_OPT_REQUIRED_CAP_GEN3, Socket %lx Link %lx Depth %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_OPT_UNUSED_LINKS: + printk(BIOS_DEBUG, "HT_EVENT_OPT_UNUSED_LINKS, SocketA%lx LinkA%lx SocketB%lx LinkB%lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3, + event->DataParam4); + break; + + case HT_EVENT_OPT_LINK_PAIR_EXCEED: + printk(BIOS_DEBUG, "HT_EVENT_OPT_LINK_PAIR_EXCEED, SocketA%lx MasterLink%lx SocketB%lx AltLink%lx\n", + + event->DataParam1, + event->DataParam2, + event->DataParam3, + event->DataParam4); + default: + break; + } +} + +/** + * + */ +static void agesa_error(EVENT_PARAMS *event) +{ + + switch (event->EventInfo >> 24) { + case 0x04: + printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case 0x08: + printk(BIOS_DEBUG, "Processor: "); + break; + + case 0x10: + printk(BIOS_DEBUG, "Hyper Transport: "); + break; + + default: + break; + } + + switch (event->EventInfo) { + case MEM_ERROR_NO_DQS_POS_RD_WINDOW: + printk(BIOS_DEBUG, "No DQS Position window for RD DQS\n"); + break; + + case MEM_ERROR_SMALL_DQS_POS_RD_WINDOW: + printk(BIOS_DEBUG, "Small DQS Position window for RD DQS\n"); + break; + + case MEM_ERROR_NO_DQS_POS_WR_WINDOW: + printk(BIOS_DEBUG, "No DQS Position window for WR DQS\n"); + break; + + case MEM_ERROR_SMALL_DQS_POS_WR_WINDOW: + printk(BIOS_DEBUG, "Small DQS Position window for WR DQS\n"); + break; + + case MEM_ERROR_DIMM_SPARING_NOT_ENABLED: + printk(BIOS_DEBUG, "DIMM sparing has not been enabled for an internal issues\n"); + break; + + case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE: + printk(BIOS_DEBUG, "Receive Enable value is too large\n"); + break; + case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW: + printk(BIOS_DEBUG, "There is no DQS receiver enable window\n"); + break; + + case MEM_ERROR_DRAM_ENABLED_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling DramEnabled bit\n"); + break; + + case MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling DctAccessDone bit\n"); + break; + + case MEM_ERROR_SEND_CTRL_WORD_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling SendCtrlWord bit\n"); + break; + + case MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling PrefDramTrainMode bit\n"); + break; + + case MEM_ERROR_ENTER_SELF_REF_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling EnterSelfRef bit\n"); + break; + + case MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling FreqChgInProg bit\n"); + break; + + case MEM_ERROR_EXIT_SELF_REF_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling ExitSelfRef bit\n"); + break; + + case MEM_ERROR_SEND_MRS_CMD_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling SendMrsCmd bit\n"); + break; + + case MEM_ERROR_SEND_ZQ_CMD_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling SendZQCmd bit\n"); + break; + + case MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling DctExtraAccessDone bit\n"); + break; + + case MEM_ERROR_MEM_CLR_BUSY_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling MemClrBusy bit\n"); + break; + + case MEM_ERROR_MEM_CLEARED_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling MemCleared bit\n"); + break; + + case MEM_ERROR_FLUSH_WR_TIME_OUT: + printk(BIOS_DEBUG, "Time out when polling FlushWr bit\n"); + break; + + case MEM_ERROR_MAX_LAT_NO_WINDOW: + printk(BIOS_DEBUG, "Fail to find pass during Max Rd Latency training\n"); + break; + + case MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL: + printk(BIOS_DEBUG, "Fail to launch training code on an AP\n"); + break; + + case MEM_ERROR_PARALLEL_TRAINING_TIME_OUT: + printk(BIOS_DEBUG, "Fail to finish parallel training\n"); + break; + + case MEM_ERROR_NO_ADDRESS_MAPPING: + printk(BIOS_DEBUG, "No address mapping found for a dimm\n"); + break; + + case MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT: + printk(BIOS_DEBUG, "There is no DQS receiver enable window and the value is equal to the largest value\n"); + break; + + case MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE: + printk(BIOS_DEBUG, "Receive Enable value is too large and is 1 less than limit\n"); + break; + + case MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR: + printk(BIOS_DEBUG, "SPD Checksum error for NV_SPDCHK_RESTRT\n"); + break; + + case MEM_ERROR_NO_CHIPSELECT: + printk(BIOS_DEBUG, "No chipselects found\n"); + break; + + case MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM: + printk(BIOS_DEBUG, "Unbuffered dimm is not supported at 333MHz\n"); + break; + + case MEM_ERROR_WL_PRE_OUT_OF_RANGE: + printk(BIOS_DEBUG, "Returned PRE value during write levelizzation was out of range\n"); + break; + + case CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE: + printk(BIOS_DEBUG, "No heap is allocated for BrandId structure\n"); + break; + + case CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED: + printk(BIOS_DEBUG, "Unable to load micro code patch\n"); + break; + + case CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE: + printk(BIOS_DEBUG, "No heap is allocated for the Pstate structure\n"); + break; + +/* + case CPU_ERROR_PM_NB_PSTATE_MISMATCH: + printk(BIOS_DEBUG, "NB P-state indicated by Index was disabled due to mismatch between processors\n"); + break; +*/ + + case CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR: + printk(BIOS_DEBUG, "Allocation rule number that has been violated:"); + if ((event->EventInfo & 0x000000FF) == 0x04) { + printk(BIOS_DEBUG, "AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x05) { + printk(BIOS_DEBUG, "AGESA_START_ADDRESS_LESS_D0000\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x06) { + printk(BIOS_DEBUG, "AGESA_THREE_CACHE_REGIONS_ABOVE_1MB\n"); + } else if ((event->EventInfo & 0x000000FF) == 0x07) { + printk(BIOS_DEBUG, "AGESA_DEALLOCATE_CACHE_REGIONS\n"); + } + printk(BIOS_DEBUG, "cache region index:%lx, start:%lx size:%lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_COH_NO_TOPOLOGY: + printk(BIOS_DEBUG, "no Matching Topology was found during coherent initializatio TotalHtNodes: %lx\n", + event->DataParam1); + break; + + case HT_EVENT_NCOH_BUID_EXCEED: + printk(BIOS_DEBUG, "there is a limit of 32 unit IDs per chain Socket%lx Link%lx Depth%lx" + "Current BUID: %lx, Unit Count: %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3, + event->DataParam4 >> 16, + event->DataParam4 & 0x0000FFFF); + break; + + case HT_EVENT_NCOH_BUS_MAX_EXCEED: + printk(BIOS_DEBUG, "maximum auto bus limit exceeded, Socket %lx Link %lx Bus %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_NCOH_CFG_MAP_EXCEED: + printk(BIOS_DEBUG, "there is a limit of four non-coherent chains, Socket %lx Link %lx\n", + event->DataParam1, + event->DataParam2); + break; + + case HT_EVENT_NCOH_DEVICE_FAILED: + printk(BIOS_DEBUG, "after assigning an IO Device an ID, it does not respond at the new ID" + "Socket %lx Link %lx Depth %lx DeviceID %lx\n", + event->DataParam1, + event->DataParam2, + event->DataParam3, + event->DataParam4); + default: + break; + } +} +/** + * + */ +static void agesa_critical(EVENT_PARAMS *event) +{ + switch (event->EventInfo) { + case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3: + printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR3\n", + event->DataParam1); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2: + printk(BIOS_DEBUG, "Socket: %lx, Heap allocation error for DMI table for DDR2\n", + event->DataParam1); + break; + + case MEM_ERROR_UNSUPPORTED_DIMM_CONFIG: + printk(BIOS_DEBUG, "Socket: %lx, Dimm population is not supported\n", + event->DataParam1); + break; + + case HT_EVENT_COH_PROCESSOR_TYPE_MIX: + printk(BIOS_DEBUG, "Socket %lx Link %lx TotalSockets %lx, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case HT_EVENT_COH_MPCAP_MISMATCH: + printk(BIOS_DEBUG, "Socket %lx Link %lx MpCap %lx TotalSockets %lx, HT_EVENT_COH_MPCAP_MISMATCH\n", + event->DataParam1, + event->DataParam2, + event->DataParam3, + event->DataParam4); + default: + break; + } +} + +/** + * + */ +static void agesa_fatal(EVENT_PARAMS *event) +{ + + switch (event->EventInfo >> 24) { + case 0x04: + printk(BIOS_DEBUG, "Memory: Socket %lx Dct %lx Channel%lx ", + event->DataParam1, + event->DataParam2, + event->DataParam3); + break; + + case 0x08: + printk(BIOS_DEBUG, "Processor: "); + break; + + case 0x10: + printk(BIOS_DEBUG, "Hyper Transport: "); + break; + + default: + break; + } + + switch (event->EventInfo) { + case MEM_ERROR_MINIMUM_MODE: + printk(BIOS_DEBUG, "Running in minimum mode\n"); + break; + + case MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM: + printk(BIOS_DEBUG, "DIMM modules are missmatched\n"); + break; + + case MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM: + printk(BIOS_DEBUG, "No DIMMs have been foun\n"); + break; + + case MEM_ERROR_MISMATCH_DIMM_CLOCKS: + printk(BIOS_DEBUG, "DIMM clocks miss-matched\n"); + break; + + case MEM_ERROR_NO_CYC_TIME: + printk(BIOS_DEBUG, "No cycle time found\n"); + break; + case MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS: + printk(BIOS_DEBUG, "Heap allocation error with dynamic storing of trained timings\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs: + printk(BIOS_DEBUG, "Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV: + printk(BIOS_DEBUG, "Heap allocation error with REMOTE_TRAINING_ENV\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_SPD: + printk(BIOS_DEBUG, "Heap allocation error for SPD data\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA: + printk(BIOS_DEBUG, "Heap allocation error for RECEIVED_DATA during parallel training\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS: + printk(BIOS_DEBUG, "Heap allocation error for S3 \"SPECIAL_CASE_REGISTER\"\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA: + printk(BIOS_DEBUG, "Heap allocation error for Training Data\n"); + break; + + case MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK: + printk(BIOS_DEBUG, "Heap allocation error for DIMM Identify \"MEM_NB_BLOCK\"\n"); + break; + + case MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM: + printk(BIOS_DEBUG, "No Constructor for DIMM Identify\n"); + break; + + case MEM_ERROR_VDDIO_UNSUPPORTED: + printk(BIOS_DEBUG, "VDDIO of the dimms on the board is not supported\n"); + break; + + case CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT: + printk(BIOS_DEBUG, "Socket: %lx, All PStates exceeded the motherboard current limit on specified socket\n", + event->DataParam1); + break; + + default: + break; + } +} + +/** + * + * Interprte the agesa event log to an user readable string + */ +static void interpret_agesa_eventlog(EVENT_PARAMS *event) +{ + switch (event->EventClass) { + case AGESA_BOUNDS_CHK: + agesa_bound_check(event); + break; + + case AGESA_ALERT: + agesa_alert(event); + break; + + case AGESA_WARNING: + agesa_warning(event); + break; + + case AGESA_ERROR: + agesa_error(event); + break; + + case AGESA_CRITICAL: + agesa_critical(event); + break; + + case AGESA_FATAL: + agesa_fatal(event); + break; + + default: + break; + } +} + +/** + * @param HeapStatus -the current HeapStatus + */ +UINT32 agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + printk(BIOS_DEBUG, "enter in %s\n", __func__); + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, + 0, + sizeof(EVENT_PARAMS), + &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = NULL; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + /* I have to know the current HeapStatus to Locate the EventLogHeapPointer */ + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG,"\nEventLog: EventClass = %lx, EventInfo = %lx.\n",AmdEventParams.EventClass,AmdEventParams.EventInfo); + printk(BIOS_DEBUG," Param1 = %lx, Param2 = %lx.\n",AmdEventParams.DataParam1,AmdEventParams.DataParam2); + printk(BIOS_DEBUG," Param3 = %lx, Param4 = %lx.\n",AmdEventParams.DataParam3,AmdEventParams.DataParam4); + interpret_agesa_eventlog(&AmdEventParams); + Status = AmdReadEventLog(&AmdEventParams); + } + + printk(BIOS_DEBUG, "exit %s \n", __func__); + return (UINT32)Status; +} + diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.h b/src/mainboard/supermicro/h8scm/agesawrapper.h new file mode 100644 index 0000000..43c7d10 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/agesawrapper.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +#ifndef _AGESAWRAPPER_H_ +#define _AGESAWRAPPER_H_ + +#include <stdint.h> +#include "Porting.h" +#include "AGESA.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS + +enum { + PICK_DMI, /* DMI Interface */ + PICK_PSTATE, /* Acpi Pstate SSDT Table */ + PICK_SRAT, /* SRAT Table */ + PICK_SLIT, /* SLIT Table */ + PICK_WHEA_MCE, /* WHEA MCE table */ + PICK_WHEA_CMC, /* WHEA CMV table */ + PICK_ALIB, /* SACPI SSDT table with ALIB implementation */ +}; + + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +typedef struct { + UINT32 CalloutName; + AGESA_STATUS (*CalloutPtr)(UINT32 Func, UINT32 Data, VOID* ConfigPtr); +} BIOS_CALLOUT_STRUCT; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * E X P O R T E D F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------------------- + * L O C A L F U N C T I O N S + *--------------------------------------------------------------------------------------- + */ + +UINT32 agesawrapper_amdinitreset (void); +UINT32 agesawrapper_amdinitearly (void); +UINT32 agesawrapper_amdinitenv (void); +UINT32 agesawrapper_amdinitlate (void); +UINT32 agesawrapper_amdinitpost (void); +UINT32 agesawrapper_amdinitmid (void); +UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus); +UINT32 agesawrapper_amdinitmmio (void); +void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask(UINT32 Data, VOID *ConfigPtr); + +#endif diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c new file mode 100644 index 0000000..adf368e --- /dev/null +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -0,0 +1,616 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "CommonReturns.h" +#include "AdvancedApi.h" +#include <PlatformMemoryConfiguration.h> +#include "Filecode.h" +#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE +//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE +/* AGESA will check the OEM configuration during preprocessing stage, + * coreboot enable -Wundef option, so we should make sure we have all contanstand defined + */ +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE*/ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode + +/* User makes option selections here + * Comment out the items wanted to be included in the build. + * Uncomment those items you with to REMOVE from the build. + */ +//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE +//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE +//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +//#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE +//#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE +#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE +//#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE +////#define BLDOPT_REMOVE_ACPI_PSTATES TRUE +////#define BLDOPT_REMOVE_SRAT TRUE +////#define BLDOPT_REMOVE_SLIT TRUE +//#define BLDOPT_REMOVE_WHEA TRUE +//#define BLDOPT_REMOVE_DMI TRUE + +/*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */ +#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE + +//#define BLDOPT_REMOVE_HT_ASSIST TRUE +//#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE +//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE + +/* Build configuration values here. + */ +#define BLDCFG_VRM_CURRENT_LIMIT 120000 +#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 +#define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 0 +#define BLDCFG_PLAT_NUM_IO_APICS 3 +#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST +#define BLDCFG_MEM_INIT_PSTATE 0 +#define BLDCFG_AMD_PSTATE_CAP_VALUE 0 + +#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_SERVER + +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY//1600 +#define BLDCFG_MEMORY_MODE_UNGANGED TRUE +#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE +#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED +#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE +#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE +#define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE//TRUE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE//TRUE +#define BLDCFG_MEMORY_POWER_DOWN FALSE +#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHANNEL +#define BLDCFG_ONLINE_SPARE FALSE +#define BLDCFG_BANK_SWIZZLE TRUE +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO +#define BLDCFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY //DDR800_FREQUENCY +#define BLDCFG_DQS_TRAINING_CONTROL TRUE +#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE +#define BLDCFG_USE_BURST_MODE FALSE +#define BLDCFG_MEMORY_ALL_CLOCKS_ON TRUE +#define BLDCFG_ENABLE_ECC_FEATURE TRUE +#define BLDCFG_ECC_REDIRECTION FALSE +#define BLDCFG_SCRUB_IC_RATE 0 +#define BLDCFG_ECC_SYNC_FLOOD TRUE +#define BLDCFG_ECC_SYMBOL_SIZE 4 + +#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS +#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER + +/** + * Enable Message Based C1e CPU feature in multi-socket systems. + * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value, + * else the feature cannot be enabled. + */ +#define BLDCFG_PLATFORM_C1E_MODE C1eModeMsgBased +#define BLDCFG_PLATFORM_C1E_OPDATA 0x80//TODO +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0 +//#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0 + +#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 +#define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000 +#define BLDCFG_1GB_ALIGN FALSE +//#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C' +//#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' +// + +// Select the platform control flow mode for performance tuning. +#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm + +/** + * Enable the probe filtering performance tuning feature. + * The probe filter provides filtering of broadcast probes to + * improve link bandwidth and performance for multi- node systems. + * + * This feature may interact with other performance features. + * TRUE -Enable the feature (default) if supported by all processors, + * based on revision and presence of L3 cache. + * The feature is not enabled if there are no coherent HT links. + * FALSE -Do not enable the feature regardless of the configuration. + */ +//TODO enable it, +//but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone +//hang in F10HtAssistInit() do{...} while(PFInitDone != 1) +#define BLDCFG_USE_HT_ASSIST FALSE + +/** + * The socket and link match values are platform specific + */ +CONST MANUAL_BUID_SWAP_LIST ROMDATA h8scm_manual_swaplist[2] = +{ + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + { //BUID Swap List + { //BUID Swaps + /* Each Non-coherent chain may have a list of device swaps, + * Each item specify a device will be swap from its current id to a new one + */ + /* FromID 0x00 is the chain with the southbridge */ + /* 'Move' device zero to device zero, All others are non applicable */ + {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + }, + + { //The ordered final BUIDs + /* Specify the final BUID to be zero, All others are non applicable */ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + } + } + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } +}; + +#if CONFIG_HT3_SUPPORT == 1 +/** + * The socket and link match values are platform specific + * + */ +CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] = +{ + { + /* On the reference platform, these settings apply to all coherent links */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } +}; + +CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] = +{ + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } +}; +#else //CONFIG_HT3_SUPPORT == 0 +CONST CPU_TO_CPU_PCB_LIMITS ROMDATA h8scm_cpu2cpu_limit_list[2] = +{ + { + /* On the reference platform, these settings apply to all coherent links */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY, + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } +}; + +CONST IO_PCB_LIMITS ROMDATA h8scm_io_limit_list[2] = +{ + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY, + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL + } +}; +#endif //CONFIG_HT3_SUPPORT == 0 + +/** + * HyperTransport links will typically require an equalization at high frequencies. + * This is called deemphasis. + * + * Deemphasis is specified as levels, for example, -3 db. + * There are two levels for each link, its receiver deemphasis level and its DCV level, + * which is based on the far side transmitter's deemphasis. + * For each link, different levels may be required at each link frequency. + * + * Coherent connections between processors should have an entry for the port on each processor. + * There should be one entry for the host root port of each non-coherent chain. + * + * AGESA initialization code does not set deemphasis on IO Devices. + * A default is provided for internal links of MCM processors, and + * those links will generally not need deemphasis structures. + */ +CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA h8scm_deemphasis_list[] = +{ + /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */ + + /* Non-coherent link deemphasis. */ + {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5}, + {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7}, + {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9}, + + /* Coherent link deemphasis. */ + {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone}, + {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3}, + {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6}, + {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6}, + {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8}, + {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11}, + + /* End of the list */ + { + HT_LIST_TERMINAL + } +}; + +/** + * For systems using socket infrastructure that permits strapping the SBI + * address for each socket, this should be used to provide a socket ID value. + * This is referred to as the hardware method for socket naming, and is the + * preferred solution. + */ +/* + * I do NOT know howto config socket id in simnow, + * so use this software way to make HT works in simnow, + * real hardware do not need this Socket Map. + * + * A physical socket map for a 4 G34 Sockets MCM processors topology, + * reference the mainboard schemantic in detail. + * + */ +CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA h8scm_socket_map[] = +{ +#define HT_SOCKET0 0 +#define HT_SOCKET1 1 +#define HT_SOCKET2 2 +#define HT_SOCKET3 3 + +/** + * 0-3 are sublink 0, 4-7 are sublink 1 + */ +#define HT_LINK0A 0 +#define HT_LINK1A 1 +#define HT_LINK2A 2 +#define HT_LINK3A 3 +#define HT_LINK0B 4 +#define HT_LINK1B 5 +#define HT_LINK2B 6 +#define HT_LINK3B 7 + + /* Source Socket, Link, Target Socket */ + {HT_SOCKET0, HT_LINK0A, HT_SOCKET1}, + {HT_SOCKET0, HT_LINK0B, HT_SOCKET3}, + {HT_SOCKET0, HT_LINK1A, HT_SOCKET1}, + {HT_SOCKET0, HT_LINK1B, HT_SOCKET3}, + {HT_SOCKET0, HT_LINK3A, HT_SOCKET2}, + {HT_SOCKET0, HT_LINK3B, HT_SOCKET2}, + + {HT_SOCKET1, HT_LINK0A, HT_SOCKET2}, + {HT_SOCKET1, HT_LINK0B, HT_SOCKET3}, + {HT_SOCKET1, HT_LINK1A, HT_SOCKET0}, + {HT_SOCKET1, HT_LINK1B, HT_SOCKET2}, + {HT_SOCKET1, HT_LINK3A, HT_SOCKET0}, + {HT_SOCKET1, HT_LINK3B, HT_SOCKET3}, + + {HT_SOCKET2, HT_LINK0A, HT_SOCKET3}, + {HT_SOCKET2, HT_LINK0B, HT_SOCKET0}, + {HT_SOCKET2, HT_LINK1A, HT_SOCKET3}, + {HT_SOCKET2, HT_LINK1B, HT_SOCKET1}, + {HT_SOCKET2, HT_LINK3A, HT_SOCKET1}, + {HT_SOCKET2, HT_LINK3B, HT_SOCKET0}, + + {HT_SOCKET3, HT_LINK0A, HT_SOCKET2}, + {HT_SOCKET3, HT_LINK0B, HT_SOCKET1}, + {HT_SOCKET3, HT_LINK1A, HT_SOCKET1}, + {HT_SOCKET3, HT_LINK1B, HT_SOCKET0}, + {HT_SOCKET3, HT_LINK3A, HT_SOCKET0}, + {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, +}; + +CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] = +{ + {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E}, + {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000}, + {AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818}, + {AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818}, + {CPU_LIST_TERMINAL} +}; + +#define BLDCFG_BUID_SWAP_LIST &h8scm_manual_swaplist +#define BLDCFG_HTFABRIC_LIMITS_LIST &h8scm_cpu2cpu_limit_list +#define BLDCFG_HTCHAIN_LIMITS_LIST &h8scm_io_limit_list +#define BLDCFG_PLATFORM_DEEMPHASIS_LIST &h8scm_deemphasis_list +#define BLDCFG_AP_MTRR_SETTINGS_LIST &h8scm_ap_mtrr_list +//#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP &h8scm_socket_map + + +/* Process the options... + * This file include MUST occur AFTER the user option selection settings + */ +#define AGESA_ENTRY_INIT_RESET TRUE//FALSE +#define AGESA_ENTRY_INIT_RECOVERY FALSE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE +#define AGESA_ENTRY_INIT_ENV TRUE +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE TRUE +#define AGESA_ENTRY_INIT_RESUME TRUE +#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE +#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE + +/* +#if (CONFIG_CPU_AMD_AGESA_FAMILY15 == 1) + #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE +#endif +#if (CONFIG_CPU_AMD_AGESA_FAMILY10 == 1) + #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE +#endif +*/ + +//#include "GnbInterface.h" /*prototype for GnbInterfaceStub*/ +#include "SanMarinoInstall.h" + +/*---------------------------------------------------------------------------------------- + * CUSTOMER OVERIDES MEMORY TABLE + *---------------------------------------------------------------------------------------- + */ + +//reference BKDG Table87: works +#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM. +#define SEED_A 0x54 +#define SEED_B 0x4D +#define SEED_C 0x45 +#define SEED_D 0x40 + +#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM. +//4B 41 51 + +/* + * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA + * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable + * is populated, AGESA will base its settings on the data from the table. Otherwise, it will + * use its default conservative settings. + */ +CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { + // + // The following macros are supported (use comma to separate macros): + // + // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap) + // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap. + // AGESA will base on this value to disable unused MemClk to save power. + // Example: + // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below: + // Bit AM3/S1g3 pin name + // 0 M[B,A]_CLK_H/L[0] + // 1 M[B,A]_CLK_H/L[1] + // 2 M[B,A]_CLK_H/L[2] + // 3 M[B,A]_CLK_H/L[3] + // 4 M[B,A]_CLK_H/L[4] + // 5 M[B,A]_CLK_H/L[5] + // 6 M[B,A]_CLK_H/L[6] + // 7 M[B,A]_CLK_H/L[7] + // And platform has the following routing: + // CS0 M[B,A]_CLK_H/L[4] + // CS1 M[B,A]_CLK_H/L[2] + // CS2 M[B,A]_CLK_H/L[3] + // CS3 M[B,A]_CLK_H/L[5] + // Then platform can specify the following macro: + // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00) + // + // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap) + // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap. + // AGESA will base on this value to tristate unused CKE to save power. + // + // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap) + // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap. + // AGESA will base on this value to tristate unused ODT pins to save power. + // + // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap) + // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap. + // AGESA will base on this value to tristate unused Chip select to save power. + // + // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) + // Specifies the number of DIMM slots per channel. + // + // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) + // Specifies the number of Chip selects per channel. + // + // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) + // Specifies the number of channels per socket. + // + // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED) + // Specifies DDR bus speed of channel ChannelID on socket SocketID. + // + // DRAM_TECHNOLOGY(ANY_SOCKET, DDR3_TECHNOLOGY), + // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...) + // + // WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, + // Byte6Seed, Byte7Seed, ByteEccSeed) + // Specifies the write leveling seed for a channel of a socket. + // + + /* Specifies the write leveling seed for a channel of a socket. + * WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, + * ByteEccSeed) + */ +// WRITE_LEVELING_SEED( +// ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, +// F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, +// F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, +// F15_WL_SEED), + + /* HW_RXEN_SEED(SocketID, ChannelID, DimmID, + * Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, + * Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed) + */ +// HW_RXEN_SEED( +// ANY_SOCKET, CHANNEL_A, ALL_DIMMS, +// SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, +// SEED_A), +// HW_RXEN_SEED( +// ANY_SOCKET, CHANNEL_B, ALL_DIMMS, +// SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, +// SEED_B), +// HW_RXEN_SEED( +// ANY_SOCKET, CHANNEL_C, ALL_DIMMS, +// SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, +// SEED_C), +// HW_RXEN_SEED( +// ANY_SOCKET, CHANNEL_D, ALL_DIMMS, +// SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, +// SEED_D), + + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), //max 3 + PSO_END +}; + +/* + * These tables are optional and may be used to adjust memory timing settings + */ +//HY Customer table +UINT8 AGESA_MEM_TABLE_HY[][sizeof (MEM_TABLE_ALIAS)] = +{ + // Hardcoded Memory Training Values + + // The following macro should be used to override training values for your platform + // + // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20), + // + // NOTE: + // The following training hardcode values are example values that were taken from a tilapia motherboard + // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in + // the table and replace the byte lane values with your own. + // + // ------------------ BYTE LANES ---------------------- + // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC + // Write Data Timing + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0 + // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1 + + // DQS Receiver Enable + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x19, 0x0F, 0x08, 0x1D, 0x17, 0x1B, 0x03, 0x0F, 0x14),// DCT0, DIMM1 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0 + // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x19, 0x0F, 0x08, 0x1D, 0x17, 0x1B, 0x03, 0x10, 0x14),// DCT1, DIMM1 + + // Write DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1 + + // Read DQS Delays + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0 + // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1 + //-------------------------------------------------------------------------------------------------------------------------------------------------- + // TABLE END + NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table +}; +UINT8 SizeOfTableHy = sizeof (AGESA_MEM_TABLE_HY) / sizeof (AGESA_MEM_TABLE_HY[0]); + diff --git a/src/mainboard/supermicro/h8scm/chip.h b/src/mainboard/supermicro/h8scm/chip.h new file mode 100644 index 0000000..a252705 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/chip.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; diff --git a/src/mainboard/supermicro/h8scm/cmos.layout b/src/mainboard/supermicro/h8scm/cmos.layout new file mode 100644 index 0000000..3b98cbb --- /dev/null +++ b/src/mainboard/supermicro/h8scm/cmos.layout @@ -0,0 +1,118 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +#***************************************************************************** + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb new file mode 100644 index 0000000..5f13750 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/devicetree.cb @@ -0,0 +1,128 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +chip northbridge/amd/agesa/family15/root_complex + device lapic_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end #f15 + #device lapic 0x10 on end #f10 + end + end + device pci_domain 0 on + subsystemid 0x15d9 0xab11 inherit #Supermicro + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex 0x9600 + device pci 0.1 on end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 + device pci 3.0 on end # GPP1 Port1 + device pci 4.0 on end # GPP3a Port0 x4 SAS + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 on end # GPP3a Port4 x1 NC + device pci a.0 on end # GPP3a Port5 x1 NC + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 off end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "1" # Configuration 16:0 default + #register "gpp2_configuration" = "0" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x61f" + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8scm not have codec. + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 #keyboard + irq 0x72 = 0x0C #mouse + end + device pnp 2e.6 off # SPI + end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b off # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 + end # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end # southbridge/amd/cimx/sb700 + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end #f15 + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex + end #pci_domain +end #northbridge/amd/agesa/family15/root_complex + diff --git a/src/mainboard/supermicro/h8scm/dimmSpd.c b/src/mainboard/supermicro/h8scm/dimmSpd.c new file mode 100644 index 0000000..81bdbd6 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/dimmSpd.c @@ -0,0 +1,229 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info); +#define DIMENSION(array)(sizeof (array)/ sizeof (array [0])) + +/* SP5100 GPIO 49-52 contoled by SMBUS PCI_Reg 0x52 */ +#define SP5100_GPIO37_46_47_48 0xA6 +#define SP5100_GPIO49_52 0x50 + +/** + * TODO not support all GPIO yet + * @param reg -GPIO Cntrl Register + * @param out -GPIO bitmap + * @param out -GPIO enable bitmap + * @return old setting + */ +static u8 sp5100_set_gpio(u8 reg, u8 out, u8 enable) +{ + u8 value, ret; + device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS + + value = pci_read_config8(sm_dev, reg); + ret = value; + value &= ~(enable); + value |= out; + value &= ~(enable << 4); + pci_write_config8(sm_dev, reg, value); + + return ret; +} + +static void sp5100_restore_gpio(u8 reg, u8 value) +{ + device_t sm_dev = PCI_DEV(0, 0x14, 0); + pci_write_config8(sm_dev, reg, value); +} + +/*----------------------------------------------------------------------------- + * + * SPD address table - porting required + */ +static const UINT8 spdAddressLookup [1] [2] [2] = { // socket, channel, dimm + /* socket 0 */ + { + {0xA4, 0xA6}, + {0xA0, 0xA2}, + }, + /* socket 1 */ + /* { */ + /* {0xA0, 0xA4, 0xA8}, */ + /* {0xA2, 0xA6, 0xAA}, */ + /* }, */ +}; + +/*----------------------------------------------------------------------------- + * + * readSmbusByteData - read a single SPD byte from any offset + */ + +static int readSmbusByteData (int iobase, int address, char *buffer, int offset) +{ + unsigned int status; + UINT64 limit; + + address |= 1; // set read bit + + outb(0xFF, iobase + 0); // clear error status + outb(0x1F, iobase + 1); // clear error status + outb(offset, iobase + 3); // offset in eeprom + outb(address, iobase + 4); // slave address and read bit + outb(0x48, iobase + 2); // read byte command + + // time limit to avoid hanging for unexpected error status (should never happen) + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = inb(iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = inb(iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*----------------------------------------------------------------------------- + * + * readSmbusByte - read a single SPD byte from the default offset + * this function is faster function readSmbusByteData + */ + +static int readSmbusByte (int iobase, int address, char *buffer) +{ + unsigned int status; + UINT64 limit; + + outb(0xFF, iobase + 0); // clear error status + outb(0x44, iobase + 2); // read command + + // time limit to avoid hanging for unexpected error status + limit = __rdtsc () + 2000000000 / 10; + for (;;) + { + status = inb(iobase); + if (__rdtsc () > limit) break; + if ((status & 2) == 0) continue; // SMBusInterrupt not set, keep waiting + if ((status & 1) == 1) continue; // HostBusy set, keep waiting + break; + } + + buffer [0] = inb(iobase + 5); + if (status == 2) status = 0; // check for done with no errors + return status; +} + +/*--------------------------------------------------------------------------- + * + * readspd - Read one or more SPD bytes from a DIMM. + * Start with offset zero and read sequentially. + * Optimization relies on autoincrement to avoid + * sending offset for every byte. + * Reads 128 bytes in 7-8 ms at 400 KHz. + */ + +static int readspd (int iobase, int SmbusSlaveAddress, char *buffer, int count) +{ + int index, error; + + /* read the first byte using offset zero */ + error = readSmbusByteData (iobase, SmbusSlaveAddress, buffer, 0); + if (error) { + return error; + } + + /* read the remaining bytes using auto-increment for speed */ + for (index = 1; index < count; index++) + { + error = readSmbusByte (iobase, SmbusSlaveAddress, buffer + index); + if (error) + return error; + } + + return 0; +} + +static void setupFch (int ioBase) +{ + outb(66000000 / 400000 / 4, ioBase + 0x0E); /* set SMBus clock to 400 KHz */ +} + +AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info) +{ + AGESA_STATUS status; + int spdAddress, ioBase, i; + u8 i2c_channel; + u8 backup; + device_t sm_dev; + + if (info->SocketId >= DIMENSION (spdAddressLookup )) return AGESA_ERROR; + if (info->MemChannelId >= DIMENSION (spdAddressLookup[0] )) return AGESA_ERROR; + if (info->DimmId >= DIMENSION (spdAddressLookup[0][0])) return AGESA_ERROR; + i2c_channel = (UINT8) info->SocketId; + + printk(BIOS_DEBUG, "S=%x, c=%x, d=%x\n", info->SocketId, info->MemChannelId, info->DimmId); + /* set IDTQS3253 i2c channel + * GPIO49,48 control the S1,S0 + * S1 S0 true table + * 0 0 channel 0 + * 0 1 channel 1 + * 1 0 channel 2 - Socket 0 + * 1 1 channel 3 - Socket 1 + * Note: Above is abstracted from Schemetic. But actually it seems to be other way. + * 1 0 channel 2 - Socket 1 + * 1 1 channel 3 - Socket 0 + * Note: The DIMMs need to be plugged in from the farthest slot for each channel. + */ + //backup = sp5100_set_gpio(SP5100_GPIO49_52, 0x1, 0x1); + //sp5100_set_gpio(SP5100_GPIO37_46_47_48, (~i2c_channel & 1) << 3, 0x1 << 3); + + spdAddress = spdAddressLookup [info->SocketId] [info->MemChannelId] [info->DimmId]; + if (spdAddress == 0) + return AGESA_ERROR; + + /* + * SMBus Base Address was set during southbridge early setup. + * e.g. sb700 IO mapped SMBUS_IO_BASE 0x6000, CIMX using 0xB00 as default + */ + sm_dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM), 0); + ioBase = pci_read_config32(sm_dev, 0x90) & (0xFFFFFFF0); + setupFch(ioBase); + + status = readspd(ioBase, spdAddress, (void *)info->Buffer, 256); + for (i=0; i<256; i++) { + printk(BIOS_DEBUG, "%02X ", info->Buffer[i]); + if ((i%16)==15) + printk(BIOS_DEBUG, "\n"); + } + printk(BIOS_DEBUG, "\n"); + //sp5100_restore_gpio(SP5100_GPIO49_52, backup); + + return status; +} diff --git a/src/mainboard/supermicro/h8scm/dsdt.asl b/src/mainboard/supermicro/h8scm/dsdt.asl new file mode 100644 index 0000000..bf09231 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/dsdt.asl @@ -0,0 +1,1804 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "S8226 ", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* + * Processor Object + * + */ + Scope (\_PR) { /* define processor scope */ + Processor( + C000, /* name space name */ + 0x00, /* Unique number for this processor */ + 0x810, /* PBLK system I/O address !hardcoded! */ + 0x06 /* PBLKLEN for boot processor */ + ) { + //#include "acpi/cpstate.asl" + } + Processor(C001, 0x01, 0x00000000, 0x00) {} + Processor(C002, 0x02, 0x00000000, 0x00) {} + Processor(C003, 0x03, 0x00000000, 0x00) {} + Processor(C004, 0x04, 0x00000000, 0x00) {} + Processor(C005, 0x05, 0x00000000, 0x00) {} + Processor(C006, 0x06, 0x00000000, 0x00) {} + Processor(C007, 0x07, 0x00000000, 0x00) {} + Processor(C008, 0x08, 0x00000000, 0x00) {} + Processor(C009, 0x09, 0x00000000, 0x00) {} + Processor(C00A, 0x0A, 0x00000000, 0x00) {} + Processor(C00B, 0x0B, 0x00000000, 0x00) {} + Processor(C00C, 0x0C, 0x00000000, 0x00) {} + Processor(C00D, 0x0D, 0x00000000, 0x00) {} + Processor(C00E, 0x0E, 0x00000000, 0x00) {} + Processor(C00F, 0x0F, 0x00000000, 0x00) {} + Processor(C010, 0x10, 0x00000000, 0x00) {} + Processor(C011, 0x11, 0x00000000, 0x00) {} + Processor(C012, 0x12, 0x00000000, 0x00) {} + Processor(C013, 0x13, 0x00000000, 0x00) {} + Processor(C014, 0x14, 0x00000000, 0x00) {} + Processor(C015, 0x15, 0x00000000, 0x00) {} + Processor(C016, 0x16, 0x00000000, 0x00) {} + Processor(C017, 0x17, 0x00000000, 0x00) {} + Processor(C018, 0x18, 0x00000000, 0x00) {} + Processor(C019, 0x19, 0x00000000, 0x00) {} + Processor(C01A, 0x1A, 0x00000000, 0x00) {} + Processor(C01B, 0x1B, 0x00000000, 0x00) {} + Processor(C01C, 0x1C, 0x00000000, 0x00) {} + Processor(C01D, 0x1D, 0x00000000, 0x00) {} + Processor(C01E, 0x1E, 0x00000000, 0x00) {} + Processor(C01F, 0x1F, 0x00000000, 0x00) {} + Processor(C020, 0x20, 0x00000000, 0x00) {} + Processor(C021, 0x21, 0x00000000, 0x00) {} + Processor(C022, 0x22, 0x00000000, 0x00) {} + Processor(C023, 0x23, 0x00000000, 0x00) {} + Processor(C024, 0x24, 0x00000000, 0x00) {} + Processor(C025, 0x25, 0x00000000, 0x00) {} + Processor(C026, 0x26, 0x00000000, 0x00) {} + Processor(C027, 0x27, 0x00000000, 0x00) {} + Processor(C028, 0x28, 0x00000000, 0x00) {} + Processor(C029, 0x29, 0x00000000, 0x00) {} + Processor(C02A, 0x2A, 0x00000000, 0x00) {} + Processor(C02B, 0x2B, 0x00000000, 0x00) {} + Processor(C02C, 0x2C, 0x00000000, 0x00) {} + Processor(C02D, 0x2D, 0x00000000, 0x00) {} + Processor(C02E, 0x2E, 0x00000000, 0x00) {} + Processor(C02F, 0x2F, 0x00000000, 0x00) {} + Alias (C000, CPU0) + Alias (C001, CPU1) + Alias (C002, CPU2) + Alias (C003, CPU3) + Alias (C004, CPU4) + Alias (C005, CPU5) + Alias (C006, CPU6) + Alias (C007, CPU7) + Alias (C008, CPU8) + } /* End _PR scope */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + AINT, 0x00000008, /* Index 4 */ + SINT, 0x00000008, /* Index 5 */ + , 0x00000008, /* Index 6 */ + AAUD, 0x00000008, /* Index 7 */ + AMOD, 0x00000008, /* Index 8 */ + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100) + Field (GRAM, ByteAcc, Lock, Preserve) + { + Offset (0x10), + FLG0, 8 + } + + Scope(\_SB) { + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + #include "acpi/routing.asl" + + Scope(\_SB) { + Method(CkOT, 0){ + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIND, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PING, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + \_SB.PCI0.SIOS (Arg0) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + \_SB.PCI0.SIOW (Arg0) + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + Method(_L00) { + //DBGO("\\_GPE\\_L00\n") + } + + /* General event 1 */ + Method(_L01) { + //DBGO("\\_GPE\\_L01\n") + } + + /* General event 2 */ + Method(_L02) { + //DBGO("\\_GPE\\_L02\n") + } + + /* General event 3 */ + Method(_L03) { + //DBGO("\\_GPE\\_L00\n") + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + Method(_L04) { + //DBGO("\\_GPE\\_L04\n") + } + + /* General event 5 */ + Method(_L05) { + //DBGO("\\_GPE\\_L05\n") + } + + /* _L06 General event 6 - Used for GPM6, moved to USB.asl */ + /* _L07 General event 7 - Used for GPM7, moved to USB.asl */ + + /* Legacy PM event */ + Method(_L08) { + //DBGO("\\_GPE\\_L08\n") + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + //DBGO("\\_GPE\\_L09\n") + Notify (\_TZ.TZ00, 0x80) + } + + /* Reserved */ + Method(_L0A) { + //DBGO("\\_GPE\\_L0A\n") + } + + /* USB controller PME# */ + Method(_L0B) { + //DBGO("\\_GPE\\_L0B\n") + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + Method(_L0C) { + //DBGO("\\_GPE\\_L0C\n") + } + + /* OtherTherm PME# */ + Method(_L0D) { + //DBGO("\\_GPE\\_L0D\n") + } + + /* _L0E GPM9 SCI event - Moved to USB.asl */ + + /* PCIe HotPlug event */ + Method(_L0F) { + //DBGO("\\_GPE\\_L0F\n") + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + //DBGO("\\_GPE\\_L10\n") + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + //DBGO("\\_GPE\\_L11\n") + } + + /* PCIe PME# event */ + Method(_L12) { + //DBGO("\\_GPE\\_L12\n") + } + + /* _L13 GPM0 SCI event - Moved to USB.asl */ + /* _L14 GPM1 SCI event - Moved to USB.asl */ + /* _L15 GPM2 SCI event - Moved to USB.asl */ + /* _L16 GPM3 SCI event - Moved to USB.asl */ + /* _L17 GPM8 SCI event - Moved to USB.asl */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + //DBGO("\\_GPE\\_L18\n") + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRb, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRc, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBRd, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* _L19 GPM4 SCI event - Moved to USB.asl */ + /* _L1A GPM5 SCI event - Moved to USB.asl */ + + /* Azalia SCI event */ + Method(_L1B) { + //DBGO("\\_GPE\\_L1B\n") + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + Method(_L1C) { + //DBGO("\\_GPE\\_L1C\n") + } + + /* GPM7 SCI event - Reassigned to _L07 */ + Method(_L1D) { + //DBGO("\\_GPE\\_L1D\n") + } + + /* GPIO2 or GPIO66 SCI event */ + Method(_L1E) { + //DBGO("\\_GPE\\_L1E\n") + } + + /* _L1F SATA SCI event - Moved to sata.asl */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + #include <arch/x86/acpi/globutil.asl> /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) //assigned when update_ssdt() + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ + + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBRb) { + Name(_ADR, 0x000b0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSb) } /* APIC mode */ + Return (PSb) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRb */ + + Device(PBRc) { + Name(_ADR, 0x000c0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSc) } /* APIC mode */ + Return (PSc) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRc */ + + Device(PBRd) { + Name(_ADR, 0x000d0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSd) } /* APIC mode */ + Return (PSd) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRd */ + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00130001) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130003) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00130004) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00130005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device (PS2M) { + Name (_HID, EisaId ("PNP0F13")) + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x00, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x00, 0x01) + IRQNoFlags () {12} + }) + Method (_STA, 0, NotSerialized) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + } + + Device (PS2K) { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) { + And (FLG0, 0x04, Local0) + If (LEqual (Local0, 0x04)) { + Return (0x0F) + } Else { + Return (0x00) + } + } + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x00, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x00, 0x01) + IRQNoFlags () {1} + }) + } + +#if 0 //acpi_create_hpet + Device(HPET) { + Name(_HID,EISAID("PNP0103")) + Name(CRS, ResourceTemplate() { + IRQNoFlags () {0} + IRQNoFlags () {2} + IRQNoFlags () {8} + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, MNT) /* 1kb reserved space */ + }) + Method(_STA, 0, NotSerialized) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0, NotSerialized) { + CreateDwordField(CRS, ^MNT._BAS, HPT) + Store(HPBA, HPT) + Return(CRS) + } + } /* End Device(_SB.PCI0.LIBR.HPET) */ +#endif + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + /* ITE8718 Support */ + OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8718 MB PnP Mode */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) /* 8718 magic number */ + } + /* Exit the 8718 MB PnP Mode */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB700 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8718F\n") */ + + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } + + Name (CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,,) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x03AF, // Range Maximum + 0x0000, // Translation Offset + 0x03B0, // Length + ,, , TypeStatic) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x03E0, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0918, // Length + ,, , TypeStatic) + + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x03B0, // Range Minimum + 0x03BB, // Range Maximum + 0x0000, // Translation Offset + 0x000C, // Length + ,, , TypeStatic) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x03C0, // Range Minimum + 0x03DF, // Range Maximum + 0x0000, // Translation Offset + 0x0020, // Length + ,, , TypeStatic) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) // VGA memory space + + Memory32Fixed (ReadOnly, + 0xE0000000, // Address Base + 0x10000000, // Address Length, (1MB each Bus, 256 Buses by default) + MMIO) + }) + + Method (_CRS, 0, NotSerialized) + { + CreateDWordField (CRS, \_SB.PCI0.MMIO._BAS, BAS1) + CreateDWordField (CRS, \_SB.PCI0.MMIO._LEN, LEN1) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, BAS1) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, LEN1) + //DBGO(TOM1) + + Return (CRS) + } + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + *} + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +} +/* End of ASL file */ diff --git a/src/mainboard/supermicro/h8scm/fadt.c b/src/mainboard/supermicro/h8scm/fadt.c new file mode 100644 index 0000000..0c63162 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/fadt.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include "Platform.h" /*sb700 platform header*/ + +#ifndef ACPI_BLK_BASE + #define ACPI_BLK_BASE PM1_EVT_BLK_ADDRESS +#endif + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "ACPI_BLK_BASE: 0x%04x\n", ACPI_BLK_BASE); + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "AMD ", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, PM1_CNT_BLK_ADDRESS); /* set SCI_EN */ + fadt->pm1a_evt_blk = PM1_EVT_BLK_ADDRESS; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = PM1_CNT_BLK_ADDRESS; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->pm_tmr_blk = PM1_TMR_BLK_ADDRESS; + fadt->gpe0_blk = GPE0_BLK_ADDRESS; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = PM1_EVT_BLK_ADDRESS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK_ADDRESS; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = PM1_TMR_BLK_ADDRESS; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = GPE0_BLK_ADDRESS; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} + diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c new file mode 100644 index 0000000..8c31cbf --- /dev/null +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#include "agesawrapper.h" +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif + + +/* Global variables for MB layouts and these will be shared by irqtable mptable + * and acpi_tables busnum is default. + */ +u8 bus_isa; +u8 bus_sp5100[2]; +u8 bus_sr5650[14]; + + +u32 bus_type[256]; + +u32 sbdn_sr5650; +u32 sbdn_sp5100; + +static u32 get_bus_conf_done = 0; + + +void get_bus_conf(void) +{ + u32 status; + + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + + get_bus_conf_done = 1; + + /* + * This is the call to AmdInitLate. It is really in the wrong place, conceptually, + * but functionally within the coreboot model, this is the best place to make the + * call. The logically correct place to call AmdInitLate is after PCI scan is done, + * after the decision about S3 resume is made, and before the system tables are + * written into RAM. The routine that is responsible for writing the tables is + * "write_tables", called near the end of "hardwaremain". There is no platform + * specific entry point between the S3 resume decision point and the call to + * "write_tables", and the next platform specific entry points are the calls to + * the ACPI table write functions. The first of ose would seem to be the right + * place, but other table write functions, e.g. the PIRQ table write function, are + * called before the ACPI tables are written. This routine is called at the beginning + * of each of the write functions called prior to the ACPI write functions, so this + * becomes the best place for this call. + */ + status = agesawrapper_amdinitlate(); + if(status) { + printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status); + } + + sbdn_sp5100 = 0; + + for (i = 0; i < 0; i++) { + bus_sp5100[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { + bus_sr5650[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_sr5650[0] = 0; + bus_sp5100[0] = bus_sr5650[0]; + + /* sp5100 */ + dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + + if (dev) { + bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sp5100[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* sr5650 */ + for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { + dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); + if (dev) { + bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_sr5650[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_sr5650[i]] = 1; /* PCI bus. */ + } + } + } + +/* + for (i = 0; i < 4; i++) { + dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i)); + if (dev) { + bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + } + } + for (j = bus_sp5100[2]; j < bus_isa; j++) + bus_type[j] = 1; +*/ + + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); + sb_Late_Post(); +#endif +} diff --git a/src/mainboard/supermicro/h8scm/irq_tables.c b/src/mainboard/supermicro/h8scm/irq_tables.c new file mode 100644 index 0000000..11e5256 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/irq_tables.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <cpu/amd/amdfam10_sysconf.h> + + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_sp5100[2]; +extern unsigned long sbdn_sp5100; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sp5100[0]; + pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + + + slot_num++; + + + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; + +} diff --git a/src/mainboard/supermicro/h8scm/mainboard.c b/src/mainboard/supermicro/h8scm/mainboard.c new file mode 100644 index 0000000..f6ce547 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/mainboard.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <boot/tables.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <NbPlatform.h> +#include "chip.h" + +void set_pcie_dereset(void *nbconfig); +void set_pcie_reset(void *nbconfig); + +/** + * + */ +void set_pcie_reset(void *nbconfig) +{ +} + +/** + * Mainboard specific RD890 CIMx callback + * Release Resets to PCIe Links + * For Both SR56X0 chips, PCIE_RESET_GPIO1 to reset pcie + */ +void set_pcie_dereset(void *nbconfig) +{ + //u32 nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + u32 i; + u32 val; + u32 nb_addr; + + val = 0x00000007UL; + AMD_NB_CONFIG_BLOCK *pConfig = (AMD_NB_CONFIG_BLOCK*)nbconfig; + for (i = 0; i < MAX_NB_COUNT; i ++) { + nb_addr = pConfig->Northbridges[i].NbPciAddress.AddressValue | NB_HTIU_INDEX; + LibNbPciIndexRMW(nb_addr, + NB_HTIU_REGA8, + AccessS3SaveWidth32, + ~val, + val, + &(pConfig->Northbridges[i])); + } +} + + +/************************************************* + * enable the dedicated function in h8scm board. + *************************************************/ +static void h8scm_enable(device_t dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); +} + +#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1) +int add_mainboard_resources(struct lb_memory *mem) +{ + return 0; +} +#endif + +struct chip_operations mainboard_ops = { + CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER " Mainboard") + .enable_dev = h8scm_enable, +}; diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c new file mode 100644 index 0000000..61a7bd4 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/amdfam10_sysconf.h> + +extern u8 bus_sr5650[14]; +extern u8 bus_sp5100[2]; +extern u32 bus_type[256]; +extern u32 sbdn_sr5650; +extern u32 sbdn_sp5100; +extern u8 bus_isa; + + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + u32 apicid_sp5100; + u32 apicid_sr5650; + device_t dev; + u32 dword; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + mptable_init(mc, LOCAL_APIC_ADDR); + + smp_write_processors(mc); + get_bus_conf(); + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * AGESA v5 Apply apic enumeration rules + * For systems with >= 16 APICs, put the IO-APICs at 0..n and + * put the local-APICs at m..z + * For systems with < 16 APICs, put the Local-APICs at 0..n and + * put the IO-APICs at (n + 1)..z + */ +#if CONFIG_MAX_CPUS >= 16 + apicid_sp5100 = 0x0; +#else + apicid_sp5100 = CONFIG_MAX_CPUS + 1 +#endif + apicid_sr5650 = apicid_sp5100 + 1; + + dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + if (dev) { + /* Set SP5100 IOAPIC ID */ + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sp5100, 0x20, dword); + +#ifdef UNUSED_CODE + u8 byte; + /* Initialize interrupt mapping */ + /* aza */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= 0; /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + /* SATA */ + dword = pci_read_config32(dev, 0xAC); + dword &= ~(7 << 26); + dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ + /* dword |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xAC, dword); +#endif + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + + /* Set RS5650 IOAPIC ID */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) { + pci_write_config32(dev, 0xF8, 0x1); + dword = pci_read_config32(dev, 0xFC) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sr5650, 0x20, dword); + } + + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sp5100, (pin)) + + /* SMBUS */ + //PCI_INT(0x0, 0x14, 0x0, 0x10); //not generate interrupt, 3Ch hardcoded to 0 + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x2, 0x10); + + /* USB */ + /* OHCI0, OHCI1 hard-wired to 01h, corresponding to using INTA# */ + /* EHCI hard-wired to 02h, corresponding to using INTB# */ + /* USB1 */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* OHCI0 Port 0~2 */ + PCI_INT(0x0, 0x12, 0x1, 0x10); /* OHCI1 Port 3~5 */ + PCI_INT(0x0, 0x12, 0x2, 0x11); /* EHCI Port 0~5 */ + + /* USB2 */ + PCI_INT(0x0, 0x13, 0x0, 0x10); /* OHCI0 Port 6~8 */ + PCI_INT(0x0, 0x13, 0x1, 0x10); /* OHCI1 Port 9~11 */ + PCI_INT(0x0, 0x13, 0x2, 0x11); /* EHCI Port 6~11 */ + + /* USB3 EHCI hard-wired to 03h, corresponding to using INTC# */ + PCI_INT(0x0, 0x14, 0x5, 0x12); /* OHCI0 Port 12~13 */ + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG + + /* on board NIC & Slot PCIE. */ + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); + */ + + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ + //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sp5100[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sp5100[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sp5100[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sp5100[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sp5100[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sp5100[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sp5100[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sp5100[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sp5100[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sp5100[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sp5100[1], 0x7, 0x3, 0x15); + + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/supermicro/h8scm/platform_cfg.h b/src/mainboard/supermicro/h8scm/platform_cfg.h new file mode 100644 index 0000000..bbc4ad7 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/platform_cfg.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _PLATFORM_CFG_H_ +#define _PLATFORM_CFG_H_ + + +/* northbridge customize options */ +/** + * Max number of northbridges in the system + */ +#define MAX_NB_COUNT 1 //TODO: only 1 NB tested + +/** + * Enable check for PCIe endpoint to be ready for PCI enumeration. + * + */ +//#define EPREADY_WORKAROUND_DISABLED + +/** + * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. + * + */ +#define IOMMU_SUPPORT_DISABLE //TODO: enable it + +/** + * Disable server PCIe hotplug support. + */ + +//#define HOTPLUG_SUPPORT_DISABLED + +/** + * Disable support for device number remapping for PCIe portsserver PCIe hotplug support. + */ + +//#define DEVICE_REMAP_DISABLE + +#endif //_PLATFORM_CFG_H_ diff --git a/src/mainboard/supermicro/h8scm/platform_oem.c b/src/mainboard/supermicro/h8scm/platform_oem.c new file mode 100644 index 0000000..883cad1 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/platform_oem.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "AGESA.h" +#include "amdlib.h" +#include "Ids.h" +#include "heapManager.h" +#include "Filecode.h" + +#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE + + +/*---------------------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) +{ + //InitEarly->PlatformConfig.CoreLevelingMode = CORE_LEVEL_TWO; +} + diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.c b/src/mainboard/supermicro/h8scm/rd890_cfg.c new file mode 100644 index 0000000..7a947b3 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.c @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include <string.h> +#include <arch/ioapic.h> + +#ifndef __PRE_RAM__ +#include <device/device.h> +extern void set_pcie_reset(void *config); +extern void set_pcie_dereset(void *config); + +/** + * Platform dependent configuration at ramstage + */ +static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr) +{ + u16 i; + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr); + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* update the platform depentent configuration by devicetree */ + rd890_info = nb_dev->chip_info; + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} +#endif // __PRE_RAM__ + +/** + * @brief Entry point of Northbridge CIMx callout/CallBack + * + * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr); + * + * @param[in] u32 func Northbridge CIMx CallBackId + * @param[in] u32 data Northbridge Input Data. + * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer. + * + */ +static u32 rd890_callout_entry(u32 func, u32 data, void *config) +{ + u32 ret = 0; +#ifndef __PRE_RAM__ + device_t nb_dev = (device_t)data; +#endif + AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config; + + switch (func) { + case PHCB_AmdPortTrainingCompleted: + break; + + case PHCB_AmdPortResetDeassert: +#ifndef __PRE_RAM__ + set_pcie_dereset(config); +#endif + break; + + case PHCB_AmdPortResetAssert: +#ifndef __PRE_RAM__ + set_pcie_reset(config); +#endif + break; + + case PHCB_AmdPortResetSupported: + break; + case PHCB_AmdGeneratePciReset: + break; + case PHCB_AmdGetExclusionTable: + break; + case PHCB_AmdAllocateBuffer: + break; + case PHCB_AmdUpdateApicInterruptMapping: + break; + case PHCB_AmdFreeBuffer: + break; + case PHCB_AmdLocateBuffer: + break; + case PHCB_AmdReportEvent: + break; + case PHCB_AmdPcieAsmpInfo: + break; + + case CB_AmdSetNbPorConfig: + break; + case CB_AmdSetHtConfig: + /*TODO: different HT path and deempasis for each NB */ + nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES; + + break; + case CB_AmdSetPcieEarlyConfig: +#ifndef __PRE_RAM__ + nb_platform_config(nb_dev, nbConfigPtr); +#endif + break; + + case CB_AmdSetEarlyPostConfig: + break; + + case CB_AmdSetMidPostConfig: + nbConfigPtr->pNbConfig->IoApicBaseAddress = IO_APIC_ADDR; +#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu + /* SBIOS must alloc 16K memory for IOMMU MMIO */ + UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress + LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C, + AccessWidth32, + &MmcfgBarAddress, + nbConfigPtr); + MmcfgBarAddress &= ~0xf; + if (MmcfgBarAddress != 0) { + nbConfigPtr->IommuBaseAddress = MmcfgBarAddress; + } + nbConfigPtr->IommuBaseAddress = 0; //disable iommu +#endif + break; + + case CB_AmdSetLatePostConfig: + break; + + case CB_AmdSetRecoveryConfig: + break; + } + + return ret; +} + + +/** + * @brief North Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig) +{ + u16 i = 0; + PCI_ADDR PciAddress; + u32 val, sbNode, sbLink; + + if (!pConfig) { + return; + } + + memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK)); + for (i = 0; i < MAX_NB_COUNT; i++) { + pConfig->Northbridges[i].pNbConfig = &nbConfig[i]; + pConfig->Northbridges[i].pHtConfig = &htConfig[i]; + pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i]; + pConfig->Northbridges[i].ConfigPtr = &pConfig; + } + + /* Initialize all NB structures */ + AmdInitializer(pConfig); + + pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ + //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; + pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; + pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + + /* + * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. + * Always 0:0:0 on single NB platform. + */ + pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); + + /* Set HT path to NB by SbNode and SbLink */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbNode = (val >> 8) & 0x07; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64); + LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0])); + sbLink = (val >> 8) & 0x07; //assum ganged + pConfig->Northbridges[0].NbHtPath.NodeID = sbNode; + pConfig->Northbridges[0].NbHtPath.LinkID = sbLink; + //TODO: other NBs + +#ifndef __PRE_RAM__ + /* If temporrary MMIO enable set up CPU MMIO */ + for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) { + UINT32 MmioBase; + UINT32 LinkId; + UINT32 SubLinkId; + MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress; + if (MmioBase != 0) { + LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf; + SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0; + /* Set Limit */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84), + AccessWidth32, + 0x0, + ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6), + &(pConfig->Northbridges[i])); + /* Set Base */ + LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80), + AccessWidth32, + 0x0, + (MmioBase << 12) | 0x3, + &(pConfig->Northbridges[i])); + } + } +#endif +} + diff --git a/src/mainboard/supermicro/h8scm/rd890_cfg.h b/src/mainboard/supermicro/h8scm/rd890_cfg.h new file mode 100644 index 0000000..8f45019 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/rd890_cfg.h @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _RD890_CFG_H_ +#define _RD890_CFG_H_ + +#include "NbPlatform.h" + +/* platform dependent configuration default value */ + +/** + * Path from CPU to NB + * [0..7] - Node (0..8) + * [8..11] - Link (0..3) + * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. + */ +#ifndef DEFAULT_HT_PATH +#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1 +#define DEFAULT_HT_PATH {0x0, 0x3} +#endif +#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1 +#define DEFAULT_HT_PATH {0x0, 0x1} +#endif +#endif + +/** + * Bitmap of enabled ports on NB #0/1/2/3 + * Bit[0] - Reserved + * Bit[1] - Reserved + * Bit[2] - Enable PCIe port 2 + * Bit[3] - Enable PCIe port 3 + * Bit[4] - Enable PCIe port 4 + * Bit[5] - Enable PCIe port 5 + * Bit[6] - Enable PCIe port 2 + * Bit[7] - Enable PCIe port 7 + * Bit[8] - Reserved + * Bit[9] - Enable PCIe port 9 + * Bit[10]- Enable PCIe port 10 + * Bit[11]- Enable PCIe port 11 + * Bit[12]- Enable PCIe port 12 + * Bit[13]- Enable PCIe port 13 + * Example: + * port_enable = 0x14 + * Port 2 and 4 enabled for training/initialization + */ +#ifndef DEFAULT_PORT_ENABLE_MAP +#define DEFAULT_PORT_ENABLE_MAP 0x0014 +#endif + +/** + * Bitmap of ports that have slot or onboard device connected. + * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4) + * #define DEFAULT_PORT_FORCE_GEN1 0x604 + */ +#ifndef DEFAULT_PORT_FORCE_GEN1 +#define DEFAULT_PORT_FORCE_GEN1 0x0 +#endif + +/** + * Bitmap of ports that have server hotplug support + */ +#ifndef DEFAULT_HOTPLUG_SUPPORT +#define DEFAULT_HOTPLUG_SUPPORT 0x0 +#endif + +#ifndef DEFAULT_HOTPLUG_DESCRIPTOR +#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0} +#endif + +#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS +#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000 +#endif + +/** + * Default GPP1 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP1_CONFIG +#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP2 core configuraton on NB #0/1/2/3. + * 2 x8 slot, GFX_CONFIG_AABB + * 1 x16 slot, GFX_CONFIG_AAAA + */ +#ifndef DEFAULT_GPP2_CONFIG +#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB +#endif + +/** + * Default GPP3a core configuraton on NB #0/1/2/3. + * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1 + * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2 + * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3 + * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4 + * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5 + * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6 + */ +#ifndef DEFAULT_GPP3A_CONFIG +#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111 +#endif + + +/** + * Default HT Transmitter de-emphasis setting + */ +#ifndef DEFAULT_HT_DEEMPASIES +#define DEFAULT_HT_DEEMPASIES 0x3 +#endif + +/** + * Default APIC nterrupt base for IOAPIC + */ +#ifndef DEFAULT_APIC_INTERRUPT_BASE +#define DEFAULT_APIC_INTERRUPT_BASE 24 +#endif + + +#define DEFAULT_PLATFORM_CONFIG(name) \ + NB_PLATFORM_CONFIG name = { \ + DEFAULT_PORT_ENABLE_MAP, \ + DEFAULT_PORT_FORCE_GEN1, \ + DEFAULT_HOTPLUG_SUPPORT, \ + DEFAULT_HOTPLUG_DESCRIPTOR, \ + DEFAULT_TEMPMMIO_BASE_ADDRESS, \ + DEFAULT_GPP1_CONFIG, \ + DEFAULT_GPP2_CONFIG, \ + DEFAULT_GPP3A_CONFIG, \ + DEFAULT_HT_DEEMPASIES, \ + /*DEFAULT_HT_PATH,*/ \ + DEFAULT_APIC_INTERRUPT_BASE, \ + } + +/** + * Platform configuration + */ +typedef struct { + UINT16 PortEnableMap; ///< Bitmap of enabled ports + UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2 + UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug + UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors + UINT32 TemporaryMmio; ///< Temporary MMIO + UINT32 Gpp1Config; ///< Default PCIe GFX core configuration + UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration + UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration + UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level + // HT_PATH NbHtPath; ///< HT path to NB + UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC. +} NB_PLATFORM_CONFIG; + +/** + * Bridge CIMx configuration + */ +void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig); + +#endif //_RD890_CFG_H_ diff --git a/src/mainboard/supermicro/h8scm/reset.c b/src/mainboard/supermicro/h8scm/reset.c new file mode 100644 index 0000000..68a39f2 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/reset.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <reset.h> +#include <arch/io.h> /*inb, outb*/ +#include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ + +#define HT_INIT_CONTROL 0x6C +#define HTIC_BIOSR_Detect (1<<5) + +#if CONFIG_MAX_PHYSICAL_CPUS > 32 +#define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) +#else +#define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) +#endif + +static inline void set_bios_reset(void) +{ + u32 nodes; + u32 htic; + device_t dev; + int i; + + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; + for(i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 0); + htic = pci_read_config32(dev, HT_INIT_CONTROL); + htic &= ~HTIC_BIOSR_Detect; + pci_write_config32(dev, HT_INIT_CONTROL, htic); + } +} + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} + +//SbReset(); +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x06, 0x0cf9); +} + diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c new file mode 100644 index 0000000..d62a9d9 --- /dev/null +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <lib.h> +#include <reset.h> +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <arch/stages.h> +#include "cpu/x86/bist.h" +#include "cpu/x86/lapic/boot_cpu.c" +#include "agesawrapper.h" +#include "northbridge/amd/agesa/family10/reset_test.h" +#include <nb_cimx.h> +#include <sb_cimx.h> +#include "src/drivers/pc80/i8254.c" +#include "src/drivers/pc80/i8259.c" +#include "superio/nuvoton/wpcm450/wpcm450.h" +#include "superio/winbond/w83627dhg/w83627dhg.h" +#include <cpu/x86/cache.h> + +extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define DUMMY_DEV PNP_DEV(0x2e, 0) + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + + post_code(0x30); + agesawrapper_amdinitmmio(); + post_code(0x31); + + /* Halt if there was a built in self test failure */ + post_code(0x33); + report_bist_failure(bist); + + sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ + wpcm450_enable_dev(WPCM450_SP1, 0x164E, CONFIG_TTYS0_BASE); + sb7xx_51xx_disable_wideio(0); + post_code(0x34); + + uart_init(); + post_code(0x35); + console_init(); + + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + + post_code(0x37); + val = agesawrapper_amdinitreset(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); + } + + if (!cpu_init_detectedx && boot_cpu()) { + post_code(0x38); + /* + * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, + * Disable all Pcie Bridges to work around It. + */ + sr56x0_rd890_disable_pcie_bridge(); + post_code(0x39); + nb_Poweron_Init(); + post_code(0x3A); + sb_Poweron_Init(); + } + post_code(0x3B); + val = agesawrapper_amdinitearly(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); + } + + post_code(0x3C); + nb_Ht_Init(); + + post_code(0x3D); + /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + distinguish_cpu_resets(0); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + + post_code(0x40); + val = agesawrapper_amdinitpost(); + if (val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); + } else { + printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); + } + + post_code(0x41); + val = agesawrapper_amdinitenv(); + if(val) { + printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); + } + printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); + + post_code(0x42); + + /* Initialize i8259 pic */ + post_code(0x41); + setup_i8259 (); + + /* Initialize i8254 timers */ + post_code(0x42); + setup_i8254 (); + + post_code(0x50); + print_debug("Disabling cache as ram "); + disable_cache_as_ram(); + enable_cache(); + print_debug("done\n"); + + post_code(0x51); + copy_and_run(0); + + /* We will not return, Should never see this message and post code. */ + print_debug("should not be here -\n"); + post_code(0x54); +} + diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.c b/src/mainboard/supermicro/h8scm/sb700_cfg.c new file mode 100644 index 0000000..6de765c --- /dev/null +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <string.h> +#include <console/console.h> /* printk */ +#include "Platform.h" +#include "sb700_cfg.h" + + +/** + * @brief South Bridge CIMx configuration + * + * should be called before exeucte CIMx function. + * this function will be called in romstage and ramstage. + */ +void sb700_cimx_config(AMDSBCFG *sb_config) +{ + if (!sb_config) { + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - No sb_config.\n"); + return; + } + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - Start.\n"); + memset(sb_config, 0, sizeof(AMDSBCFG)); + + /* SB_POWERON_INIT */ + sb_config->StdHeader.Func = SB_POWERON_INIT; + + /* header */ + sb_config->StdHeader.pPcieBase = PCIEX_BASE_ADDRESS; + + /* static Build Parameters */ + sb_config->BuildParameters.BiosSize = BIOS_SIZE; + sb_config->BuildParameters.LegacyFree = LEGACY_FREE; + sb_config->BuildParameters.EcKbd = 0; + sb_config->BuildParameters.EcChannel0 = 0; + sb_config->BuildParameters.Smbus0BaseAddress = SMBUS0_BASE_ADDRESS; + sb_config->BuildParameters.Smbus1BaseAddress = SMBUS1_BASE_ADDRESS; + sb_config->BuildParameters.SioPmeBaseAddress = SIO_PME_BASE_ADDRESS; + sb_config->BuildParameters.WatchDogTimerBase = WATCHDOG_TIMER_BASE_ADDRESS; + sb_config->BuildParameters.SpiRomBaseAddress = SPI_BASE_ADDRESS; + + sb_config->BuildParameters.AcpiPm1EvtBlkAddr = PM1_EVT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPm1CntBlkAddr = PM1_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiPmTmrBlkAddr = PM1_TMR_BLK_ADDRESS; + sb_config->BuildParameters.CpuControlBlkAddr = CPU_CNT_BLK_ADDRESS; + sb_config->BuildParameters.AcpiGpe0BlkAddr = GPE0_BLK_ADDRESS; + sb_config->BuildParameters.SmiCmdPortAddr = SMI_CMD_PORT; + sb_config->BuildParameters.AcpiPmaCntBlkAddr = ACPI_PMA_CNT_BLK_ADDRESS; + + sb_config->BuildParameters.SataIDESsid = SATA_IDE_MODE_SSID; + sb_config->BuildParameters.SataRAIDSsid = SATA_RAID_MODE_SSID; + sb_config->BuildParameters.SataRAID5Ssid = SATA_RAID5_MODE_SSID; + sb_config->BuildParameters.SataAHCISsid = SATA_AHCI_SSID; + sb_config->BuildParameters.Ohci0Ssid = OHCI0_SSID; + sb_config->BuildParameters.Ohci1Ssid = OHCI1_SSID; + sb_config->BuildParameters.Ohci2Ssid = OHCI2_SSID; + sb_config->BuildParameters.Ohci3Ssid = OHCI3_SSID; + sb_config->BuildParameters.Ohci4Ssid = OHCI4_SSID; + sb_config->BuildParameters.Ehci0Ssid = EHCI0_SSID; + sb_config->BuildParameters.Ehci1Ssid = EHCI1_SSID; + sb_config->BuildParameters.SmbusSsid = SMBUS_SSID; + sb_config->BuildParameters.IdeSsid = IDE_SSID; + sb_config->BuildParameters.AzaliaSsid = AZALIA_SSID; + sb_config->BuildParameters.LpcSsid = LPC_SSID; + + sb_config->BuildParameters.HpetBase = HPET_BASE_ADDRESS; + + /* General */ + sb_config->Spi33Mhz = 1; + sb_config->SpreadSpectrum = 0; + sb_config->PciClk5 = 1; + sb_config->PciClks = 0x1F; + sb_config->ResetCpuOnSyncFlood = 1; // Do not reset CPU on sync flood + sb_config->TimerClockSource = 2; // Auto + sb_config->S3Resume = 0; + sb_config->RebootRequired = 0; + + /* HPET */ + sb_config->HpetTimer = HPET_TIMER; + + /* USB */ + sb_config->UsbIntClock = 0; // Use external clock + sb_config->Usb1Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 18 Func0 + sb_config->Usb1Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 18 Func1 + sb_config->Usb1Ehci = 1; //0:disable 1:enable Bus 0 Dev 18 Func2 + sb_config->Usb2Ohci0 = 1; //0:disable 1:enable Bus 0 Dev 19 Func0 + sb_config->Usb2Ohci1 = 1; //0:disable 1:enable Bus 0 Dev 19 Func1 + sb_config->Usb2Ehci = 1; //0:disable 1:enable Bus 0 Dev 19 Func2 + sb_config->Usb3Ohci = 1; //0:disable 1:enable Bus 0 Dev 20 Func5 + sb_config->UsbOhciLegacyEmulation = 1; //0:Enable 1:Disable + + sb_config->AcpiS1Supported = 1; + + /* SATA */ + sb_config->SataController = 1; + sb_config->SataClass = CONFIG_SATA_CONTROLLER_MODE; //0 native, 1 raid, 2 ahci + sb_config->SataSmbus = 0; + sb_config->SataAggrLinkPmCap = 1; + sb_config->SataPortMultCap = 1; + sb_config->SataClkAutoOff = 1; + sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary, 1 -IDE as secondary. + //TODO: set to secondary not take effect. + sb_config->SataIdeCombinedMode = 0; //1 IDE controlor exposed and combined mode enabled, 0 disabled + sb_config->SataEspPort = 0; + sb_config->SataClkAutoOffAhciMode = 1; + sb_config->SataHpcpButNonESP = 0; + sb_config->SataHideUnusedPort = 0; + + /* Azalia HDA */ + sb_config->AzaliaController = AZALIA_CONTROLLER; + sb_config->AzaliaPinCfg = AZALIA_PIN_CONFIG; + sb_config->AzaliaSdin0 = AZALIA_SDIN_PIN; + sb_config->pAzaliaOemCodecTablePtr = NULL; + +#ifndef __PRE_RAM__ + /* ramstage cimx config here */ + if (!sb_config->StdHeader.pCallBack) { + sb_config->StdHeader.pCallBack = sb700_callout_entry; + } + + //sb_config-> +#endif //!__PRE_RAM__ + printk(BIOS_DEBUG, "SB700 - Cfg.c - sb700_cimx_config - End.\n"); +} + diff --git a/src/mainboard/supermicro/h8scm/sb700_cfg.h b/src/mainboard/supermicro/h8scm/sb700_cfg.h new file mode 100644 index 0000000..aac61ec --- /dev/null +++ b/src/mainboard/supermicro/h8scm/sb700_cfg.h @@ -0,0 +1,237 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#ifndef _SB700_CFG_H_ +#define _SB700_CFG_H_ + +#include <stdint.h> + + +/** + * @def BIOS_SIZE_1M + * @def BIOS_SIZE_2M + * @def BIOS_SIZE_4M + * @def BIOS_SIZE_8M + */ +#define BIOS_SIZE_1M 0 +#define BIOS_SIZE_2M 1 +#define BIOS_SIZE_4M 3 +#define BIOS_SIZE_8M 7 + +/* In SB700, default ROM size is 1M Bytes, if your platform ROM + * bigger than 1M you have to set the ROM size outside CIMx module and + * before AGESA module get call. + */ +#ifndef BIOS_SIZE +#if CONFIG_COREBOOT_ROMSIZE_KB_1024 == 1 +#define BIOS_SIZE BIOS_SIZE_1M +#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#define BIOS_SIZE BIOS_SIZE_2M +#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#define BIOS_SIZE BIOS_SIZE_4M +#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#define BIOS_SIZE BIOS_SIZE_8M +#endif +#endif + +/** + * @def SPREAD_SPECTRUM + * @brief + * 0 - Disable Spread Spectrum function + * 1 - Enable Spread Spectrum function + */ +#define SPREAD_SPECTRUM 0 + +/** + * @def SB_HPET_TIMER + * @breif + * 0 - Disable hpet + * 1 - Enable hpet + */ +#define HPET_TIMER 1 + +/** + * @def USB_CONFIG + * @brief bit[0-6] used to control USB + * 0 - Disable + * 1 - Enable + * Usb Ohci1 Contoller (Bus 0 Dev 18 Func0) is define at BIT0 + * Usb Ehci1 Contoller (Bus 0 Dev 18 Func2) is define at BIT1 + * Usb Ohci2 Contoller (Bus 0 Dev 19 Func0) is define at BIT2 + * Usb Ehci2 Contoller (Bus 0 Dev 19 Func2) is define at BIT3 + * Usb Ohci3 Contoller (Bus 0 Dev 22 Func0) is define at BIT4 + * Usb Ehci3 Contoller (Bus 0 Dev 22 Func2) is define at BIT5 + * Usb Ohci4 Contoller (Bus 0 Dev 20 Func5) is define at BIT6 + */ +#define USB_CINFIG 0x7F + +/** + * @def PCI_CLOCK_CTRL + * @breif bit[0-4] used for PCI Slots Clock Control, + * 0 - disable + * 1 - enable + * PCI SLOT 0 define at BIT0 + * PCI SLOT 1 define at BIT1 + * PCI SLOT 2 define at BIT2 + * PCI SLOT 3 define at BIT3 + * PCI SLOT 4 define at BIT4 + */ +#define PCI_CLOCK_CTRL 0x1F + +/** + * @def SATA_CONTROLLER + * @breif INCHIP Sata Controller + */ +#ifndef SATA_CONTROLLER +#define SATA_CONTROLLER 1 +#endif + +/** + * @def SATA_MODE + * @breif INCHIP Sata Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_MODE +#define SATA_MODE NATIVE_IDE_MODE +#endif + +/** + * @breif INCHIP Sata IDE Controller Mode + */ +#define IDE_LEGACY_MODE 0 +#define IDE_NATIVE_MODE 1 + +/** + * @def SATA_IDE_MODE + * @breif INCHIP Sata IDE Controller Mode + * NOTE: DO NOT ALLOW SATA & IDE use same mode + */ +#ifndef SATA_IDE_MODE +#define SATA_IDE_MODE IDE_LEGACY_MODE +#endif + +/** + * @def EXTERNAL_CLOCK + * @brief 00/10: Reference clock from crystal oscillator via + * PAD_XTALI and PAD_XTALO + * + * @def INTERNAL_CLOCK + * @brief 01/11: Reference clock from internal clock through + * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL + */ +#define EXTERNAL_CLOCK 0x00 +#define INTERNAL_CLOCK 0x01 + +#define SATA_CLOCK_SOURCE EXTERNAL_CLOCK + +/** + * @def SATA_PORT_MULT_CAP_RESERVED + * @brief 1 ON, 0 0FF + */ +#define SATA_PORT_MULT_CAP_RESERVED 1 + + +/** + * @def AZALIA_AUTO + * @brief Detect Azalia controller automatically. + * + * @def AZALIA_DISABLE + * @brief Disable Azalia controller. + + * @def AZALIA_ENABLE + * @brief Enable Azalia controller. + */ +#define AZALIA_AUTO 0 +#define AZALIA_DISABLE 1 +#define AZALIA_ENABLE 2 + +/** + * @breif INCHIP HDA controller + */ +#ifndef AZALIA_CONTROLLER +#define AZALIA_CONTROLLER AZALIA_AUTO +#endif + +/** + * @def AZALIA_PIN_CONFIG + * @brief + * 0 - disable + * 1 - enable + */ +#ifndef AZALIA_PIN_CONFIG +#define AZALIA_PIN_CONFIG 1 +#endif + +/** + * @def AZALIA_SDIN_PIN + * @brief + * SDIN0 is define at BIT0 & BIT1 + * 00 - GPIO PIN + * 01 - Reserved + * 10 - As a Azalia SDIN pin + * SDIN1 is define at BIT2 & BIT3 + * SDIN2 is define at BIT4 & BIT5 + * SDIN3 is define at BIT6 & BIT7 + */ +#ifndef AZALIA_SDIN_PIN +//#define AZALIA_SDIN_PIN 0xAA +#define AZALIA_SDIN_PIN 0x2A +#endif + +/** + * @def GPP_CONTROLLER + */ +#ifndef GPP_CONTROLLER +#define GPP_CONTROLLER 1 +#endif + +/** + * @def GPP_CFGMODE + * @brief GPP Link Configuration + * four possible configuration: + * GPP_CFGMODE_X4000 + * GPP_CFGMODE_X2200 + * GPP_CFGMODE_X2110 + * GPP_CFGMODE_X1111 + */ +#ifndef GPP_CFGMODE +#define GPP_CFGMODE GPP_CFGMODE_X1111 +#endif + + +/** + * @brief South Bridge CIMx configuration + * + */ +void sb700_cimx_config(AMDSBCFG *sb_cfg); + +/** + * @brief Entry point of Southbridge CIMx callout + * + * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) + * + * @param[in] func Southbridge CIMx Function ID. + * @param[in] data Southbridge Input Data. + * @param[in] sb_cfg Southbridge configuration structure pointer. + * + */ +u32 sb700_callout_entry(u32 func, u32 data, void* sb_cfg); + +#endif //_SB700_CFG_H_

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New patch to review for coreboot: 1d6afe5 amd rd890 late.c: don't enable ports after pcie init.
by Siyuan Wang 28 Oct '12

28 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1640 -gerrit commit 1d6afe558dcff5a33c4ae655ba649cb2fb40e13e Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Sun Oct 28 18:16:19 2012 +0800 amd rd890 late.c: don't enable ports after pcie init. when the pcie init is finished, the pcie bridge with device is on and the pcie bridge without device is off. Now the code open pcie bridge according to devicetree.cb. this is not correct, because some pcie slots may not have device. in the rd890 enable, pcie init and post init is enough, and should only do once. Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/northbridge/amd/cimx/rd890/late.c | 115 ++++++++-------------------------- 1 file changed, 26 insertions(+), 89 deletions(-) diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 33da2b4..1a345a2 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -69,10 +69,7 @@ void nb_Late_Post_Init(void) static void rd890_enable(device_t dev) { u32 address = 0; - u32 mask; - u32 val; u32 devfn; - u32 port; AMD_NB_CONFIG *NbConfigPtr = NULL; u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ @@ -80,97 +77,37 @@ static void rd890_enable(device_t dev) NbConfigPtr = &(gConfig.Northbridges[nb_index]); devfn = dev->path.pci.devfn; - port = devfn >> 3; printk(BIOS_INFO, "rd890_enable "); printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", 0, (devfn >> 3), (devfn & 0x07), dev->enabled); - if (port != 0) { - if (dev->enabled) { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; - } else { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; + + /* we only do this once */ + if(devfn==0) { + /* CIMX configuration defualt initialize */ + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); } - } + /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree + * After this call EP are fully operational on particular NB + */ + nb_Pcie_Early_Init(); + + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Early_Post_Init(); - switch (port) { - case 0x0: /* Root Complex, and ClkConfig */ - - if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ - break; - } - - /* CIMX configuration defualt initialize */ - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - /* NOTE: not use LibNbCallBack */ - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); - } - /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ - nb_Pcie_Early_Init(); - break; - - case 0x2: /* Gpp1 Port0 */ - case 0x3: /* Gpp1 Port1 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x4: /* Gpp3a Port0 */ - case 0x5: /* Gpp3a Port1 */ - case 0x6: /* Gpp3a Port2 */ - case 0x7: /* Gpp3a Port3 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x8: /* SB ALink */ - mask = ~(1 << 6); - val = (dev->enabled ? 1 : 0) << 6; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x9: /* Gpp3a Port4 */ - case 0xa: /* Gpp3a Port5 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xb: /* Gpp2 Port0 */ - case 0xc: /* Gpp2 Port1 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xd: /* Gpp3b */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - - /* Init NB at Early Post */ - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Early_Post_Init();// - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Mid_Post_Init(); - nb_Pcie_Late_Init(); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Late_Post_Init(); - break; - - default: - printk(BIOS_INFO, "Buggy Device Tree\n"); - break; + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Mid_Post_Init(); + nb_Pcie_Late_Init(); + + if (gConfig.StandardHeader.CalloutPtr != NULL) { + gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); + } + nb_Late_Post_Init(); } }

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New patch to review for coreboot: bbfaf24 amd agesa family15 pci domain should scan bus from 0x18.0
by Siyuan Wang 28 Oct '12

28 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1639 -gerrit commit bbfaf24b04ed8964a785cd2092570e795dfdf265 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Sun Oct 28 18:06:40 2012 +0800 amd agesa family15 pci domain should scan bus from 0x18.0 there are 4 mainboards using agesa family15 code: supermicro h8scm and h8qgi, tyan s8226 and amd dinar. all of these boards's pci domain is start from 0x18.0. take h8scm as an example, pci devices from 0.0 to 0x14.5 is under 0x18.0. Now, the pci domain's scan bus function stats from 0.0. this would result to the pci devices be scanned twice. because when the function run to device 18.0, it will scan from 0.0 again. this issue would result to 2 problem: 1) pci device may be assigned two different pci address. if this happenned on vga device, coreboot may be not load vga bios correctly. 2) coreboot initializes rd890's io apic twice. so this patch scans from 0x18.0 and could resolve the problems above. Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 9 ++++++++- src/northbridge/amd/agesa/family15/northbridge.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index f297fc0..12a211f 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -846,7 +846,7 @@ static struct device_operations pci_domain_ops = { .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, .init = NULL, - .scan_bus = pci_domain_scan_bus, + .scan_bus = f15_pci_domain_scan_bus, #if CONFIG_MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, @@ -1143,3 +1143,10 @@ struct chip_operations northbridge_amd_agesa_family15_root_complex_ops = { CHIP_NAME("AMD FAM15 Root Complex") .enable_dev = root_complex_enable_dev, }; + +/* all family15's pci devices are under 0x18.0, so we search from dev 0x18 fun 0 */ +static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(dev->link_list, PCI_DEVFN(0x18, 0), 0xff, max); + return max; +} diff --git a/src/northbridge/amd/agesa/family15/northbridge.h b/src/northbridge/amd/agesa/family15/northbridge.h index 7606b32..cd9f83c 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.h +++ b/src/northbridge/amd/agesa/family15/northbridge.h @@ -22,5 +22,6 @@ static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; +static unsigned int f15_pci_domain_scan_bus(device_t dev, unsigned int max); #endif /* NORTHBRIDGE_AMD_AGESA_FAM15_H */

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Re: [coreboot] Gigabyte GA-6BXE CD-ROM
by Kevin O'Connor 28 Oct '12

28 Oct '12

On Sat, Oct 27, 2012 at 02:48:34PM +0300, Eino-Pekka Kanto wrote: > Hello! > > I burned coreboot to my Gigabyte 6bxe rev 1.9 motherboard, using > SeaBIOS as payload. Floppy drive didn't work (marked as WIP), but > otherwise it did support Voodoo 3dfx in AGP. 120Gb WD1200 drive also > worked, but Toshiba XM-6402B drive didn't. I tested it with Lubuntu > 8.04 CD-R (tested with that same drive in vendor BIOS and it worked). > The drive opens and closes but SeaBIOS doesn't boot it. > > SeaBIOS config: http://dpaste.com/818910/ > Coreboot config: http://dpaste.com/818909/ > > Coreboot and SeaBIOS logs from serial port (without any drives): [...] > No bootable device. Retrying in 60 seconds. > > > Ps. will there be floppy support soon for this motherboard? Are you trying to boot from a floppy drive? It's not clear from your report. SeaBIOS doesn't enable floppies on coreboot, because it has never been tested on real hardware. If you want to give it a test you could try applying this patch to the SeaBIOS code: --- a/src/floppy.c +++ b/src/floppy.c @@ -136,7 +136,7 @@ floppy_setup(void) dprintf(3, "init floppy drives\n"); if (CONFIG_COREBOOT) { - // XXX - disable floppies on coreboot for now. + addFloppy(0, 4); } else { u8 type = inb_cmos(CMOS_FLOPPY_DRIVE_TYPE); if (type & 0xf0) I really have no idea if it will work on real hardware. It certainly wont work with anything other than a 1.44Mbit 3.5" drive. -Kevin

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Re: [coreboot] problems with Gigabyte GA-MA785GM-US2H
by Peter Stuge 28 Oct '12

28 Oct '12

Anthoine Bourgeois wrote: > > Did you run the VGA BIOS in the coreboot emulator or did you make > > sure that only SeaBIOS would run it? Note that the default is > > coreboot, which I think is wrong. > > I'm not sure I understand the nuance coreboot by default tries to run option ROMs in an emulator. SeaBIOS runs option ROMs on bare metal. It is redundant and wrong to do both. It is a really bad error that coreboot defaults both to running ROMs *and* using SeaBIOS as default payload. The only thing that makes sense is to have only one. If SeaBIOS is available it should generally be taking care of option ROMs. > I followed the instruction on SeaBIOS page ( > http://www.coreboot.org/SeaBIOS#Adding_a_VGA_option_ROM) then I think > it's SeaBIOS who managed the VGABIOS. No. > But I didn't know who ran the VGABIOS really (emulator or SeaBIOS). > How can I check it ? All my config was default Then the configuration is wrong. Disable all the option ROM stuff under Chipset in coreboot menuconfig. Or use this: git clone http://review.coreboot.org/coreboot && cd coreboot && \ git fetch origin refs/changes/38/1638/1 && git checkout FETCH_HEAD > > > I pass radeon.modeset=0 to access a console and flash my rom to get > > > my old bios back. > > > > OK, so you did have graphics then? > > No, only the console worked, the screen froze when xorg started up. Console very much counts as working graphics. "not working graphics" means that the screen never shows anything. Start by fixing the redundant option ROM configuration. See if that helps at all. //Peter

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Re: [coreboot] problems with Gigabyte GA-MA785GM-US2H
by Peter Stuge 28 Oct '12

28 Oct '12

Anthoine Bourgeois wrote: > I tested the support of the Gigabyte GA-MA785GM-US2H. My main problem was > that the integrated radeon doesn't work even with the VGA bios image I > extracted from the official bios. Did you run the VGA BIOS in the coreboot emulator or did you make sure that only SeaBIOS would run it? Note that the default is coreboot, which I think is wrong. > I pass radeon.modeset=0 to access a console and flash my rom to get > my old bios back. OK, so you did have graphics then? Note that the kernel drivers are often unaware that there exists anything other than what the factory BIOS does, so when testing some graphics hardware together with coreboot you have to be prepared for things not working out of the box. If you fix it, maybe it will work out of the box for the next person. > Any idea on how this can append and how can change my MAC ? Sorry, don't know about that one. //Peter

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Re: [coreboot] Gigabyte GA-6BXE: floppy drive support
by Anders Jenbo 27 Oct '12

27 Oct '12

Hello Thank you for including me since I'm not on the list currently. My port was based on Gigabyte GA-6BXC witch also does not have floppy support, so the WIP status i basically just me intending to port it to GA-6BXE once it be implemented for GA-6BXC. I haven't worked actively on core boot for little over a year but still have both boards and would be willing to help test any progress you make. Anders Den 27-10-2012 14:39, Paul Menzel skrev: > Dear Eino-Pekka, > > > thank you for your message. > > Am Samstag, den 27.10.2012, 14:48 +0300 schrieb Eino-Pekka Kanto: > >> I burned coreboot to my Gigabyte 6bxe rev 1.9 motherboard, using >> SeaBIOS as payload. Floppy drive didn't work (marked as WIP), > […] > >> Ps. will there be floppy support soon for this motherboard? > The chances are pretty low, unless you do it. :/ > > Looking at the commit history > > $ git log --grep=6BXE > commit 96d8fef5d2151878d96f6b445ec1678a529b4001 > Author: Anders Jenbo <anders(a)jenbo.dk> > Date: Fri May 14 21:29:08 2010 +0000 > > ITE IT8671F: Add it8671f_48mhz_clkin(). > > This fixes serial console on GIGABYTE GA-6BXE. > > Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 > > commit 9d1c76f54c105a15f227183460ebe8d88cb719a7 > Author: Anders Jenbo <anders(a)jenbo.dk> > Date: Fri May 14 19:50:11 2010 +0000 > > Add initial support for the GIGABYTE GA-6BXE. > > Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> > Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> > > git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 > > Anders did the port and I am adding him as a recipient. Unfortunately > besides to the Wiki page [1] there is no note in the commit message, why > the floppy drive might not work. > > > Thanks and good luck, > > Paul > > > [1] http://www.coreboot.org/GIGABYTE_GA-6BXE >

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coreboot October 2012