coreboot October 2012

coreboot@coreboot.org

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312 discussions

Patch set updated for coreboot: 5cb3097 Persimmon: disable the unconnected Full-Speed USB port
by Dave Frodin 31 Oct '12

31 Oct '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1660 -gerrit commit 5cb3097c6a1c34073f69190c2a9688531be9ffdc Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Oct 31 08:51:01 2012 -0600 Persimmon: disable the unconnected Full-Speed USB port Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/persimmon/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index da81dc3..178fd76 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -82,7 +82,7 @@ chip northbridge/amd/agesa/family14/root_complex end # f81865f end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 + device pci 14.5 off end # USB 2 device pci 15.0 off end # PCIe PortA device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC

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New patch to review for coreboot: 31760c3 Persimmon: turn off the unused full speed USB port
by Dave Frodin 31 Oct '12

31 Oct '12

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1660 -gerrit commit 31760c31c6593393d0c5d8d78e6fc6189ff8ec0e Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Oct 31 08:51:01 2012 -0600 Persimmon: turn off the unused full speed USB port Change-Id: Ia3824059a38412896ed2be0c8714018b2291c9f8 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/mainboard/amd/persimmon/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index da81dc3..178fd76 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -82,7 +82,7 @@ chip northbridge/amd/agesa/family14/root_complex end # f81865f end #LPC device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 + device pci 14.5 off end # USB 2 device pci 15.0 off end # PCIe PortA device pci 15.1 off end # PCIe PortB device pci 15.2 off end # PCIe PortC

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New patch to review for coreboot: d43978c AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
by Siyuan Wang 31 Oct '12

31 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1659 -gerrit commit d43978cc03374c88ffd97a83e6e598af2207095c Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Wed Oct 31 15:39:51 2012 +0800 AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU each G34 socket has two node. previous lapic algorithm is written for the CPU which has one node per socket. I test the code on h8qgi with 4 family 15 CPUs(8 cores per CPU). the topology is: socket 0 --> Node 0, Node 1 socket 2 --> Node 2, Node 3 socket 1 --> Node 4, Node 5 socket 3 --> Node 6, Node 7 each node has 4 cores. I change the code according to this topology. Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/northbridge/amd/agesa/family15/northbridge.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 12a211f..78986e4 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -1068,7 +1068,11 @@ static u32 cpu_bus_scan(device_t dev, u32 max) lapicid_start = (lapicid_start + 1) * core_max; printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start); } - u32 apic_id = (i * core_max) + j + lapicid_start; +#if CONFIG_CPU_AMD_SOCKET_G34 + u32 apic_id = (i / 2 * core_max) + j + lapicid_start + (i % 2 ? siblings + 1 : 0); +#else + u32 apic_id = (i * core_max) + j + lapicid_start; +#endif printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n", i, j, apic_id);

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Re: [coreboot] Modern motherboard support - ASUS SABERTOOTH 990FX R2.0?
by František Kučera 30 Oct '12

30 Oct '12

Dne 23.10.2012 10:48, Paul Menzel napsal(a): > Dear František, > > > Am Dienstag, den 23.10.2012, 09:52 +0200 schrieb František Kučera: > >> I am interested in building high performance workstation completely based >> on free software -- beside free GNU/Linux distribution I want to use >> Coreboot. > welcome! > > Please note, although strange in some languages that coreboot is spelled > all lowercase. OK, coreboot :-) >> Important for me is virtualization support including IOMMU/VT-d. >> Both Intel and AMD are good form me, but AMD seems to be a better choice, >> isn't it? > AMD directly contributes code. > >> I want to build this computer for myself and later may be offer same model >> to others. >> The ASUS M5A88-V looks good and, according to wiki, is supported, but this >> board is discontinued and even if I can buy one somewhere, the availability >> is problem. >> Could you please recommend me some more modern board good for >> experimenting with Coreboot? >> What about some board with AMD 990FX e.g. ASUS SABERTOOTH 990FX R2.0? >> I have seen that it is supported by Flashrom, so the first step is done. > Please take a look at the *whole* thread »F2A85-V PRO as good target?« > on the coreboot list [1]. If you want to reply to it, make sure to > import the mbox of the archive from [2] to keep the threading. Thanks for the link, I found here some inspiration. I am thinking about AMD FX-8350, so I need an AM3+ board. According to some pictures I found, Sabertooth 990 FX seems to have ITE IT8721F, which should be - al least partially - supported: http://www.coreboot.org/pipermail/coreboot/2011-September/066483.html (but I didn't find it in Supported Chipsets and Devices in wiki) > Thanks, > > Paul Also thanks. I will probably buy this board (if I don't find better one) and post more info about it. František > [1] http://www.coreboot.org/pipermail/coreboot/2012-October/071705.html > [2] http://www.coreboot.org/pipermail/coreboot/

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Patch merged into coreboot/master: f87b008 Add support for socket LGA775
by gerrit＠coreboot.org 30 Oct '12

30 Oct '12

the following patch was just integrated into master: commit f87b0084fb4ffad4cafb9df88a2e65e291b8e556 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Sat Oct 13 13:15:04 2012 +0200 Add support for socket LGA775 Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Tue Oct 30 17:55:57 2012, giving +2 See http://review.coreboot.org/1581 for details. -gerrit

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New patch to review for coreboot: 3fcc0bc Overhaul speedstep code
by Patrick Georgi 30 Oct '12

30 Oct '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1658 -gerrit commit 3fcc0bc02004f773b9bee1271bbb5ce72e64ee3a Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Oct 2 11:11:42 2012 +0200 Overhaul speedstep code This adds proper support for turbo and super-low-frequency modes. Calculation of the p-states has been rewritten and moved into an extra file speedstep.c so it can be used for non-acpi stuff like EMTTM table generation. It has been tested with a Core2Duo T9400 (Penryn) processor. Change-Id: I5f7104fc921ba67d85794254f11d486b6688ecec Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/cpu/intel/speedstep/Makefile.inc | 2 +- src/cpu/intel/speedstep/acpi.c | 195 +++++++++++++++++++++-------------- src/cpu/intel/speedstep/speedstep.c | 171 ++++++++++++++++++++++++++++++ src/include/cpu/intel/speedstep.h | 74 +++++++++++++ 4 files changed, 361 insertions(+), 81 deletions(-) diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc index c717a33..753dbcd 100644 --- a/src/cpu/intel/speedstep/Makefile.inc +++ b/src/cpu/intel/speedstep/Makefile.inc @@ -1 +1 @@ -ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 070f8d5..910055d 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2009 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -28,7 +29,18 @@ #include <cpu/intel/speedstep.h> #include <device/device.h> -// XXX: PSS table values for power consumption are for Merom only +/** + * @brief Returns c-state entries for this system + * + * This function is usually overwritten in mainboard code. + * + * @return Number of c-states *entries will point to. + */ +int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries + __attribute__((unused))) +{ + return 0; +} static int determine_total_number_of_cores(void) { @@ -47,110 +59,133 @@ static int determine_total_number_of_cores(void) return count; } +/** + * @brief Returns three times the FSB clock in MHz + * + * The result of calculations with the returned value shall be divided by 3. + * This helps to avoid rounding errors. + */ static int get_fsb(void) { const u32 fsbcode = rdmsr(0xcd).lo & 7; switch (fsbcode) { - case 0: return 266; - case 1: return 133; - case 2: return 200; - case 3: return 166; - case 4: return 333; - case 5: return 100; - case 6: return 400; + case 0: return 800; /* / 3 == 266 */ + case 1: return 400; /* / 3 == 133 */ + case 2: return 600; /* / 3 == 200 */ + case 3: return 500; /* / 3 == 166 */ + case 4: return 1000; /* / 3 == 333 */ + case 5: return 300; /* / 3 == 100 */ + case 6: return 1200; /* / 3 == 400 */ } - printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n"); - return 200; + printk(BIOS_WARNING, + "Warning: No supported FSB frequency. Assuming 200MHz\n"); + return 600; } -int __attribute__((weak)) get_cst_entries(acpi_cstate_t **entries __attribute__((unused))) +static int gen_pstate_entries(const sst_table_t *const pstates, + const int cpuID, const int cores_per_package, + const uint8_t coordination) { - return 0; + int i; + int len, len_ps; + int frequency; + + len = acpigen_write_empty_PCT(); + len += acpigen_write_PSD_package( + cpuID, cores_per_package, coordination); + len += acpigen_write_name("_PSS"); + + const int fsb3 = get_fsb(); + const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO( + pstates->states[pstates->num_states - 1]); + const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(pstates->states[0]); + printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", + (min_ratio2 * fsb3) + / (pstates->states[pstates->num_states - 1].is_slfm ? 12 : 6), + (max_ratio2 * fsb3) / 6); + + printk(BIOS_DEBUG, "adding %x P-States between " + "busratio %x and %x, ""incl. P0\n", + pstates->num_states, min_ratio2 / 2, max_ratio2 / 2); + len_ps = acpigen_write_package(pstates->num_states); + for (i = 0; i < pstates->num_states; ++i) { + const sst_state_t *const pstate = &pstates->states[i]; + /* Report frequency of turbo mode as that of HFM + 1. */ + if (pstate->is_turbo) + frequency = (SPEEDSTEP_DOUBLE_RATIO( + pstates->states[i + 1]) * fsb3) / 6 + 1; + /* Super-LFM runs at half frequency. */ + else if (pstate->is_slfm) + frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/12; + else + frequency = (SPEEDSTEP_DOUBLE_RATIO(*pstate)*fsb3)/6; + len_ps += acpigen_write_PSS_package( + frequency, pstate->power, 0, 0, + SPEEDSTEP_ENCODE_STATE(*pstate), + SPEEDSTEP_ENCODE_STATE(*pstate)); + } + len_ps--; + acpigen_patch_len(len_ps); + + len += acpigen_write_PPC(0); + + len += len_ps; + + return len; } +/** + * @brief Generate ACPI entries for Speedstep for each cpu + */ void generate_cpu_entries(void) { - int len_pr, len_ps; + int len_pr; int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6; - msr_t msr; int totalcores = determine_total_number_of_cores(); int cores_per_package = (cpuid_ebx(1)>>16) & 0xff; - int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout - int count; - acpi_cstate_t *cst_entries; + int numcpus = totalcores/cores_per_package; /* This assumes that all + CPUs share the same + layout. */ + int num_cstates; + acpi_cstate_t *cstates; + sst_table_t pstates; + uint8_t coordination; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); - printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); + num_cstates = get_cst_entries(&cstates); + speedstep_gen_pstates(&pstates); + if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067) + /* For Penryn use HW_ALL. */ + coordination = HW_ALL; + else + /* Use SW_ANY as that was the default. */ + coordination = SW_ANY; - for (cpuID=1; cpuID <=numcpus; cpuID++) { + for (cpuID = 0; cpuID < numcpus; ++cpuID) { for (coreID=1; coreID<=cores_per_package; coreID++) { if (coreID>1) { pcontrol_blk = 0; plen = 0; } + + /* Generate processor \_PR.CPUx. */ len_pr = acpigen_write_processor( - (cpuID - 1) * cores_per_package + coreID - 1, pcontrol_blk, plen); - len_pr += acpigen_write_empty_PCT(); - len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY); - if ((count = get_cst_entries(&cst_entries)) > 0) - len_pr += acpigen_write_CST_package(cst_entries, count); - len_pr += acpigen_write_name("_PSS"); - - int max_states=8; - int busratio_step=2; - msr = rdmsr(IA32_PERF_STS); - int busratio_min=(msr.lo >> 24) & 0x1f; - int busratio_max=(msr.hi >> (40-32)) & 0x1f; - int vid_min=msr.lo & 0x3f; - msr = rdmsr(IA32_PLATFORM_ID); - int vid_max=msr.lo & 0x3f; - int clock_max=get_fsb()*busratio_max; - int clock_min=get_fsb()*busratio_min; - printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max); -#define MEROM_MIN_POWER 16000 -#define MEROM_MAX_POWER 35000 - int power_max=MEROM_MAX_POWER; - int power_min=MEROM_MIN_POWER; - - int num_states=(busratio_max-busratio_min)/busratio_step; - while (num_states > max_states-1) { - busratio_step <<= 1; - num_states >>= 1; - } - printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", - num_states+1, busratio_min, busratio_max); - int vid_step=(vid_max-vid_min)/num_states; - int power_step=(power_max-power_min)/num_states; - int clock_step=(clock_max-clock_min)/num_states; - len_ps = acpigen_write_package(num_states + 1); /* For Super LFM, this must - be increases by another one. */ - len_ps += acpigen_write_PSS_package( - clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, - (busratio_max << 8) | vid_max /*control*/, - (busratio_max << 8) | vid_max /*status*/); - - int current_busratio=busratio_min+((num_states-1)*busratio_step); - int current_vid=vid_min+((num_states-1)*vid_step); - int current_power=power_min+((num_states-1)*power_step); - int current_clock=clock_min+((num_states-1)*clock_step); - int i; - for (i=0;i<num_states; i++) { - len_ps += acpigen_write_PSS_package( - current_clock /*mhz*/, current_power /*mW*/, - 0 /*lat1*/, 0 /*lat2*/, - (current_busratio << 8) | current_vid /*control*/, - (current_busratio << 8) | current_vid /*status*/); - current_busratio -= busratio_step; - current_vid -= vid_step; - current_power -= power_step; - current_clock -= clock_step; - } - len_ps--; - acpigen_patch_len(len_ps); - len_pr += acpigen_write_PPC(0); - len_pr += len_ps; + cpuID * cores_per_package + coreID - 1, + pcontrol_blk, plen); + + /* Generate p-state entries. */ + len_pr += gen_pstate_entries(&pstates, cpuID, + cores_per_package, coordination); + + /* Generate c-state entries. */ + if (num_cstates > 0) + len_pr += acpigen_write_CST_package( + cstates, num_cstates); + len_pr--; acpigen_patch_len(len_pr); } } } - diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c new file mode 100644 index 0000000..e5509ec --- /dev/null +++ b/src/cpu/intel/speedstep/speedstep.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <console/console.h> +#include <cpu/intel/speedstep.h> + +/** + * @brief Gather speedstep limits for current processor + * + * At least power limits are processor type specific. Penryn introduced half + * steps in bus ratios. Don't know about Atom processors. + */ +static void speedstep_get_limits(sst_params_t *const params) +{ + msr_t msr; + + const uint16_t cpu_id = (cpuid_eax(1) >> 4) & 0xffff; + const uint32_t state_mask = + /* Penryn supports non integer (i.e. half) ratios. */ + ((cpu_id == 0x1067) ? SPEEDSTEP_RATIO_NONINT : 0) + | SPEEDSTEP_RATIO_VALUE_MASK | SPEEDSTEP_VID_MASK; + + /* Initialize params to zero. */ + memset(params, '\0', sizeof(*params)); + + /* Read Super-LFM parameters. */ + if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and + enabled bits */ + msr = rdmsr(MSR_FSB_CLOCK_VCC); + params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + params->slfm.dynfsb = 1; + params->slfm.is_slfm = 1; + } + + /* Read normal minimum parameters. */ + msr = rdmsr(MSR_THERM2_CTL); + params->min = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + + /* Read normal maximum parameters. */ + msr = rdmsr(IA32_PLATFORM_ID); + params->max = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); + + /* Read turbo parameters. */ + msr = rdmsr(MSR_FSB_CLOCK_VCC); + if ((msr.hi & (1 << (63 - 32))) && + /* supported and */ + !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { + /* not disabled */ + params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); + params->turbo.is_turbo = 1; + } + + /* Set power limits by processor type. */ + /* Defined values match the normal voltage versions only. But + they are only a hint for OSPM, so this should not hurt much. */ + switch (cpu_id) { + case 0x1067: + /* Penryn */ + params->slfm.power = SPEEDSTEP_SLFM_POWER_PENRYN; + params->min.power = SPEEDSTEP_MIN_POWER_PENRYN; + params->max.power = SPEEDSTEP_MAX_POWER_PENRYN; + params->turbo.power = SPEEDSTEP_TURBO_POWER_PENRYN; + break; + default: + /* Use Merom values by default (as before). */ + params->slfm.power = SPEEDSTEP_SLFM_POWER_MEROM; + params->min.power = SPEEDSTEP_MIN_POWER_MEROM; + params->max.power = SPEEDSTEP_MAX_POWER_MEROM; + params->turbo.power = SPEEDSTEP_TURBO_POWER_MEROM; + break; + } +} + +/** + * @brief Generate full p-states table from processor parameters + * + * This is generic code and should work at least for Merom and Penryn + * processors. It is used to generate acpi tables and configure EMTTM. + */ +void speedstep_gen_pstates(sst_table_t *const table) +{ + sst_params_t params; + /* Gather speedstep limits. */ + speedstep_get_limits(&params); + + + /*\ First, find the number of normal states: \*/ + + /* Calculate with doubled values to work + around non-integer (.5) bus ratios. */ + const int power_diff2 = (params.max.power - params.min.power) * 2; + const int vid_diff2 = (params.max.vid - params.min.vid) * 2; + const int max_ratio2 = SPEEDSTEP_DOUBLE_RATIO(params.max); + const int min_ratio2 = SPEEDSTEP_DOUBLE_RATIO(params.min); + const int ratio_diff2 = max_ratio2 - min_ratio2; + /* Calculate number of normal states (LFM to HFM, min to max). */ + /* Increase step size, until all states fit into the table. + (Note: First try should always work, if + SPEEDSTEP_MAX_NORMAL_STATES is set correctly.) */ + int states, step2 = 0; + do { + step2 += 2 * 2; /* Must be a multiple of 2 (doubled). */ + states = ratio_diff2 / step2 + 1; + } while (states > SPEEDSTEP_MAX_NORMAL_STATES); + if (step2 > 4) + printk(BIOS_INFO, "Enhanced Speedstep processor with " + "more than %d possible p-states.\n", + SPEEDSTEP_MAX_NORMAL_STATES); + if (states < 2) /* Report at least two normal states. */ + states = 2; + + + /*\ Now, fill the table: \*/ + + table->num_states = 0; + + /* Add turbo state if supported. */ + if (params.turbo.is_turbo) + table->states[table->num_states++] = params.turbo; + + /* Add HFM first. */ + table->states[table->num_states] = params.max; + /* Work around HFM and LFM having the same bus ratio. */ + if ((params.max.dynfsb == params.min.dynfsb) && + (params.max.nonint == params.min.nonint) && + (params.max.ratio == params.min.ratio)) + table->states[table->num_states].vid = params.min.vid; + ++table->num_states; + --states; + + /* Now, add all other normal states based on LFM (min). */ + const int power_step = power_diff2 / ratio_diff2; + const int vid_step = vid_diff2 / ratio_diff2; + const int ratio_step = step2 / 2; + int power = params.min.power + (states - 1) * power_step; + int vid = params.min.vid + (states - 1) * vid_step; + int ratio = params.min.ratio + (states - 1) * ratio_step; + for (; states > 0; --states) { + table->states[table->num_states++] = + (sst_state_t){ 0, 0, ratio, vid, 0, 0, power }; + power -= power_step; + vid -= vid_step; + ratio -= ratio_step; + } + + /* At last, add Super-LFM state if supported. */ + if (params.slfm.is_slfm) + table->states[table->num_states++] = params.slfm; +} diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index c3cd2d2..697c34a 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH + * 2012 secunet Security Networks AG * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,6 +20,11 @@ * MA 02110-1301 USA */ +#ifndef CPU_INTEL_SPEEDSTEP_H +#define CPU_INTEL_SPEEDSTEP_H + +#include <stdint.h> + /* Magic value used to locate speedstep configuration in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC @@ -39,3 +45,71 @@ #define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 +#define MSR_FSB_CLOCK_VCC 0xce +#define MSR_EXTENDED_CONFIG 0xee + + +typedef struct { + uint8_t dynfsb : 1; /* whether this is SLFM */ + uint8_t nonint : 1; /* add .5 to ratio */ + uint8_t ratio : 6; + uint8_t vid; + uint8_t is_turbo; + uint8_t is_slfm; + uint32_t power; +} sst_state_t; +#define SPEEDSTEP_RATIO_SHIFT 8 +#define SPEEDSTEP_RATIO_DYNFSB_SHIFT (7 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_DYNFSB (1 << SPEEDSTEP_RATIO_DYNFSB_SHIFT) +#define SPEEDSTEP_RATIO_NONINT_SHIFT (6 + SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_RATIO_NONINT (1 << SPEEDSTEP_RATIO_NONINT_SHIFT) +#define SPEEDSTEP_RATIO_VALUE_MASK (0x1f << SPEEDSTEP_RATIO_SHIFT) +#define SPEEDSTEP_VID_MASK 0x3f +#define SPEEDSTEP_STATE_FROM_MSR(val, mask) ((sst_state_t){ \ + 0, /* dynfsb won't be read. */ \ + ((val & mask) & SPEEDSTEP_RATIO_NONINT) ? 1 : 0, \ + (((val & mask) & SPEEDSTEP_RATIO_VALUE_MASK) \ + >> SPEEDSTEP_RATIO_SHIFT), \ + (val & mask) & SPEEDSTEP_VID_MASK, \ + 0, /* not turbo by default */ \ + 0, /* not slfm by default */ \ + 0 /* power is hardcoded in software. */ \ + }) +#define SPEEDSTEP_ENCODE_STATE(state) ( \ + ((uint16_t)(state).dynfsb << SPEEDSTEP_RATIO_DYNFSB_SHIFT) | \ + ((uint16_t)(state).nonint << SPEEDSTEP_RATIO_NONINT_SHIFT) | \ + ((uint16_t)(state).ratio << SPEEDSTEP_RATIO_SHIFT) | \ + ((uint16_t)(state).vid & SPEEDSTEP_VID_MASK)) +#define SPEEDSTEP_DOUBLE_RATIO(state) ( \ + ((uint8_t)(state).ratio * 2) + (state).nonint) + +typedef struct { + sst_state_t slfm; + sst_state_t min; + sst_state_t max; + sst_state_t turbo; +} sst_params_t; + +/* Looking at core2's spec, the highest normal bus ratio for an eist enabled + processor is 14, the lowest is always 6. This makes 5 states with the + minimal step width of 2. With turbo mode and super LFM we have at most 7. */ +#define SPEEDSTEP_MAX_NORMAL_STATES 5 +#define SPEEDSTEP_MAX_STATES (SPEEDSTEP_MAX_NORMAL_STATES + 2) +typedef struct { + /* Table of p-states for EMTTM and ACPI by decreasing performance. */ + sst_state_t states[SPEEDSTEP_MAX_STATES]; + int num_states; +} sst_table_t; + +void speedstep_gen_pstates(sst_table_t *); + +#define SPEEDSTEP_TURBO_POWER_MEROM 35000 +#define SPEEDSTEP_MAX_POWER_MEROM 35000 +#define SPEEDSTEP_MIN_POWER_MEROM 25000 +#define SPEEDSTEP_SLFM_POWER_MEROM 12000 +#define SPEEDSTEP_TURBO_POWER_PENRYN 35000 +#define SPEEDSTEP_MAX_POWER_PENRYN 35000 +#define SPEEDSTEP_MIN_POWER_PENRYN 15000 +#define SPEEDSTEP_SLFM_POWER_PENRYN 12000 + +#endif /* CPU_INTEL_SPEEDSTEP_H */

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New patch to review for coreboot: efb8ab0 Fix some indentation flaws and break very long lines
by Patrick Georgi 30 Oct '12

30 Oct '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1657 -gerrit commit efb8ab08a26c3ba23badc6080ce40351f1b8baee Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Sep 14 12:52:32 2012 +0200 Fix some indentation flaws and break very long lines Change-Id: I3efef6bc8f519382ffdd92eb10b4bcd1a4361ba9 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/cpu/intel/speedstep/acpi.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index d658c70..070f8d5 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -83,11 +83,12 @@ void generate_cpu_entries(void) for (cpuID=1; cpuID <=numcpus; cpuID++) { for (coreID=1; coreID<=cores_per_package; coreID++) { - if (coreID>1) { - pcontrol_blk = 0; - plen = 0; - } - len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen); + if (coreID>1) { + pcontrol_blk = 0; + plen = 0; + } + len_pr = acpigen_write_processor( + (cpuID - 1) * cores_per_package + coreID - 1, pcontrol_blk, plen); len_pr += acpigen_write_empty_PCT(); len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY); if ((count = get_cst_entries(&cst_entries)) > 0) @@ -115,19 +116,29 @@ void generate_cpu_entries(void) busratio_step <<= 1; num_states >>= 1; } - printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max); + printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", + num_states+1, busratio_min, busratio_max); int vid_step=(vid_max-vid_min)/num_states; int power_step=(power_max-power_min)/num_states; int clock_step=(clock_max-clock_min)/num_states; - len_ps = acpigen_write_package(num_states+1); // for Super LFM, this must be increases by another one - len_ps += acpigen_write_PSS_package(clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (busratio_max<<8)|(vid_max) /*control*/, (busratio_max<<8)|(vid_max) /*status*/); + len_ps = acpigen_write_package(num_states + 1); /* For Super LFM, this must + be increases by another one. */ + len_ps += acpigen_write_PSS_package( + clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, + (busratio_max << 8) | vid_max /*control*/, + (busratio_max << 8) | vid_max /*status*/); + int current_busratio=busratio_min+((num_states-1)*busratio_step); int current_vid=vid_min+((num_states-1)*vid_step); int current_power=power_min+((num_states-1)*power_step); int current_clock=clock_min+((num_states-1)*clock_step); int i; for (i=0;i<num_states; i++) { - len_ps += acpigen_write_PSS_package(current_clock /*mhz*/, current_power /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (current_busratio<<8)|(current_vid) /*control*/, (current_busratio<<8)|(current_vid) /*status*/); + len_ps += acpigen_write_PSS_package( + current_clock /*mhz*/, current_power /*mW*/, + 0 /*lat1*/, 0 /*lat2*/, + (current_busratio << 8) | current_vid /*control*/, + (current_busratio << 8) | current_vid /*status*/); current_busratio -= busratio_step; current_vid -= vid_step; current_power -= power_step; @@ -136,9 +147,9 @@ void generate_cpu_entries(void) len_ps--; acpigen_patch_len(len_ps); len_pr += acpigen_write_PPC(0); - len_pr += len_ps; - len_pr--; - acpigen_patch_len(len_pr); + len_pr += len_ps; + len_pr--; + acpigen_patch_len(len_pr); } } }

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New patch to review for coreboot: 6e5a8d2 Correct FSB reading in speedstep ACPI
by Patrick Georgi 30 Oct '12

30 Oct '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1656 -gerrit commit 6e5a8d23dff4c96065f4a67b25cad4897dd26f8e Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Sep 6 17:46:30 2012 +0200 Correct FSB reading in speedstep ACPI We parsed the MSR the wrong way, and didn't support some valid values. Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/cpu/intel/speedstep/acpi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 249d9e4..d658c70 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -49,13 +49,15 @@ static int determine_total_number_of_cores(void) static int get_fsb(void) { - u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7; + const u32 fsbcode = rdmsr(0xcd).lo & 7; switch (fsbcode) { case 0: return 266; case 1: return 133; case 2: return 200; case 3: return 166; + case 4: return 333; case 5: return 100; + case 6: return 400; } printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n"); return 200;

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New patch to review for coreboot: 065fde7 Merge cpu/intel/acpi.h into cpu/intel/speedstep.h
by Patrick Georgi 30 Oct '12

30 Oct '12

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1655 -gerrit commit 065fde704df295308e25c100cd622e4b55bbe2d8 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Oct 1 15:53:14 2012 +0200 Merge cpu/intel/acpi.h into cpu/intel/speedstep.h We had only some MSR definitions in there, which are used in speedstep related code. I think speedstep.h is the better and less confusing place for these. Change-Id: I1eddea72c1e2d3b2f651468b08b3c6f88b713149 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/cpu/intel/model_206ax/acpi.c | 1 - src/cpu/intel/model_6ex/model_6ex_init.c | 1 - src/cpu/intel/model_6fx/model_6fx_init.c | 1 - src/cpu/intel/speedstep/acpi.c | 1 - src/include/cpu/intel/acpi.h | 24 ------------------------ src/include/cpu/intel/speedstep.h | 7 +++++++ src/mainboard/intel/eagleheights/romstage.c | 2 +- 7 files changed, 8 insertions(+), 29 deletions(-) diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c index c8c30a4..80ed4ba 100644 --- a/src/cpu/intel/model_206ax/acpi.c +++ b/src/cpu/intel/model_206ax/acpi.c @@ -26,7 +26,6 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/turbo.h> #include <device/device.h> diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 1c8c72b..9dbb137 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -30,7 +30,6 @@ #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/acpi.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <usbdebug.h> diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 106719e..3cdfdc4 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/acpi.h> #include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index 5cc4c1d..249d9e4 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -25,7 +25,6 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> -#include <cpu/intel/acpi.h> #include <cpu/intel/speedstep.h> #include <device/device.h> diff --git a/src/include/cpu/intel/acpi.h b/src/include/cpu/intel/acpi.h deleted file mode 100644 index aac4592..0000000 --- a/src/include/cpu/intel/acpi.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Patrick Georgi <patrick(a)georgi-clan.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 00a5b9b..c3cd2d2 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -32,3 +32,10 @@ */ #define PMB1_BASE 0x800 + +/* Speedstep related MSRs */ +#define IA32_PLATFORM_ID 0x017 +#define IA32_PERF_STS 0x198 +#define IA32_PERF_CTL 0x199 +#define MSR_THERM2_CTL 0x19D +#define IA32_MISC_ENABLES 0x1A0 diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index a250c05..1e906ef 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -30,7 +30,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include <cpu/intel/acpi.h> +#include <cpu/intel/speedstep.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "reset.c"

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Patch set updated for coreboot: 65ef2bc tyan s8226: change lapic of lapic_cluster 0 to 0x30
by Siyuan Wang 30 Oct '12

30 Oct '12

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1652 -gerrit commit 65ef2bcf71650b60e3caa89ff86b93c61368a404 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Sun Oct 28 18:06:40 2012 +0800 tyan s8226: change lapic of lapic_cluster 0 to 0x30 amd family15 cpu has a lapic_cluster which is the same level with pci domain. Now, the lapic is 0x20 which is already taken by CPU. there are two CPUs on s8226 and each CPU has 8 cores. CPU 0 takes lapic from 0x10 to 0x17 and CPU 1 takes from 0x20 to 0x27. Now, the dmesg complains as follow: do_IRQ: 1.55 No irq handler for vector (irq -1) so I change lapic of lapic_cluster to 0x30. although I am not sure what's the exactly meaning of lapic_cluster, this is a workaround to solve this issue. Change-Id: Ie17820e0f11d11c35e7e2351a454fa8e823bbf2c Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/tyan/s8226/devicetree.cb | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index 4459019..c7bd8c3 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -19,8 +19,7 @@ chip northbridge/amd/agesa/family15/root_complex device lapic_cluster 0 on chip cpu/amd/agesa/family15 - device lapic 0x20 on end #f15 - #device lapic 0x10 on end #f10 + device lapic 0x30 on end end end device pci_domain 0 on

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coreboot October 2012