coreboot October 2012

coreboot@coreboot.org

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312 discussions

New patch to review for coreboot: 53ebf6d Reorder entries in .gitignore
by Stefan Tauner 26 Oct '12

26 Oct '12

Stefan Tauner (stefan.tauner(a)gmx.at) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1633 -gerrit commit 53ebf6d213b1ce3193a3338a06c84b57ada9b071 Author: Stefan Tauner <stefan.tauner(a)gmx.at> Date: Fri Oct 26 23:35:34 2012 +0200 Reorder entries in .gitignore Change-Id: I7fcf190ef92b06b857d8b85c3d27da9cdee071b1 Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at> --- .gitignore | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/.gitignore b/.gitignore index 8a0982a..9bd7108 100644 --- a/.gitignore +++ b/.gitignore @@ -5,16 +5,13 @@ build/ coreboot-builds/ payloads/external/FILO/filo/ payloads/external/SeaBIOS/seabios/ -util/crossgcc/tarballs/ -util/crossgcc/xgcc/ -util/crossgcc/Python-*/ util/crossgcc/acpica-unix-*/ util/crossgcc/binutils-*/ util/crossgcc/build-binutils/ +util/crossgcc/build-expat/ util/crossgcc/build-gcc/ util/crossgcc/build-gdb/ util/crossgcc/build-gmp/ -util/crossgcc/build-expat/ util/crossgcc/build-libelf/ util/crossgcc/build-mpc/ util/crossgcc/build-mpfr/ @@ -27,14 +24,17 @@ util/crossgcc/libelf-*/ util/crossgcc/mingwrt-*/ util/crossgcc/mpc-*/ util/crossgcc/mpfr-*/ +util/crossgcc/Python-*/ +util/crossgcc/tarballs/ util/crossgcc/w32api-*/ -*.o -*.elf +util/crossgcc/xgcc/ +*.\# +*.bin *.debug +*.elf +*.o *.out -*.\# *.swp -*.bin # # KDE editors create lots of backup files whenever @@ -62,11 +62,11 @@ util/msrtool/msrtool util/nrv2b/nrv2b util/nvramtool/.dependencies util/nvramtool/nvramtool -util/superiotool/superiotool util/optionlist/Options.wiki util/romcc/romcc -util/romcc/tests/*.S-O2-mmmx util/romcc/tests/fail_test*.S +util/romcc/tests/*.S-O2-mmmx +util/superiotool/superiotool util/vgabios/testbios documentation/*.aux

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Patch set updated for coreboot: cfd7a42 Drop get_smbios_data from chip_operations
by Kyösti Mälkki 26 Oct '12

26 Oct '12

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1492 -gerrit commit cfd7a424b8e18f8301dbcbd921eccfd8c57b0d16 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Aug 28 07:49:49 2012 +0300 Drop get_smbios_data from chip_operations We only want to add data once per device. Using the one in chip_operations is not very usable anyway, as different devices under the same chip directory would need to output entirely different sets of data. Change-Id: I96690c4c699667343ebef44a7f3de1f974cf6d6d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/smbios.c | 3 --- src/include/device/device.h | 3 --- src/mainboard/samsung/lumpy/mainboard.c | 28 ++++++++++++++-------------- 3 files changed, 14 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index a171707..8a8b2e4 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -283,9 +283,6 @@ static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *cu if (dev->ops && dev->ops->get_smbios_data) len += dev->ops->get_smbios_data(dev, handle, current); - - if (dev->chip_ops && dev->chip_ops->get_smbios_data) - len += dev->chip_ops->get_smbios_data(dev, handle, current); } return len; } diff --git a/src/include/device/device.h b/src/include/device/device.h index 642a4a6..2f0f799 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -17,9 +17,6 @@ struct smbus_bus_operations; struct chip_operations { void (*enable_dev)(struct device *dev); const char *name; -#if CONFIG_GENERATE_SMBIOS_TABLES - int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current); -#endif }; #define CHIP_NAME(X) .name = X, diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 9d44c9a..bd60a98 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -251,19 +251,6 @@ static void mainboard_init(device_t dev) lumpy_ec_init(); } -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = mainboard_init; -#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE - /* Install custom int15 handler for VGA OPROM */ - mainboard_interrupt_handlers(0x15, &int15_handler); -#endif - verb_setup(); -} - static int lumpy_smbios_type41_irq(int *handle, unsigned long *current, const char *name, u8 irq, u8 addr) { @@ -308,9 +295,22 @@ static int lumpy_onboard_smbios_data(device_t dev, int *handle, return len; } +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = lumpy_onboard_smbios_data; +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + struct chip_operations mainboard_ops = { CHIP_NAME("Samsung Lumpy ChromeBook") .enable_dev = mainboard_enable, - .get_smbios_data = lumpy_onboard_smbios_data, };

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Patch merged into coreboot/master: b640523 iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
by gerrit＠coreboot.org 26 Oct '12

26 Oct '12

the following patch was just integrated into master: commit b640523330fd7600ec96e81a04e37f338168aff3 Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:02:44 2012 +0200 iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned The PCI registers should be accessed aligned and 0x62 is not 32bit aligned therefore this patch changes it to a 16bit access. Change-Id: I00725a4569f471eedb061834f626911b42e734fb Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 20:43:06 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 21:07:23 2012, giving +1 See http://review.coreboot.org/1631 for details. -gerrit

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Patch merged into coreboot/master: bab8fab northbridge/sch: move the \n so it reads a little better
by gerrit＠coreboot.org 26 Oct '12

26 Oct '12

the following patch was just integrated into master: commit bab8fab0f11b511a5b4007e6cb0dc689b34e311b Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:03:14 2012 +0200 northbridge/sch: move the \n so it reads a little better Without this, the output of "Setting up ACPI…" continues right after the output of stepping. Change-Id: I2ad7cc3e55884ff509600b01274258b8e8250981 Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 19:22:27 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 20:52:29 2012, giving +1 See http://review.coreboot.org/1632 for details. -gerrit

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Patch merged into coreboot/master: b8d9fcb iwave/iWRainbowG6: remove USE_DCACHE_RAM
by gerrit＠coreboot.org 26 Oct '12

26 Oct '12

the following patch was just integrated into master: commit b8d9fcb56ded4896110febcdfdea61e46d60926c Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:02:10 2012 +0200 iwave/iWRainbowG6: remove USE_DCACHE_RAM This is not available as a config option anymore. Change-Id: Icac173d62928423a08671321ec21d4af82c5cded Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 19:22:02 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 20:22:53 2012, giving +1 See http://review.coreboot.org/1630 for details. -gerrit

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Patch merged into coreboot/master: 3646090 northbridge/sch: read the size of main memory from the proper register
by gerrit＠coreboot.org 26 Oct '12

26 Oct '12

the following patch was just integrated into master: commit 364609066b3ad1be8c5827405d6d3813c72a65a6 Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:01:45 2012 +0200 northbridge/sch: read the size of main memory from the proper register I don't know if the size main memory supposed to be in PCI(0,0) reg 0x9c but it is not written there. The size of memory is written in src/northbridge/intel/sch/raminit.c to SCH port(2, 8, 4) (look for "Setting up TOM"). Change-Id: Iea04a5185bda56f61d1c382533d5a0dac429ebbd Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 19:26:25 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 20:08:16 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Oct 26 19:28:13 2012, giving +2 See http://review.coreboot.org/1629 for details. -gerrit

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Patch merged into coreboot/master: 9ca468c northbridge/sch: Read the GPU memory from the correct PCI device
by gerrit＠coreboot.org 26 Oct '12

26 Oct '12

the following patch was just integrated into master: commit 9ca468c393884f342b167d4c2d4028b8d976e60b Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:01:17 2012 +0200 northbridge/sch: Read the GPU memory from the correct PCI device The GGC register which contains the size of memory that is used for GPU is in PCI device 2,0 and not 0,0. It is set to to 4MiB in src/mainboard/iwave/iWRainbowG6/romstage.c. Change-Id: Ie9f1cc60544ecd9cad770f34c83c33564a6129d4 Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 19:23:20 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 19:54:08 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Oct 26 19:27:40 2012, giving +2 See http://review.coreboot.org/1628 for details. -gerrit

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Patch merged into coreboot/master: 9e467ca northbridge/sch: don't overwrite hightables with GPU / TSEG memory
by gerrit＠coreboot.org 26 Oct '12

26 Oct '12

the following patch was just integrated into master: commit 9e467ca71a7eb2f1d723a7880a6eda635b4bc7eb Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:00:22 2012 +0200 northbridge/sch: don't overwrite hightables with GPU / TSEG memory Without this, the hightables are placed just before the end of memory. However we might have the GPU memory located at the exact same spot, that is in the last 4 MiB. So without this patch, this area won't remain marked as "CONFIGURATION TABLES" within coreboot's memory table but becomes "RESERVED" because it is part of the PCI(2,0) device. Change-Id: Ibd111c167c2f6ac03b0ba68581a74ecbd2c9c160 Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 19:25:24 2012, giving +2 Build-Tested: build bot (Jenkins) at Fri Oct 26 19:39:40 2012, giving +1 Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Oct 26 19:27:08 2012, giving +2 See http://review.coreboot.org/1627 for details. -gerrit

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problems with Gigabyte GA-MA785GM-US2H
by Anthoine Bourgeois 26 Oct '12

26 Oct '12

Hello, I tested the support of the Gigabyte GA-MA785GM-US2H. My main problem was that the integrated radeon doesn't work even with the VGA bios image I extracted from the official bios. I pass radeon.modeset=0 to access a console and flash my rom to get my old bios back. It worked as expected except that my MAC address has change to a strange value = 00:20:ed:ff:ff:ff. I read my bios and search this value, I found it and replaced it with the old one MAC but it's overwrite on the next reboot. Any idea on how this can append and how can change my MAC ? Regards, Anthoine

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Patch set updated for coreboot: b640523 iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned
by Sebastian Andrzej Siewior 26 Oct '12

26 Oct '12

Sebastian Andrzej Siewior (sebastian(a)breakpoint.cc) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1631 -gerrit commit b640523330fd7600ec96e81a04e37f338168aff3 Author: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> Date: Fri Oct 26 19:02:44 2012 +0200 iwave/iWRainbowG6: use 16bit access for a register which is not 32bit aligned The PCI registers should be accessed aligned and 0x62 is not 32bit aligned therefore this patch changes it to a 16bit access. Change-Id: I00725a4569f471eedb061834f626911b42e734fb Signed-off-by: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> --- src/mainboard/iwave/iWRainbowG6/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 833d930..83ae657 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -321,11 +321,11 @@ static void poulsbo_setup_Stage1Regs(void) static void poulsbo_setup_Stage2Regs(void) { - u32 reg32; + u16 reg16; printk(BIOS_DEBUG, "Reserved"); - reg32 = pci_read_config32(PCI_DEV(0, 0x2, 0), 0x62); - pci_write_config32(PCI_DEV(0, 0x2, 0), 0x62, (reg32 | 0x3)); + reg16 = pci_read_config16(PCI_DEV(0, 0x2, 0), 0x62); + pci_write_config16(PCI_DEV(0, 0x2, 0), 0x62, (reg16 | 0x3)); /* Slot capabilities */ pci_write_config32(PCI_DEV(0, 28, 0), 0x54, 0x80500); pci_write_config32(PCI_DEV(0, 28, 1), 0x54, 0x100500);

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coreboot October 2012