Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1638
-gerrit
commit dbe054c45f6fe714fe5d448a09983d90dfddf3b0
Author: Peter Stuge <peter(a)stuge.se>
Date: Sat Oct 27 14:20:10 2012 +0200
Hide all _ROM_RUN Kconfig options if the payload is SeaBIOS
The options are shown regardless of payload if CONFIG_EXPERT is set.
Change-Id: I12c81ce41a0e300e852481424eadc83f281863bf
Signed-off-by: Peter Stuge <peter(a)stuge.se>
---
src/devices/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 15db8e1..04f6f64 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -23,6 +23,7 @@ config VGA_ROM_RUN
bool "Run VGA Option ROMs"
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
+ depends on !PAYLOAD_SEABIOS || EXPERT
help
Execute VGA Option ROMs in coreboot if found. This is required
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
@@ -51,6 +52,7 @@ config PCI_ROM_RUN
bool "Run non-VGA Option ROMs"
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
+ depends on !PAYLOAD_SEABIOS || EXPERT
help
Execute non-VGA PCI Option ROMs in coreboot if found.
@@ -67,6 +69,7 @@ config ON_DEVICE_ROM_RUN
bool "Run Option ROMs on PCI devices"
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
+ depends on !PAYLOAD_SEABIOS || EXPERT
help
Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1637
-gerrit
commit 9ef50b72a0ca9140b2c0d02fd2e903fb79ebb981
Author: Peter Stuge <peter(a)stuge.se>
Date: Sat Oct 27 14:17:04 2012 +0200
Run option ROMs in coreboot by default only if the payload is not SeaBIOS
Change-Id: I29fb86ff3a3187b720ce5ef246c4eeee696ab5cd
Signed-off-by: Peter Stuge <peter(a)stuge.se>
---
src/devices/Kconfig | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 013ab9a..15db8e1 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -21,7 +21,8 @@
# TODO: Explain differences (if any) for onboard cards.
config VGA_ROM_RUN
bool "Run VGA Option ROMs"
- default y
+ default n if PAYLOAD_SEABIOS
+ default y if !PAYLOAD_SEABIOS
help
Execute VGA Option ROMs in coreboot if found. This is required
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
@@ -48,7 +49,8 @@ config S3_VGA_ROM_RUN
config PCI_ROM_RUN
bool "Run non-VGA Option ROMs"
- default y
+ default n if PAYLOAD_SEABIOS
+ default y if !PAYLOAD_SEABIOS
help
Execute non-VGA PCI Option ROMs in coreboot if found.
@@ -63,7 +65,8 @@ config PCI_ROM_RUN
config ON_DEVICE_ROM_RUN
bool "Run Option ROMs on PCI devices"
- default y
+ default n if PAYLOAD_SEABIOS
+ default y if !PAYLOAD_SEABIOS
help
Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
Peter Stuge (peter(a)stuge.se) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1636
-gerrit
commit 5498b3b93e8107a71692b41a7dc49c65fd878a9e
Author: Peter Stuge <peter(a)stuge.se>
Date: Sat Oct 27 13:45:51 2012 +0200
Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot
Also clarify that enabling these options is generally not desirable if
using SeaBIOS as payload since the option ROMs are run by SeaBIOS with
more complete BIOS interrupt services available than coreboot.
Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05
Signed-off-by: Peter Stuge <peter(a)stuge.se>
---
src/devices/Kconfig | 43 +++++++++++++++++++++++++++++++++----------
1 file changed, 33 insertions(+), 10 deletions(-)
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index d83d551..013ab9a 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -23,37 +23,60 @@ config VGA_ROM_RUN
bool "Run VGA Option ROMs"
default y
help
- Execute VGA Option ROMs, if found. This is required to enable
- PCI/AGP/PCI-E video cards.
+ Execute VGA Option ROMs in coreboot if found. This is required
+ to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
+ payload.
+
+ When using a SeaBIOS payload it runs all option ROMs with much
+ more complete BIOS interrupt services available than coreboot,
+ which some option ROMs require in order to function correctly.
+
+ If unsure, say N when using SeaBIOS as payload, Y otherwise.
config S3_VGA_ROM_RUN
bool "Re-run VGA Option ROMs on S3 resume"
default y
depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
help
- Execute VGA Option ROMs when coming out of an S3 resume.
+ Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
+
+ When using a SeaBIOS payload it runs all option ROMs with much
+ more complete BIOS interrupt services available than coreboot,
+ which some option ROMs require in order to function correctly.
+
+ If unsure, say N when using SeaBIOS as payload, Y otherwise.
config PCI_ROM_RUN
bool "Run non-VGA Option ROMs"
default y
help
- Execute non-VGA PCI Option ROMs, if found.
+ Execute non-VGA PCI Option ROMs in coreboot if found.
Examples include IDE/SATA controller Option ROMs and Option ROMs
for network cards (NICs).
+ When using a SeaBIOS payload it runs all option ROMs with much
+ more complete BIOS interrupt services available than coreboot,
+ which some option ROMs require in order to function correctly.
+
+ If unsure, say N when using SeaBIOS as payload, Y otherwise.
+
config ON_DEVICE_ROM_RUN
bool "Run Option ROMs on PCI devices"
default y
help
- Execute Option ROMs that are stored on PCI/PCIe/AGP devices.
+ Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
+
+ If disabled, only Option ROMs stored in CBFS will be executed by
+ coreboot. If you are concerned about security, you might want to
+ disable this option, but it might leave your system in a state of
+ degraded functionality.
- If disabled, only Option ROMs stored in CBFS will be executed. If
- you are concerned about security, you might want to disable this
- option, but it might leave your system in a state of degraded
- functionality.
+ When using a SeaBIOS payload it runs all option ROMs with much
+ more complete BIOS interrupt services available than coreboot,
+ which some option ROMs require in order to function correctly.
- If unsure, say Y
+ If unsure, say N when using SeaBIOS as payload, Y otherwise.
choice
prompt "Option ROM execution type"
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1634
-gerrit
commit b5473f0627febc162ac6fe037fe3bb4e845d47be
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Oct 10 23:14:28 2012 +0300
Add name field for device
The constant field "name" in chip_operations is common to multiple
different devices within a chip and cannot reflect the actual device
as found on the platform.
The intention is that a driver sets dev->name as part of the device
enumeration sequence with the detected hardware type and revision.
The field is for debug print use only.
Change-Id: Ib7bf90ba3c618ad0cb715d80d6a937ceaae0adcf
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/devices/device_util.c | 4 +++-
src/include/device/device.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 5cf5eab..224c58e 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -230,7 +230,9 @@ const char *dev_path(device_t dev)
const char *dev_name(device_t dev)
{
- if (dev->chip_ops && dev->chip_ops->name)
+ if (dev->name)
+ return dev->name;
+ else if (dev->chip_ops && dev->chip_ops->name)
return dev->chip_ops->name;
else
return "unknown";
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 7e07dc1..6ab2db4 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -104,6 +104,7 @@ struct device {
struct device_operations *ops;
#ifndef __PRE_RAM__
const struct chip_operations *chip_ops;
+ const char *name;
#endif
ROMSTAGE_CONST void *chip_info;
};
the following patch was just integrated into master:
commit 6e3b7cef795f0cad4a8b4003b6d65c0bf2f40bd1
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Mon Sep 24 10:58:41 2012 +0200
inteltool: Add output of 64bit registers in PMBASE
Output values of 64bit registers and fix settings for GPE0_EN for
ICH9/10.
Change-Id: I8ca6b32500331707670972b38466345f581844cd
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Build-Tested: build bot (Jenkins) at Fri Oct 26 16:44:27 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Oct 26 19:06:50 2012, giving +2
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sat Oct 27 02:54:23 2012, giving +2
See http://review.coreboot.org/1625 for details.
-gerrit
the following patch was just integrated into master:
commit 563dc5e980a6e9de9e55619932c96aac16c85632
Author: Nico Huber <nico.huber(a)secunet.com>
Date: Thu Aug 30 15:36:57 2012 +0200
libpayload: New AHCI, ATA and ATAPI drivers
This adds a new interface for storage devices. A driver for ATA and
ATAPI drives on AHCI host controllers comes along.
The interface is very simple and was designed to match FILO's needs.
It consists of three functions:
void storage_initialize(void);
Initializes controllers. Should be called once at startup.
storage_poll_t storage_probe(size_t dev_num);
with typedef enum {
POLL_NO_DEVICE = -2,
POLL_ERROR = -1,
POLL_NO_MEDIUM = 0,
POLL_MEDIUM_PRESENT = 1,
} storage_poll_t;
Looks for a drive with number dev_num (drives are counted from
zero) and polls for a medium in the drive if appropriate.
int storage_read_blocks512(size_t dev_num,
u64 start, size_t count,
unsigned char *buf);
Reads count blocks of 512 bytes from block start of drive dev_num
into buf.
Change-Id: I1c85796b7f8e379ff3817a61b1837636b57e182b
Signed-off-by: Nico Huber <nico.huber(a)secunet.com>
Build-Tested: build bot (Jenkins) at Fri Oct 26 15:46:59 2012, giving +1
Reviewed-By: Stefan Reinauer <stefan.reinauer(a)coreboot.org> at Fri Oct 26 19:08:37 2012, giving +2
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sat Oct 27 02:52:58 2012, giving +2
See http://review.coreboot.org/1622 for details.
-gerrit
the following patch was just integrated into master:
commit ad4885f9bffc6bb182c22d0db32face42a41f45a
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Oct 7 14:57:15 2012 +0200
Take care of NULL chip_ops->name
Change-Id: Ic44915cdb07e0d87962eff0744acefce2a4845a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-By: Patrick Georgi <patrick(a)georgi-clan.de> at Fri Oct 26 18:27:53 2012, giving +2
Build-Tested: build bot (Jenkins) at Fri Oct 26 17:16:23 2012, giving +1
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sat Oct 27 02:52:14 2012, giving +2
See http://review.coreboot.org/1626 for details.
-gerrit
the following patch was just integrated into master:
commit 53ebf6d213b1ce3193a3338a06c84b57ada9b071
Author: Stefan Tauner <stefan.tauner(a)gmx.at>
Date: Fri Oct 26 23:35:34 2012 +0200
Reorder entries in .gitignore
Change-Id: I7fcf190ef92b06b857d8b85c3d27da9cdee071b1
Signed-off-by: Stefan Tauner <stefan.tauner(a)gmx.at>
Build-Tested: build bot (Jenkins) at Sat Oct 27 00:04:10 2012, giving +1
Reviewed-By: Peter Stuge <peter(a)stuge.se> at Sat Oct 27 02:32:49 2012, giving +2
See http://review.coreboot.org/1633 for details.
-gerrit